CN101345014B - Electro-optical device, driving circuit, and electronic apparatus - Google Patents

Abstract

The invention provides an electro-optical device, a driving circuit and an electronic apparatus. Pixels (110) include liquid crystal capacitors and holding capacitors having one end connected to pixel electrodes and the other end connected to common electrodes corresponding to the first to 320th rows. A common electrode driving circuit (170) includes TFTs for individual rows. In a partial mode, when a period in which a level of a scanning signal is high is long, a control signal Vg-c is brought to a high level during the period so that the TFTs are turned on. Since gate voltages are applied to the TFTs (173, 174), a problem in that the gate voltages are reduced due to voltage leakage and the common electrodes (108) are brought into high-impedance states is avoided. Alternatively, potentials of the common electrodes (108) are fixed to a voltage of a common signal Vc, which is a low-level when positive-polarity writing is specified to all the rows and a high-level when negative-polarity writing is specified to all the rows.

Description

Electro-optical device, driving circuit and electronic equipment

Technical field

The present invention relates to suppress the technology of the demonstration inequality in the electro-optical device of liquid crystal etc.

Background technology

Known such technology, in the electro-optical device of liquid crystal etc., be provided with pixel capacitance (liquid crystal capacitance) accordingly with intersecting of sweep trace and data line, in order to suppress the voltage amplitude of data line when this pixel capacitance of AC driving, make common electrode individual to every sweep trace (every row), and sweep trace is being applied when selecting voltage, giving electric wire (with reference to patent documentation 1) with the corresponding common electrode of this sweep trace is connected in and writes the polarity correspondent voltage via transistor.

Patent documentation 1: the spy opens the 2005-300948 communique

But, in this technology, there is following problem, promptly above-mentioned transistor disconnects during sweep trace not being applied the non-selection of selecting voltage, so common electrode becomes the voltage nondeterministic statement (high impedance status) that does not have electrical connection.Therefore, common electrode is subjected to the change in voltage of data line, the influence of interference via stray capacitance, so voltage changes easily.If the common electrode variation in voltage, then its influence manifests line by line, so produce the demonstration inequality of striated in a lateral direction, display quality significantly descends.

Summary of the invention

The present invention makes in view of such situation, and one of its purpose is, a kind of formation that individually drives common electrode is provided, can suppresses to show electro-optical device, driving circuit and the electronic equipment of uneven generation.

To achieve these goals, the invention provides the driving circuit of electro-optical device, described electro-optical device has: the multi-strip scanning line; Many data lines; The a plurality of common electrodes that on each bar of described multi-strip scanning line, are provided with; And pixel; Described pixel was provided with accordingly with intersecting of described sweep trace and described data line, and each pixel comprises: the pixel switch element, and the one end is connected with described data line, and becomes conducting state when described sweep trace being applied selection voltage; And pixel capacitance, the one end is connected with the other end of described pixel switch element, and the other end is connected with described common electrode; Described pixel has and the corresponding gray scale of the sustaining voltage of this pixel capacitance; The driving circuit of described electro-optical device is characterised in that to possess: scan line drive circuit, and its order in accordance with regulations applies described selection voltage to described multi-strip scanning line; The common electrode drive circuit, it drives described a plurality of common electrodes each respectively; And data line drive circuit, it is via data line, to the corresponding pixel of the sweep trace that has applied described selection voltage, supply with data-signal with the gray scale correspondent voltage of this pixel; Wherein, described common electrode drive circuit has: on-off circuit, it is set to conducting or off-state according to the voltage that gate electrode kept, and this common electrode is applied the voltage of any side of low level side or high-order side when being set to described conducting state; First applies circuit, and it is when applying described selection voltage with the paired sweep trace of this common electrode, and the gate electrode of described on-off circuit is applied the forward voltage that described on-off circuit is set at conducting state; And second apply circuit, its described sweep trace is not applied select voltage during, when the indication that has via the control line of regulation, the gate electrode of described on-off circuit is applied described forward voltage.According to the present invention, even if after the selection voltage application that is through with to sweep trace, on-off circuit makes common electrode be in voltage to determine state, so prevent the common electrode potential change.

In the present invention, can constitute, described first applies circuit has first and transistor seconds, described on-off circuit has the 3rd and the 4th transistor, described second applies circuit has the 5th and the 6th transistor, the gate electrode of described the first transistor is connected with described sweep trace, first of its source electrode and the voltage of supplying with the side make described the 3rd transistor become conducting or off-state is connected to electric wire, the gate electrode of described transistor seconds is connected with described sweep trace, second of its source electrode and the voltage of supplying with the opposing party make described the 4th transistor become conducting or off-state is connected to electric wire, the described the 3rd transistorized gate electrode is connected with the drain electrode of described the first transistor, the 3rd of its source electrode and a side's who supplies with low level side or high-order side voltage is connected to electric wire, the described the 4th transistorized gate electrode is connected with the drain electrode of described transistor seconds, the 4th of its source electrode and the opposing party's who supplies with low level side or high-order side voltage is connected to electric wire, the the described the 3rd and the 4th transistor drain electrode is connected with described common electrode each other, the described the 5th transistorized gate electrode is connected with described control line, its source electrode and described first and second is connected for a side of electric wire, its drain electrode is connected with the described the 3rd transistorized gate electrode, the described the 6th transistorized gate electrode is connected with described control line, its source electrode and described first or second is connected for the opposing party of electric wire, and its drain electrode is connected with the described the 4th transistorized gate electrode.According to such formation, the composed component of common electrode drive circuit can similarly form with the pixel switch element.

At this, described common electrode drive circuit, in each of described sweep trace and common electrode, the described the 5th transistorized source electrode is connected in described first and gives electric wire, and the described the 6th transistorized source electrode is connected in described second and gives electric wire.

And then, preferably constitute, have: first pattern that effectively shows with whole pixels; And only use second pattern that effectively shows with the corresponding pixel of a part of sweep trace; Wherein, in described first pattern, described scan line drive circuit, implement described multi-strip scanning line is applied in order the action of described selection voltage with the cycle of regulation, when described sweep trace being applied selection voltage at every turn, give electric wire with making described the 3rd transistor become the voltage reversal of conducting state and off-state and being supplied to described first, at least one frame or more than the frame during, supply with a side's of described low level side or high-order side voltage to the described the 3rd to electric wire, make the described the 5th and the 6th transistor become the voltage of off-state to described control line supply, in described second pattern, described scan line drive circuit carries out described multi-strip scanning line is applied in order first action of described selection voltage with the cycle alternate repetition longer than the cycle of described regulation, apply second action of described selection voltage in order with sweep trace to a described part, the sweep trace to a described part apply described selection voltage during, when described first moves, apply a side who makes described the 3rd transistor become the voltage of conducting state or become the voltage of off-state to electric wire to described first, when described second moves, apply the opposing party who makes described the 3rd transistor become the voltage of conducting state or become the voltage of off-state to electric wire to described first, at least one frame or more than the frame during, supply with a side's of described low level side or high-order side voltage to the described the 3rd to electric wire, during beginning to described second action part or all from described first release, make the described the 5th and the 6th transistor become the voltage of conducting state to described control line supply, during in addition, make the described the 5th and the 6th transistor become the voltage of off-state to described control line supply.Constitute according to this, when in first pattern, being conceived to row of pixel, write reversal of poles because make line by line, thus this point improved with regard to display quality, preferred.In addition, in the present invention, so-called odd number, even number, but be to be used for determining the alternately relative notion of the row of arrangement.

In addition, described common electrode drive circuit, can also constitute, in described sweep trace and common electrode, the 5th transistorized source electrode of odd-numbered line is connected in described second and gives electric wire, the 6th transistorized source electrode of odd-numbered line is connected in described first and gives electric wire, and the 5th transistorized source electrode of even number line is connected in described first and gives electric wire, and the 6th transistorized source electrode of even number line is connected in described second and gives electric wire.

And then, preferably constitute, have: first pattern that effectively shows with whole pixels; And only use second pattern that effectively shows with the corresponding pixel of a part of sweep trace; In described first pattern, described scan line drive circuit, implement described multi-strip scanning line is applied in order the action of described selection voltage with the cycle of regulation, when described sweep trace being applied selection voltage at every turn, give electric wire with making described the 3rd transistor become the voltage reversal of conducting state and off-state and being supplied to described first, at least one frame or more than the frame during, supply with a side's of described low level side or high-order side voltage to the described the 3rd to electric wire, make the described the 5th and the 6th transistor become the voltage of off-state to described control line supply, in described second pattern, described scan line drive circuit carries out described multi-strip scanning line is applied in order first action of described selection voltage with the cycle alternate repetition longer than the cycle of described regulation, apply second action of described selection voltage in order with sweep trace to a described part, when described first and second action, when described sweep trace being applied selection voltage at every turn, give electric wire with making described the 3rd transistor become the voltage reversal of conducting state and off-state and being supplied to described first, at least one frame or more than the frame during, supply with a side's of described low level side or high-order side voltage to the described the 3rd to electric wire, during beginning to described second action part or all from described first release, make the described the 5th and the 6th transistor become the voltage of conducting state to described control line supply, during in addition, make the described the 5th and the 6th transistor become the voltage of off-state to described control line supply.According to this formation, even if in second pattern,, write reversal of poles because similarly make line by line with first pattern in when row of the pixel that is conceived to effectively show, thus improve this point with regard to display quality, preferred.

In addition, to achieve these goals, the invention provides the driving circuit of electro-optical device, described electro-optical device has: the multi-strip scanning line; Many data lines; The a plurality of common electrodes that on each bar of described multi-strip scanning line, are provided with; And pixel; Described pixel was provided with accordingly with intersecting of described sweep trace and described data line, and each pixel comprises: the pixel switch element, and the one end is connected with described data line, and becomes conducting state when described sweep trace being applied selection voltage; And pixel capacitance, the one end is connected with the other end of described pixel switch element, and the other end is connected with described common electrode; Described pixel has and the corresponding gray scale of the sustaining voltage of this pixel capacitance; The driving circuit of described electro-optical device is characterised in that to possess: scan line drive circuit, and its order in accordance with regulations applies described selection voltage to described multi-strip scanning line; The common electrode drive circuit, it drives described a plurality of common electrodes each respectively; And data line drive circuit, it is via data line, to the corresponding pixel of the sweep trace that has applied described selection voltage, supply with data-signal with the gray scale correspondent voltage of this pixel; Wherein, described common electrode drive circuit, for each described common electrode, have: on-off circuit, it is set to conducting or off-state according to the voltage that gate electrode kept, and this common electrode is applied the voltage of any side of low level side or high-order side when being set to described conducting state; First applies circuit, and it is when applying described selection voltage with the paired sweep trace of this common electrode, and the gate electrode of described on-off circuit is applied the forward voltage that described on-off circuit is set at conducting state; And second apply circuit, and it when the indication that has via the control line of regulation, applies the voltage of any side of described low level side or high-order side to each of described common electrode once more after the selection voltage application to described sweep trace finishes.According to the present invention, even if after the selection voltage application that is through with to sweep trace, on-off circuit makes common electrode be in voltage to determine state, so prevent the common electrode potential change.

In the present invention, can constitute, described first applies circuit has first and transistor seconds, described on-off circuit has the 3rd and the 4th transistor, described second applies circuit has the 5th transistor, in described the first transistor, its gate electrode is connected with described sweep trace, first of its source electrode and the voltage of supplying with the side make described the 3rd transistor become conducting or off-state is connected to electric wire, in described transistor seconds, its gate electrode is connected with described sweep trace, second of its source electrode and the voltage of supplying with the opposing party make described the 4th transistor become conducting or off-state is connected to electric wire, in described the 3rd transistor, its gate electrode is connected with the drain electrode of described the first transistor, the 3rd of its source electrode and a side's who supplies with low level side or high-order side voltage is connected to electric wire, in described the 4th transistor, its gate electrode is connected with the drain electrode of described transistor seconds, the 4th of its source electrode and the opposing party's who supplies with low level side or high-order side voltage is connected to electric wire, the the described the 3rd and the 4th transistor drain electrode is connected with described common electrode each other, in described the 5th transistor, its gate electrode is connected with described control line, its source electrode is connected with the signal wire of the voltage of any side of supplying with low level side or high-order side, and its drain electrode is connected with described common electrode.According to such formation, the composed component of common electrode drive circuit can similarly form with the pixel switch element.

At this, in the above-described configuration, the described the 5th transistorized source electrode is connected in common signal wire in each row of described sweep trace and common electrode.And then, preferably constitute, have: first pattern that effectively shows with whole pixels; And only use second pattern that effectively shows with the corresponding pixel of a part of sweep trace; Wherein, in described first pattern, described scan line drive circuit, implement described multi-strip scanning line is applied in order the action of described selection voltage with the cycle of regulation, when described sweep trace being applied selection voltage at every turn, give electric wire with making described the 3rd transistor become the voltage reversal of conducting state and off-state and being supplied to described first, at least one frame or more than the frame during, supply with a side's of described low level side or high-order side voltage to the described the 3rd to electric wire, make described the 5th transistor become the voltage of off-state to described control line supply, in described second pattern, described scan line drive circuit carries out described multi-strip scanning line is applied in order first action of described selection voltage with the cycle alternate repetition longer than the cycle of described regulation, apply second action of described selection voltage in order with sweep trace to a described part, the sweep trace to a described part apply described selection voltage during, when described first moves, apply a side who makes described the 3rd transistor become the voltage of conducting state or become the voltage of off-state to electric wire to described first, when described second moves, apply the opposing party who makes described the 3rd transistor become the voltage of conducting state or become the voltage of off-state to electric wire to described first, at least one frame or more than the frame during, supply with a side's of described low level side or high-order side voltage to the described the 3rd to electric wire, during beginning to described second action part or all from described first release, make described the 5th transistor become the voltage of conducting state to described control line supply, during in addition, make described the 5th transistor become the voltage of off-state to described control line supply.Constitute according to this, when in first pattern, being conceived to row of pixel, write reversal of poles, so display quality improves because make line by line.In addition, in the present invention, so-called odd number, even number, but be to be used for determining the alternately relative notion of the row of arrangement.

In addition, can also constitute, in described sweep trace and common electrode, the 5th transistorized source electrode of odd-numbered line is connected with first signal wire of a side's who supplies with low level side or high-order side voltage, and the 5th transistorized source electrode of even number line is connected with the secondary signal line of the opposing party's who supplies with low level side or high-order side voltage.And then, preferably constitute, have: first pattern that effectively shows with whole pixels; And only use second pattern that effectively shows with the corresponding pixel of a part of sweep trace; Wherein, in described first pattern, described scan line drive circuit, implement described multi-strip scanning line is applied in order the action of described selection voltage with the cycle of regulation, when described sweep trace being applied selection voltage at every turn, give electric wire with making described the 3rd transistor become the voltage reversal of conducting state and off-state and being supplied to described first, at least one frame or more than the frame during, supply with a side's of described low level side or high-order side voltage to the described the 3rd to electric wire, make described the 5th transistor become the voltage of off-state to described control line supply, in described second pattern, described scan line drive circuit carries out described multi-strip scanning line is applied in order first action of described selection voltage with the cycle alternate repetition longer than the cycle of described regulation, apply second action of described selection voltage in order with sweep trace to a described part, when described first and second action, when described sweep trace being applied selection voltage at every turn, give electric wire with making described the 3rd transistor become the voltage reversal of conducting state and off-state and being supplied to described first, at least one frame or more than the frame during, supply with a side's of described low level side or high-order side voltage to the described the 3rd to electric wire, during beginning to described second action part or all from described first release, make described the 5th transistor become the voltage of conducting state to described control line supply, during in addition, make described the 5th transistor become the voltage of off-state to described control line supply.According to this formation,,, write reversal of poles because similarly make line by line, so display quality further improves with first pattern in when row of the pixel that is conceived to effectively show even if in second pattern.

In addition, the present invention not only can comprise the driving circuit of electro-optical device, also can comprise electro-optical device.And then the present invention, not only can comprise electro-optical device, also can comprise electronic equipment with this electro-optical device.

Description of drawings

Fig. 1 is the figure of the formation of the related electro-optical device of expression first embodiment of the present invention.

Fig. 2 is the figure of the formation of the pixel in this electro-optical device of expression.

Fig. 3 is the planimetric map of wanting portion formation in the device substrate of this electro-optical device of expression.

Fig. 4 is the figure of action that is used to illustrate the full frame pattern of this electro-optical device.

Fig. 5 is the figure of the voltage waveform of the pixel electrode in this electro-optical device of expression.

Fig. 6 is the figure that is used to illustrate the action of this electro-optical device.

Fig. 7 is the figure of action that is used to illustrate the partial mode of this electro-optical device.

Fig. 8 is the figure of action that is used to illustrate the partial mode of this electro-optical device.

Fig. 9 is the figure of action that is used to illustrate the partial mode of this electro-optical device.

Figure 10 is the figure of the formation of the related electro-optical device of expression second embodiment of the present invention.

Figure 11 is the planimetric map of wanting portion formation in the device substrate of this electro-optical device of expression.

Figure 12 is the figure that is used to illustrate the action of this electro-optical device.

Figure 13 is the figure of action that is used to illustrate the partial mode of this electro-optical device.

Figure 14 is the figure of action that is used to illustrate the partial mode of this electro-optical device.

Figure 15 is the figure of action that is used to illustrate the partial mode of this electro-optical device.

Figure 16 is the figure of the formation of the related electro-optical device of expression application examples.

Figure 17 is the figure of formation of the pixel of the related electro-optical device of expression application examples.

Figure 18 is the figure of the formation of the related electro-optical device of expression first embodiment of the present invention.

Figure 19 is the figure of the formation of the pixel in this electro-optical device of expression.

Figure 20 is the planimetric map of wanting portion formation in the device substrate of this electro-optical device of expression.

Figure 21 is the planimetric map of wanting portion formation in the device substrate of this electro-optical device of expression.

Figure 22 is the figure of action that is used to illustrate the full frame pattern of this electro-optical device.

Figure 23 is the figure of the voltage waveform of the pixel electrode in this electro-optical device of expression.

Figure 24 is the figure that is used to illustrate the action of this electro-optical device.

Figure 25 is the figure of action that is used to illustrate the partial mode of this electro-optical device.

Figure 26 is the figure of action that is used to illustrate the partial mode of this electro-optical device.

Figure 27 is the figure of action that is used to illustrate the partial mode of this electro-optical device.

Figure 28 is the figure of the formation of the related electro-optical device of expression second embodiment of the present invention.

Figure 29 is the planimetric map of wanting portion formation in the device substrate of this electro-optical device of expression.

Figure 30 is the figure that is used to illustrate the action of this electro-optical device.

Figure 31 is the figure of action that is used to illustrate the partial mode of this electro-optical device.

Figure 32 is the figure of action that is used to illustrate the partial mode of this electro-optical device.

Figure 33 is the figure of action that is used to illustrate the partial mode of this electro-optical device.

Figure 34 is the figure of the formation of the related electro-optical device of expression application examples.

Figure 35 is the figure of formation of the pixel of the related electro-optical device of expression application examples.

Figure 36 is the figure that the mobile phone of the related electro-optical device of embodiment is used in expression.

Symbol description

10 electro-optical devices, 20 control circuits, 100 viewing areas, 108 common electrodes

110 pixels, 112 sweep traces, 114 data lines, 116 TFT

120 liquid crystal capacitances, 130 memory capacitance, 140 scan line drive circuits

161 first give electric wire for electric wire 163 the 3rd for electric wire 162 second

164 the 4th give electric wire 166 control lines for electric wire 165 the 5th

167 signal wires 170,170a, 170b common electrode drive circuit 171～176 TFT

190 data line drive circuits, 1200 mobile phones

Embodiment

Below, describe with reference to the accompanying drawing in the embodiments of the present invention.

At first, first embodiment of the present invention is described.Fig. 1 is the block diagram of the formation of the related electro-optical device of expression first embodiment of the present invention.

As shown in the drawing, electro-optical device 10 has viewing area 100, is the periphery in this viewing area 100, and the panel that disposes the peripheral circuit internally-arranged type of scan line drive circuit 140, common electrode drive circuit 170, data line drive circuit 190 constitutes.In addition, control circuit 20 is connected by for example FPC (flexible print circuit) substrate with the panel of above-mentioned peripheral circuit internally-arranged type.

Viewing area 100 is the zones of arranging pixel 110, and in the present embodiment, the mode of extending with (X) direction of being expert at is provided with from the sweep trace 112 of the 1st～320 row respectively, in addition, is provided with 240 column data lines in the mode of extending in row (Y) direction.And, with the sweep trace 112 of these the 1st～320 row and intersecting accordingly of the 1st～240 data line 114 that is listed as, be arranged with pixel 110 respectively.Therefore, in the present embodiment, in viewing area 100, pixel 110 is arranged in rectangular with vertical 320 row * horizontal strokes, 240 row, but the present invention is not limited to this arrangement.

In addition, in the present embodiment,, common electrode 108 is set on directions X respectively with extending for each bar of the 1st～320 sweep trace 112 of going.Therefore, for common electrode 108, each sweep trace 112 with the 1st～320 row is provided with accordingly respectively.

At this, the detailed formation of pixel 110 is described.Fig. 2 is the figure of the formation of remarked pixel 110, expression with i capable and below (i+1) row, j row of being adjacent and in corresponding 2 * 2 the formation of 4 pixels altogether of intersecting of right-hand (j+1) row that are adjacent.

In addition, i, (i+1) are the mark of general expression when arranging pixel 110 capable, i is 1,3,5 ..., the odd number arbitrarily in 319, and (i+1) be 2,4,6 with the continuous even number of i ..., the even number arbitrarily in 320.In addition, j, (j+1) are the mark of general expression when arranging the row of pixel 110, j is 1,3,5 ..., the odd number arbitrarily in 239, and (j+1) be with the continuous even number of j promptly 2,4,6 ..., the even number arbitrarily in 240.

Following only abbreviate as " TFT ") 116, liquid crystal capacitance (pixel capacitance) 120 and memory capacitance 130 as shown in Figure 2, each pixel 110 has: the thin film transistor (TFT) of the n channel-type that plays a role as the pixel switch element (thin film transistor:.About each pixel 110, same each other in the present embodiment formation, so with the pixel that is positioned at the capable j row of i is that representative describes, in the pixel 110 of the capable j row of this i, the sweep trace 112 that the gate electrode of TFT 116 and i are capable is connected, its source electrode is connected with the data line 114 of j row on the other hand, and its drain electrode is connected with an end of liquid crystal capacitance 120 and memory capacitance 130 respectively.In addition, an other end of liquid crystal capacitance 120 and an other end of memory capacitance 130 are connected with common electrode 108 respectively.

In addition, in Fig. 2, Yi, Y (i+1) represent sweep signal that the sweep trace 112 of i, (i+1) row is supplied with respectively, and in addition, Ci, C (i+1) represent the voltage of the common electrode 108 of i, (i+1) row respectively.About optical characteristics of these liquid crystal capacitances 120 etc., explanation hereinafter.

Return Fig. 1 and describe, control circuit 20 is exported various control signals and is carried out control of each one in the electro-optical device 10 etc.In addition, about control signal, suitably explanation hereinafter.

In addition, this electro-optical device 10 is with following two kinds of patterns action, promptly the pixel 110 of arranging with whole vertical 320 row * horizontal stroke, 240 row carry out in full frame pattern (first pattern) that image shows and the above-mentioned arrangement of use, and the corresponding pixel 110 of a part of sweep trace effectively show, and make other pixel not show the also partial mode (second pattern) of ineffective treatment.But, in the following description, by way of exception treat, and in principle the full frame pattern described about partial mode.

100 the periphery in the viewing area as mentioned above, is provided with the peripheral circuit of scan line drive circuit 140, common electrode drive circuit 170, data line drive circuit 190 etc.

Wherein, scan line drive circuit 140, under the full frame pattern, with sweep signal Y1, Y2, Y3 ..., Y320 is supplied to the 1st, 2,3 respectively ..., the sweep traces 112 of 320 row.Specifically, scan line drive circuit 140, as shown in Figure 4, in an image duration, press among Fig. 1 number from top to bottom the 1st, 2,3 ..., the orders of 320 row select sweep trace 112 line by line, to be made as the selection voltage Vdd suitable to the sweep signal of the sweep trace of having selected, will be made as the non-selection voltage suitable (earthing potential Gnd) to the sweep signal of in addition sweep trace with the L level with the H level.

At this, scan line drive circuit 140 for example, is shifted etc. in turn by the beginning pulsed D y that is supplied with by control circuit 20 according to clock enabling signal, make sweep signal Y1, Y2, Y3 ..., Y320 becomes the H level in proper order by this.In addition, in Fig. 4, it is identical from the timing that the L level becomes the H level with sweep signal to next sweep trace to be changed to the timing of L level from the H level to the sweep signal of certain sweep trace, but also can shorten become the H level during etc., be provided with at interval between regularly at these.

In the present embodiment, so-called 1 frame be meant in the full frame pattern, show 1 piece of image required during, be 16.7 milliseconds, as shown in Figure 4, except become the H level becomes the L level to sweep signal Y320 effective scanning from sweep signal Y1 during, the Fa, also comprise retrace interval in addition.In addition, in 1 frame in partial mode because there is as described later the situation that does not show 1 piece of pixel, thus also have in simple terms differ 16.7 milliseconds during situation.

In addition, also retrace interval can be set.In addition, the sweep trace 112 of 1 row is horizontal scan period (H) during selecteed.

On the other hand, scan line drive circuit 140, in partial mode, Fig. 7 for example described later in the frame waveform of the sweep signal Y1 in the full frame pattern～Y320, a part of, all or is only exporting the sweep signal that becomes the H level in the part to shown in Figure 9.

Common electrode drive circuit 170 in the present embodiment, is made of the group of the TFT 171～176 of and the n channel-type that is provided with corresponding with the common electrode 108 of the 1st to 320 row.

The connection of TFT 171～176, each row is identical in the present embodiment, so describe with i behavior representative, the gate electrode of the TFT 171 (the first transistor) that i is capable is connected in the capable sweep trace of i 112, its source electrode is connected in first and gives electric wire 161, and its drain electrode is connected in the gate electrode of TFT 173.The gate electrode of the TFT 172 (transistor seconds) that this i is capable is connected in the capable sweep trace of i 112, and its source electrode is connected in second and gives electric wire 162, and its drain electrode is connected in the gate electrode of TFT 174.

On the other hand, the source electrode of the TFT 173 that i is capable (the 3rd transistor) is connected in the 3rd and gives electric wire 163, the source electrode of the TFT 174 that this i is capable (the 4th transistor) is connected in the 4th and gives electric wire 164, and the drain electrode of TFT 173 and TFT 174 is connected to each other in the capable common electrode 108 of i.

And the gate electrode of the TFT 175 that i is capable (the 5th transistor) is connected in the 5th and gives electric wire 165 (control line), and its source electrode is connected in first and gives electric wire 161, and the drain electrode of its drain electrode and TFT171 is connected in the gate electrode of TFT 173 in the lump.The gate electrode of the TFT176 that this i is capable (the 6th transistor) also is connected in the 5th and gives electric wire 165, and its source electrode is connected in second and gives electric wire 162, and the drain electrode of its drain electrode and TFT 172 is connected in the gate electrode of TFT 174 in the lump.

Data line drive circuit 190, at being positioned at the pixel 110 that applies the sweep trace 112 of selecting voltage by scan line drive circuit 140, to data line 114 supply with the gray scale correspondent voltage of pixel promptly with by the specified data-signal that writes the polarity correspondent voltage of polarity specification signal Pol.

Data line drive circuit 190 has with the picture element matrix of vertical 320 row * horizontal strokes, 240 row and arranges corresponding storage area (omitting diagram), and in each storage area, the video data Da of the gray scale (brightness) of each self-corresponding pixel 110 is specified in storage.At this, data line drive circuit 190, before soon certain sweep trace 112 being applied selection voltage, read the video data Da of the pixel 110 that is positioned at this sweep trace 112 from storage area, and with its be transformed to by the specified gray scale of this video data of reading and write the polarity correspondent voltage, and select the timing of voltage as one man to be supplied to data line 114 with applying as data-signal.Data line drive circuit 190 is implemented this supply action to 1～240 row that are positioned at selected sweep trace 112 respectively.

In addition, the video data Da in that storage area is stored under the situation that displaying contents changes, rewrites from control circuit 20 supply addresses and video data Da after changing.In addition, data line drive circuit 190 under partial mode, moves as described later.

In addition, control circuit 20 in the timing that the logic level of clock signal C ly changes, is supplied with latch pulse Lp to data line drive circuit 190.As mentioned above, scan line drive circuit 140, by the beginning pulsed D y etc. that is shifted in turn according to clock signal C ly, with sweep signal Y1, Y2, Y3 ..., Y320 is made as the H level in order, so select sweep trace during beginning regularly be the timing that the logic level of clock signal C ly changes.Therefore, data line drive circuit 190, what for example select as can be known by continuous counter latch pulse Lp during 1 frame is the sweep trace of which row, and then the supply by latch pulse Lp is regularly, the beginning that can know its selection is regularly.

In addition, scan line drive circuit 140 even if under partial mode, is also implemented the shift motion of above-mentioned beginning pulsed D y etc., and only the part restriction is made as the sweep signal of H level.

Polarity specification signal Pol, in the present embodiment, under the full frame pattern, if H level, it then is the signal of specifying positive polarity to write to the pixel that is applied in the sweep trace of selecting voltage, if the L level then is the signal of specifying negative polarity to write to this pixel, be actually waveform as shown in Figure 4.Specifically, as shown in the drawing, during a certain frame (souvenir is " a n frame "), to odd number (1,3,5 ..., 319) sweep signal of sweep trace of row applies and becomes the H level when selecting voltage, to even number (2,4,6 ..., 320) sweep signal of the sweep trace of row applies and becomes the L level when selecting voltage.Therefore, in the present embodiment, under the full frame pattern, be the mode that writes the row counter-rotating that polarity reverses line by line (row counter-rotating, sweep trace counter-rotating) to pixel.

In addition, polarity specification signal Pol is under the full frame pattern, next frame (souvenir is " n+1 " frame), carry out logic inversion when same row carries out comparison, the reason that writes reversal of poles like this is in order to prevent because the deterioration that applies the liquid crystal that is caused of flip-flop.

In addition, polarity specification signal Pol, under partial mode, Fig. 7 is to shown in Figure 9 as described later, at the 1st to the 3rd frame is the L level, sweep signal in the 4th frame be the H level during become the H level, become the H level at the 7th to the 9th frame, the sweep signal in the 10th frame become the H level during become the L level.

At this, about the polarity that writes in the present embodiment, will be when keeping with the gray scale correspondent voltage at liquid crystal capacitance 120, the situation that the current potential that the current potential of pixel electrode 118 is compared common electrode 108 is in high-order side is called positive polarity, and the situation that will be in the low level side is called negative polarity.About voltage, unless otherwise specified, the L level of earthing potential Gnd and logic level is suitable, and as the benchmark of no-voltage.

Supply with signal Vg-a, Vg-b for electric wire 162 for electric wire 161 and second to first respectively by control circuit 20.At this, in the present embodiment, no matter under the full frame pattern or under partial mode, signal Vg-a and the same waveform of polarity specification signal Pol, signal Vg-b is the waveform of logic inversion polarity specification signal Pol.

The voltage Vdd suitable with the H level of logic level if put on the gate electrode of TFT 173,174, then is to be made as the forward voltage of conducting (ON) state between the source electrode of this TFT 173,174, the drain electrode.In addition, the L level is earthing potential Gnd, even if be to be applied in TFT173,174 gate electrode, is the off voltage of non-conduction (OFF) state between the source electrode of this TFT 173,174, the drain electrode.

Supply with shared signal Vc-a, Vc-b for electric wire 164 for electric wire 163 and the 4th to the 3rd respectively by control circuit 20.In the present embodiment, no matter under the full frame pattern or under partial mode, shared signal Vc-a is defined as voltage Vsl, and in addition, common voltage signal Vc-b is defined as voltage Vsh.Voltage Vsl, Vsh, (≤Vdd) such relation, voltage Vsl is the relatively low voltage of comparison with voltage Vsh (voltage Vsh is the relative higher voltage of comparison with voltage Vsl) (Gnd≤) Vsl＜Vsh.

In addition, supply with control signal Vg-c for electric wire 165 by 20 pairs the 5th of control circuits.Control signal Vg-c is the L level under the full frame pattern, and under partial mode, Fig. 7 is the H level at the 2nd, the 3rd, the 8th and the 9th frame only to shown in Figure 9 as described later.

Also have, the panel in the electro-optical device constitutes, a pair of substrate maintenance certain clearance applying that device substrate and relative substrate are constituted and enclose liquid crystal in this gap.In addition, on device substrate, be formed with described sweep trace 112, data line 114, common electrode 108, pixel electrode 118 and TFT 116,171 to 176, fit in the mode that electrode forming surface is relative with relative substrate.Fig. 3 plane earth is represented the viewing area 100 in this formation and the boundary vicinity of common electrode drive circuit 170.

According to Fig. 3 also as can be known, viewing area 100 is direction of an electric field that liquid crystal is applied FFS (fringe field switching, fringe field switching) patterns as the distortion of the IPS pattern of real estate direction.In addition, in the present embodiment, TFT 116,171 to 176 is amorphous silicon types, and its gate electrode is to compare the bottom gate polar form that semiconductor layer is positioned at downside (paper inboard).

Specifically, by becoming (the 1st) ITO (indiun tin oxide of first conductive layer, the indium sb oxide) Ceng composition, form the electrode 108f of rectangular shape, and then the composition of the grid electrode layer by becoming second conductive layer, form the grid wiring of sweep trace 112, bridging line 108e etc., be formed with gate insulating film (omitting diagram) thereon, and the semiconductor layer of TFT forms island.Then; forming protection insulation course (omitting diagram) afterwards; the composition of (the 2nd) the ITO layer by becoming the 3rd conductive layer; form the pixel electrode 118 of broach shape; and then the composition of the metal level by becoming the 4th conductive layer forms source electrode, the drain electrode of TFT; and form data line 114, first and give electric wire 165 for electric wire 164 and the 5th for electric wire the 163, the 4th for electric wire the 162, the 3rd for electric wire 161, second, also have various connection electrode.

At this, the common electrode 108 among Fig. 1 and Fig. 2 in Fig. 3, is divided into the bridging line 108e that extends in parallel with sweep trace 112 and via the electrode 108f of the rectangular shape of the stacked pixel electrode 118 of protection insulation course.At this, be positioned at each other with the bridging line 108e of delegation and electrode 108f, have the part that partially overlaps mutually, conduct.Therefore, be positioned at bridging line 108e and electrode 108f with delegation, identical aspect electric, there is no need to distinguish, so only otherwise the explanation that relates to the structure aspect is not just distinguished both, nonoculture is a common electrode 108.

In the present embodiment, memory capacitance 130 is the capacitive components that lit-par-lit structure produced that clipped the protection insulation course by electrode 108f and pixel electrode 118.In addition, in the gap of device substrate and relative substrate, also enclose liquid crystal, so between pixel electrode 118 and electrode 108f, also by the structure generation capacitive component that clips as the liquid crystal of dielectric.In the present embodiment, will be by capacitive component that this liquid crystal constituted as liquid crystal capacitance 120.

In this constituted, the corresponding electric field of sustaining voltage with the shunt capacitance of liquid crystal capacitance 120 and memory capacitance 130 produced along the device substrate face and on the direction vertical with the broach of pixel electrode 118, and the state of orientation of liquid crystal is changed.Thus, by the light quantity of polariton (omit diagram), the effective value that becomes with this sustaining voltage is worth accordingly.

In addition, in the present embodiment,,, then can also be other pattern if the electronics equivalent electrical circuit is a circuit as shown in Figure 2 though, can also be the IPS pattern as the FFS pattern.

At this, the sustaining voltage of above-mentioned shunt capacitance is the potential difference of pixel electrode 118 and common electrode 108 (electrode 108f), so for the pixel with the capable j row of i is made as the target gray scale, as long as the capable sweep trace 112 of i is applied selection voltage Vdd so that TFT 116 becomes conducting (ON) state, and will make above-mentioned potential difference become data-signal Xj with the voltage of the corresponding value of the gray scale of pixel, the data line 114 that is listed as via j and be supplied to pixel electrode 118 at the TFT 116 of the capable j row of i conducting and get final product.

In addition, in the present embodiment, for the convenience that illustrates, be made as normal black pattern, if promptly this voltage effective value is near zero, then the optical transmission rate becomes minimum and carries out black display, on the other hand along with voltage effective value increases, the light quantity of transmission also increases, and the white that finally becomes the transmissivity maximum shows.

In addition, so the data line 114 of the common electrode 108 of each row and the 1st to 240 row as shown in phantom in Figure 2, carries out capacitive coupling via stray capacitance mutually via intersections such as gate insulating films.

Formation shown in Figure 3 as just an example, about the type of TFT, can also be other structure, and for example the configuration from gate electrode can be used as the top grid type, can be used as the polysilicon type from technology.In addition, can constitute, the element of common electrode drive circuit 170 is not implanted substrate with viewing area 100 with same technology but the IC chip is installed on the device substrate yet.

When being installed to the IC chip on the device substrate, scan line drive circuit 140, common electrode drive circuit 170 and data line drive circuit 190 can be integrated into semi-conductor chip together, also can be used as independent separately chip.On the other hand, about control circuit 20, also can be the formation of implant element substrate.

In addition, about present embodiment, can be transmission-type, reflection-type etc., can also be so-called semi-transparent semi with both combinations of transmission-type and reflection-type.Therefore, do not mention reflection horizon etc. especially.

Then, the situation to the full frame pattern in the action of the related electro-optical device 10 of present embodiment describes.

As mentioned above, in the present embodiment, when being made as the full frame pattern, control circuit 20 in the n frame, is distinguished output polarity specification signal Pol, signal Vg-a, Vg-b as shown in Figure 4, shared signal Vc-a is fixed as voltage Vsl, shared signal Vc-b is fixed as voltage Vsh.

In the n frame,, at first will become the H level to the sweep signal Y1 of the 1st sweep trace 112 of going by scan line drive circuit 140.In addition, in the n frame, because specify positive polarity to write in odd-numbered line, when sweep signal Y1 becomes in the timing of H level output latch pulse Lp, data line drive circuit 190, will with voltage Vsl be benchmark exceed by the 1st row the 1st, 2,3 ..., data-signal X1, the X2 of the voltage of the high-order side of the specified voltage of the video data Da of picture element signals of 240 row, X3 ..., X240, be supplied to the 1st, 2,3 respectively ..., the data lines 114 of 240 row.Thus, for example, being supplied to the data-signal Xj of the data line 114 of j row, is that comparison with voltage Vsl exceeds the voltage by the high-order side of the specified voltage of the video data Da of the pixel 110 of 1 row j row.

When sweep signal Y1 becomes the H level, the TFT116 conducting of 1 row 1 row to the pixel of 1 row, 240 row, so to their pixel electrode 118 apply data-signal X1, X2, X3 ..., X240.

On the other hand, sweep signal Y1 become the H level during, in common electrode drive circuit 170, the 1st the row TFT 171,172 conductings.At this, sweep signal Y1 become the H level during, being supplied to the first signal Vg-a to electric wire 161 is the H level, being supplied to the second signal Vg-b to electric wire 162 is the L level, so conducting by the 1st TFT 171,172 that goes, respectively the gate electrode of the 1st TFT 173 that goes is applied the forward voltage of H level, the gate electrode of TFT 174 is applied the off voltage of L level.Therefore, the TFT 173,174 of the 1st row, respectively conducting, disconnection, thus the common electrode 108 of the 1st row, owing to be connected to electric wire 163 and become voltage Vsl with the 3rd.

Therefore, 1 row 1 row to the liquid crystal capacitance 120 of 1 row, 240 row and the shunt capacitance of memory capacitance 130, are write respectively the voltage with the corresponding positive polarity of gray scale.In addition, under the full frame pattern, the TFT 175,176 of all row disconnects, so do not become the conducting of decision TFT 173,174 and the reason of off-state.

Then, sweep signal Y1 becomes the L level, and sweep signal Y2 becomes the H level on the other hand.

At this, when sweep signal Y1 became the L level, the TFT 116 in the pixel that 1 row, 1 row to 1 row 240 is listed as disconnected.Therefore, to the pixel 110 of 1 row, 240 row, each pixel electrode 118 becomes high impedance status at 1 row, 1 row.

On the other hand, in common electrode drive circuit 170, because the TFT 171,172 of the 1st row also disconnects, so the gate electrode of TFT 173,174 becomes high impedance status.But, because TFT173,174 gate electrode, by its stray capacitance remain on be about to become the state of high impedance status, promptly be respectively the state of H, L level, so TFT 173,174 continues to remain conducting, off-state.Therefore, the common electrode 108 of the 1st row even if sweep signal Y1 becomes the L level, still continues to be connected in the 3rd and gives electric wire 163, so keep voltage Vsl.Therefore, the other end of the liquid crystal capacitance 120 that 1 row, 1 row to 1 row 240 is listed as and the shunt capacitance of memory capacitance 130 is kept voltage Vsl, so the voltage status that writes does not continue with changing.

In addition, in the n frame, because specify negative polarity to write in even number line, when sweep signal Y2 becomes in the timing of H level output latch pulse Lp, data line drive circuit 190, output with voltage Vsh be benchmark low by the 2nd row the 1st, 2,3 ..., data-signal X1, the X2 of the voltage of the low level side of the specified voltage of the video data Da of picture element signals of 240 row, X3 ..., X240.Thus, for example, be supplied to the data-signal Xj of the data line 114 of j row, be comparison with voltage Vsh low by the voltage of the low level side of the specified voltage of the video data Da of the pixel 110 of 2 row j row.

When sweep signal Y2 becomes the H level, the TFT116 conducting of 2 row 1 row to the pixel of 2 row, 240 row, so to their pixel electrode 118 apply data-signal X1, X2, X3 ..., X240.

On the other hand, sweep signal Y2 become the H level during, in common electrode drive circuit 170, the 2nd the row TFT 171,172 conductings.At this, sweep signal Y2 become the H level during, will be supplied to first respectively and switch to the L level for the signal Vg-a of electric wire 161, switch to the H level for the signal Vg-b of electric wire 162 with being supplied to second, so the 2nd the row TFT 173,174, with the 1st the row opposite, respectively the disconnection, conducting.Therefore, the common electrode 108 of the 2nd row is owing to be connected and become voltage Vsh to electric wire 164 with the 4th.

Therefore, to the liquid crystal capacitance 120 of 2 row, 1 row～2 row, 240 row and the shunt capacitance of memory capacitance 130, write voltage respectively with the corresponding negative polarity of gray scale.

Then, sweep signal Y2 becomes the L level, and sweep signal Y3 becomes the H level on the other hand.At this, when sweep signal Y2 became the L level, the TFT 116 in the pixel of 2 row, 1 row～2 row, 240 row disconnected, so in each pixel 110 of these 2 row, 1 row～2 row, 240 row, each pixel electrode 118 becomes high impedance status.

On the other hand, in common electrode drive circuit 170, the TFT 171,172 of the 2nd row also disconnects, so the gate electrode of TFT 173,174 becomes high impedance status, but because its stray capacitance, be maintained at L, H level respectively, so the TFT 173,174 of the 2nd row continues to keep disconnection, conducting state.Therefore, the common electrode 108 of the 2nd row, even if the selection of the sweep trace of the 2nd row finishes, sweep signal Y2 becomes the L level, still continues to be connected in the 4th and gives electric wire 164, so keep voltage Vsh.

Therefore, the other end of the liquid crystal capacitance 120 that 2 row, 1 row to 2 row 240 are listed as and the shunt capacitance of memory capacitance 130 is kept voltage Vsh, so the voltage status that writes does not continue with changing.

In addition, when sweep signal Y3 becomes the H level, to the liquid crystal capacitance 120 of the 3rd row and the shunt capacitance of memory capacitance 130, write voltage respectively with the corresponding positive polarity of gray scale, then, when sweep signal Y4 becomes the H level,, write voltage respectively with the corresponding negative polarity of gray scale to the liquid crystal capacitance 120 of the 4th row and the shunt capacitance of memory capacitance 130.

Below, repeat same action up to the 320th row, thus, in the n frame, to the liquid crystal capacitance 120 of odd-numbered line and the shunt capacitance of memory capacitance 130, write the voltage with the corresponding positive polarity of gray scale respectively,, write voltage respectively with the corresponding negative polarity of gray scale to the liquid crystal capacitance 120 of even number line and the shunt capacitance of memory capacitance 130.Thus, in the shunt capacitance in whole pixels, write respectively and the gray scale correspondent voltage, so in viewing area 100, show the image of 1 piece (frame).

In ensuing (n+1) frame, polarity specification signal Pol, signal Vg-a, there is inverse relation in the logic level of Vg-b and n frame before, when so the sweep trace 112 of odd-numbered line is selected, with the corresponding common electrode 108 of the sweep trace of this selecteed odd-numbered line, be connected for electric wire 164 to become voltage Vsh with the 4th, even and if this sweep trace is non-selection (sweep signal is the L level), still keep this connection status, on the other hand, when the sweep trace 112 of even number line is selected, with the corresponding common electrode 108 of the sweep trace of this selecteed even number line, be connected for electric wire 163 to become voltage Vsl with the 3rd, even and if this sweep trace is non-selection, still keep this connection status.

Therefore, in (n+1) frame, to the liquid crystal capacitance 120 of odd-numbered line and the shunt capacitance of memory capacitance 130, write voltage respectively with the corresponding negative polarity of gray scale, to the shunt capacitance of even number line, write the voltage with the corresponding positive polarity of gray scale respectively, keep the voltage status that writes respectively.

At this,, describe with reference to Fig. 5 for writing of the related voltage of present embodiment.Fig. 5 is that (i, (i+1 is j) with the figure of the relation of each sweep signal Yi, Y (i+1) j) and (i+1) go voltage Pix in the pixel electrode 118 of j row for voltage Pix in the pixel electrode 118 of the capable j of expression i row.In addition, the vertical engineer's scale of expression voltage in Fig. 5, the vertical engineer's scale of comparing for convenience among Fig. 4 amplifies.

In the n frame, specify positive polarity to write at the capable pixel of odd number i, so sweep signal Yi become the H level during, to the data line 114 of j row, supply with and compare this voltage Vsl and exceed data-signal Xj with the voltage (usefulness ↑ expression in Fig. 5) of the high-order side of the gray scale correspondent voltage of the pixel of the capable j row of i.Thus, in the shunt capacitance of the liquid crystal capacitance 120 of the capable j of i row and memory capacitance 130, write the potential difference of the voltage Vsl of the voltage of data-signal Xj and common electrode 108, promptly with the corresponding positive polarity voltage of gray scale.

At this, when sweep signal Yi became the L level, the pixel electrode 118 of the capable j row of i became high impedance status.Relative therewith, the common electrode 108 that odd number i is capable when sweep signal Yi becomes the H level, is connected in the 3rd and gives electric wire 163 in the n frame, so become voltage Vsl, this connection status lasts till when sweep signal Yi becomes the H level once more in ensuing (n+1) frame.Therefore, voltage Pix (the i of the pixel electrode 118 of the capable j row of i, j), therefore the not change of the voltage (voltage of data-signal Xj) when sweep signal Yi becomes the H level does not exert an influence to the voltage effective value that shunt capacitance kept (dash area) by liquid crystal capacitance 120 and memory capacitance 130.

In addition, in the n frame, specify negative polarity to write at the pixel of even number (i+1) row, so go through sweep signal Y (i+1) become the H level during, to the data line 114 of j row, supply with compare this voltage Vsh low with (i+1) go the data-signal Xj of voltage (usefulness ↓ expression in Fig. 5) of low level side of gray scale correspondent voltage of the pixel that j is listed as.Thus, in the shunt capacitance of the liquid crystal capacitance 120 of (i+1) row j row and memory capacitance 130, write and the corresponding reverse voltage of gray scale.In addition, the common electrode 108 of even number (i+1) row, in the n frame when sweep signal Y (i+1) becomes the H level, be connected in the 4th and give electric wire 164, so become voltage Vsh, this connection status lasts till that sweep signal Y (i+1) becomes the H level once more in ensuing (n+1) frame, so, voltage Pix (i+1, j), therefore the not change of the voltage (voltage of data-signal Xj) when sweep signal Y (i+1) becomes the H level does not exert an influence to the voltage effective value (dash area) that is kept by liquid crystal capacitance 120 and memory capacitance 130.

And, in ensuing (n+1) frame, write reversal of poles, write so implement negative polarity at the capable pixel of odd number i respectively, implement positive polarity at the pixel of even number (i+1) row and write.

So, in the present embodiment, under the full frame pattern, write polarity and reverse by every sweep trace.

According to such embodiment, specified the common electrode 108 of the row that positive polarity writes, when selecting the sweep trace 112 of this row, become relatively low voltage Vsl, to exceed with the voltage of the high-order side of gray scale correspondent voltage than this voltage and supply with as data-signal, on the other hand, specified the common electrode 108 of the row that negative polarity writes, when selecting the sweep trace 112 of this row, become relative higher voltage Vsh, will than this voltage low supply with as data-signal with the voltage of the low level side of gray scale correspondent voltage.

Therefore, the voltage amplitude of data-signal, the situation narrow certain with the voltage of common electrode 108, so suppressed the desired resistance to pressure of composed component of data line drive circuit 190, can correspondingly seek the summary that constitutes, and also can suppress because change in voltage and the electric energy that consumes in vain.

But, the common electrode 108 (bridging line 108e) of each row, as mentioned above via the data line 114 and the intersection such as gate insulating film of 1 to 240 row, so the change in voltage of these data lines 114, be that the variation of data-signal X1 to X240 is passed to common electrode 108 via stray capacitance.

Therefore, common electrode 108 with which part is not electrically connected, and then is subjected to the influence that the change in voltage (change in voltage of data-signal X1 to X240) of each data line is produced, its potential change.Common electrode 108, independent line by line in the present embodiment, so common electrode carries out potential change with different line by line amounts, there is the possibility of baneful influence higher to display quality.

Relative therewith, in the present embodiment, such as odd number i is capable, for example in the n frame when sweep signal Yi becomes the H level, TFT 171,172 conductings that i is capable, thereby make TFT 173,174 conductings, disconnection, and at the gate electrode of TFT 173,174 parasitic electric capacity, write H, L level respectively, thus, even if when sweep signal Yi becomes the L level, still keep the capable TFT of i 173,174 conductings, off-state, as a result, continue capable common electrode 108 of odd number i and the 3rd state of being connected for electric wire 163.On the other hand, in the n frame, the common electrode that continues even number (i+1) row is connected in the 4th state to electric wire 164.Therefore, in the present embodiment, the common electrode 108 of each row is in the state that applies voltage Vsl or voltage Vsh usually, do not become high impedance status, so the reduction by the display quality that variation in voltage caused of common electrode can be prevented trouble before it happens.

Then, the action to partial mode describes.Fig. 6 is the figure of an example of the action of each frame under the situation of expression partial mode, in the present embodiment, under partial mode, implements 12 actions that frame is 1 unit with the from the 1st to the 12nd frame.

In this example, be illustrated in the 1st～80 row and the 161st～320 is gone as non-display line, make and the corresponding pixel ineffective treatment of this non-display line, go as display line the 81st～160, only use under the situation about effectively showing with the corresponding pixel of this display line, at the pixel of each sweep trace that is positioned at the 1st～320 row, what kind of polarity to carry out voltage with and write.

In addition, under partial mode, about being positioned at the pixel of display line, the situation that has any one two values of white of carrying out independent conducting or the black that disconnects to show, but at this, the situation of carrying out the gray scale demonstration is described.

In the drawings, with+be positive polarity ,-be negative polarity, the situation that voltage writes is carried out in expression respectively, but * expression do not carry out the state that voltage writes.

At this, the first and the 7th frame in partial mode, the 1st～80 row and the 161st～320 row at non-display line, the voltage that carries out negative polarity and positive polarity respectively writes, but this voltage writes, to show invalidly in order making, to write forcibly and the suitable voltage of black (disconnection) at the pixel of non-display line.On the other hand, at the 1st, the 4th, the 7th and the 10th frame of partial mode, the 81st～160 row to display line carries out voltage with the order of negative polarity, positive polarity, positive polarity and negative polarity respectively and writes.Therefore, in the present embodiment, under partial mode, adjacent lines each other to write polarity identical mutually.

With reference to Fig. 7～Fig. 9 the waveform of sweep signal under the represented partial mode of such Fig. 6 etc. is described.At this, Fig. 7 is the figure of waveform etc. of the sweep signal Y1～Y320 of expression the 1st～the 4th frame, and Fig. 8 makes the figure of waveform etc. of the sweep signal Y1～Y320 of expression the 5th～the 8th frame, and Fig. 9 is the figure of waveform etc. of the sweep signal Y1～Y320 of expression the 9th～the 12nd frame.

As shown in Figure 7, in the 1st frame of partial mode, sweep signal Y1～Y320, identical with the full frame pattern.But, in the present embodiment, be fixed as the L level at the 1st frame Semi-polarity specification signal Pol, so in the non-display line of the 1st～80 row and the 161st～320 row, write the suitable voltage of black (disconnection) with negative polarity, display line at the 81st～160 row writes the gray scale correspondent voltage with negative polarity.

In the second and the 3rd frame under partial mode, sweep signal Y1～Y320 does not become the H level, therefore, does not implement any write activity.

In the 4th frame under partial mode, only the related sweep signal Y81～Y160 of display line becomes the H level in order.In addition, in the 4th frame, sweep signal Y81～Y160 become the H level during, polarity specification signal Pol becomes the H level, so write gray scale correspondent voltage with positive polarity at the display line of the 81st～160 row.

Then, as shown in Figure 8, in the 5th and the 6th frame under partial mode, with the 2nd and the 3rd frame similarly sweep signal Y1～Y320 do not become the H level, therefore, do not implement any write activity.

In the 7th frame, sweep signal Y1～Y320 is identical with the full frame pattern.But, in the present embodiment, be fixed on the H level at the 7th frame Semi-polarity specification signal Pol, so in the non-display line of the 1st～80 row and the 161st～320 row, write the suitable voltage of black (disconnection) with positive polarity, display line at the 81st～160 row writes the gray scale correspondent voltage with positive polarity.

In the 8th frame and the 9th frame shown in Figure 9, sweep signal Y1～Y320 does not become the H level, therefore, does not implement any write activity.In the 10th frame under partial mode, only the related sweep signal Y81～Y160 of display line becomes the H level in order.In addition, in the 10th frame, sweep signal Y81～Y160 become the H level during, polarity specification signal Pol becomes the L level, so write gray scale correspondent voltage with negative polarity at the display line of the 81st～160 row.In addition, in the 11st frame and the 12nd frame, sweep signal Y1～Y320 does not become the H level, therefore, does not implement any write activity.

Under the full frame pattern, implementing voltage frame by frame writes, but under partial mode, off voltage at the pixel of non-display line writes, implement with 1 such ratio of per 6 frames, the cycle that writes at the voltage of display line is to implement with 1 such ratio of per 3 frames, writes the electric energy that is consumed so suppress voltage.

But, under the full frame pattern, in common electrode drive circuit 170, the TFT 173,174 that for example i is capable, remain on conducting or the off voltage that is applied to when sweep signal Yi becomes the H level on the gate electrode by stray capacitance, even if thereby during becoming the L level, the current potential of the capable common electrode of i 108 is determined at sweep signal Yi.

But, in such partial mode, compare with the full frame pattern and become less because sweep signal becomes frequency that voltage that the H level implemented writes.Therefore, such possibility is arranged,,, become at last below the threshold value, and the situation of conducting state takes place to keep because electric leakage waits and slowly reduces by any one the forward voltage that gate electrode kept of TFT173 or 174.

For fear of such situation, considered that also additional capacitive element is to reduce the formation of the influence of leaking electricity on the gate electrode of TFT 173,174, but the extra space that is used to form this capacity cell must be arranged, correspondingly the outside of viewing area, so-called fringe region broadens.

So as described below under partial mode in the present embodiment, control circuit 20 is supplied with control signal Vg-c.That is,, under partial mode, be made as the H level, be made as the L level at other frame at the 2nd, the 3rd, the 8th and the 9th frame as Fig. 6 and Fig. 7～shown in Figure 9.

At this, in the 2nd, the 3rd, the 8th and the 9th frame, implement voltage as mentioned above and write, thus there is no need specified polarity specification signal Pol, but in the present embodiment, polarity specification signal Pol is used for specified signal Vg-a, Vg-b.That is, under partial mode, polarity specification signal Pol as shown in Figure 7, becomes the L level at the 2nd, the 3rd frame, as Fig. 8 and shown in Figure 9, becomes the H level at the 8th and the 9th frame.As mentioned above, signal Vg-a, with polarity specification signal Pol be same signal, signal Vg-b is the signal of logic inversion polarity specification signal Pol.

At this, in the 1st frame, polarity specification signal Pol is the L level, so signal Vg-a is all the L level, signal Vg-b is the H level of counter-rotating.Therefore, in common electrode drive circuit 170, capable at odd number i, become the H level at sweep signal Yi and during TFT 171,172 conductings,, apply disconnection, forward voltage respectively the gate electrode of TFT 173,174, thus, make that TFT 173,174 disconnects respectively, conducting, so the capable common electrode 108 of this i writes the voltage Vsh that correspondingly becomes high-order side with negative polarity.Equally,, also, apply disconnection, forward voltage respectively, so the common electrode 108 of this (i+1) row becomes voltage Vsh to the gate electrode of TFT 173,174 even if OK at even number (i+1).

Then, in the 2nd and the 3rd frame of partial mode, control signal Vg-c becomes the H level, and then in common electrode drive circuit 170, the TFT 175,176 of the 1st～320 row all becomes conducting.In the 2nd and the 3rd frame, signal Vg-a and polarity specification signal Pol are all the L level, and signal Vg-b is and polarity specification signal Pol H level on the contrary.

Therefore, in the 2nd and the 3rd frame, to the gate electrode of TFT 173,174, apply disconnection, forward voltage respectively continuously, so the result, whole TFT 173 disconnect, whole TFT 174 conductings, whole common electrodes 108 is defined as voltage Vsh equally with the 1st frame.

In the 4th frame, sweep signal Y81～Y160 become in order the H level during, polarity specification signal Pol becomes the H level, so signal Vg-a is the H level, signal Vg-b for the counter-rotating the L level.

In common electrode drive circuit 170, when the related sweep signal of display line becomes the H level and makes TFT 171,172 conductings, gate electrode to TFT 173,174, apply conducting, off voltage respectively, thus, TFT 173,174 conductings respectively, disconnection are so the related common electrode 108 of display line writes the voltage Vsl that correspondingly becomes the low level side with positive polarity.

On the other hand, the 7th～10 frame is implemented the action of the relation of the polarity in counter-rotating the 1st～the 4th frame.

Like this, according to present embodiment, under partial mode, even if all row are being carried out beyond the 1st and the 7th frame that voltage writes, in the 2nd, the 3rd, the 8th and the 9th frame, the current potential of common electrode 108 is also determined, so correspondingly, can suppress the reduction of display quality.

In addition, in the present embodiment, in the 2nd, the 3rd, the 8th and the 9th frame, control signal Vg-c is made as the H level, so that the current potential of common electrode 108 determines, but as long as after all row being carried out the 1st (the 7th) frame that voltage writes, to than carrying out in the forward frame of frame till the 4th (the 10th) that the voltage of display line only writes all or part of, for example can only in the 3rd and the 9th frame, control signal Vg-c be made as the H level.

(the 2nd embodiment)

In the above-described first embodiment, under the full frame pattern, it is the capable inversion mode that polarity is reversed line by line that writes to pixel, under partial mode, because display line becomes the common polarity that writes each other, so by the display quality of the shown pixel of the pixel of display line, compare variation with the situation of full frame pattern, this point is undeniable.

So, even if describe by the 2nd embodiment that every sweep trace reverses under partial mode, still making display line write polarity each other.

Figure 10 is the block diagram of the formation of the related electro-optical device of expression the 2nd embodiment.

Formation shown in this figure is with the difference of Fig. 1, and in the odd-numbered line of common electrode drive circuit 170, the source electrode of TFT 175 is connected in second and gives electric wire 162, and the source electrode of TFT 176 is connected in first and gives electric wire 161.In addition, in even number line, the source electrode of TFT 175 is connected in first and gives electric wire 161, and the source electrode of TFT 176 is connected in second and gives electric wire 162, and this point is identical with the 1st embodiment.

Figure 11 is the viewing area 100 in the device substrate of expression the 2nd embodiment and the planimetric map of the boundary vicinity of common electrode drive circuit 170.

As Figure 11 and shown in Figure 10, the source electrode of the TFT 175,176 of mutual adjacent row is connected in first by shared wiring each other and gives electric wire 162 for electric wire 161 or second.For example, the source electrode of the TFT 176 of the source electrode of the TFT 175 that odd number i is capable and adjacent even number (i+1) row, be connected in second by shared wiring and give electric wire 162, the source electrode of the TFT 176 of (i-1) row before the source electrode of the TFT 176 that odd number i is capable and the adjacent delegation is connected in first by shared wiring and gives electric wire 161.

Therefore, the formation in the common electrode drive circuit 170 can be correspondingly simplified, capable spacing can be dwindled.

In addition, in the 2nd embodiment, the action of full frame pattern, identical with the 1st embodiment.But,, be that the center describes with the difference in the partial mode for the action of the 2nd embodiment.Figure 12 is the figure of an example that is illustrated in the action of each frame under the situation of partial mode.

Even if in the 2nd embodiment, under partial mode, enforcement is the action of 1 unit with the from the 1st to the 12nd 12 frames, in addition, the 1st～80 row and the 161st～320 is gone as non-display line, the 81st～160 row is carried out illustration as display line, and this point is identical with the 1st embodiment (with reference to Fig. 6).

As shown in figure 12, writing polarity in the 1st frame under the partial mode, all is the polarity that writes of just now the full frame pattern of reversing for the both sides of display line and non-display line, in addition, writing polarity in the 7th frame, is the polarity that writes of counter-rotating the 1st frame, all is the row inversion mode.In addition, writing polarity in the 4th frame of display line, is the polarity that writes of counter-rotating the 1st frame, writes polarity in the 10th frame of display line, is the polarity that writes of counter-rotating the 7th frame, also all is the row inversion mode.

With reference to Figure 13～Figure 15 the waveform of sweep signal under such partial mode shown in Figure 12 etc. is described.At this, Figure 13 is the figure of waveform etc. of the sweep signal Y1～Y320 of expression the 1st～the 4th frame, Figure 14 is the figure of waveform etc. of the sweep signal Y1～Y320 of expression the 5th～the 8th frame, and Figure 15 is the figure of waveform etc. of the sweep signal Y1～Y320 of expression the 9th～the 12nd frame.

As shown in these figures, under partial mode, sweep signal Y1～Y320 is identical with the partial mode of the 1st embodiment.

But in the present embodiment, in the 1st frame, polarity specification signal Pol becomes the H level when the sweep signal of odd-numbered line becomes the H level, become the L level when the sweep signal of even number line becomes the H level.In addition, the polarity specification signal Pol in the 7th frame is the signal of the polarity specification signal Pol in logic inversion the 1st frame.

And, in the 4th frame, polarity specification signal Pol, the related sweep signal Y81～Y160 of display line only become in order the H level during in, the sweep signal of odd-numbered line becomes the L level when becoming the H level, becomes the H level when the sweep signal of even number line becomes the H level.In the 10th frame, polarity specification signal Pol, it is the signal of the polarity specification signal Pol in logic inversion the 4th frame, the related sweep signal Y81～Y160 of display line only become in order the H level during in, the sweep signal of odd-numbered line becomes the H level when becoming the H level, becomes the L level when the sweep signal of even number line becomes the H level.

In addition, in the present embodiment, in the 2nd, the 3rd, the 8th and the 9th frame frame, not implementing voltage as described above writes, so there is no need specified polarity specification signal Pol, but with the 1st embodiment similarly, polarity specification signal Pol is used for specified signal Vg-a, Vg-b.Therefore, polarity specification signal Pol as shown in figure 13, becomes the H level at the 2nd and the 3rd frame, as Figure 14 and shown in Figure 15ly become the L level at the 8th and the 9th frame.

In the 2nd embodiment, the action of the 1st frame, except non-display line being forced to write the voltage suitable, identical with the full frame pattern with black (disconnection).Therefore, the common electrode 108 that odd number i is capable writes the voltage Vsl that correspondingly becomes the low level side with positive polarity, and the common electrode 108 of even number (i+1) row writes the voltage Vsh that correspondingly becomes high-order side with negative polarity.

Then, in the 2nd and the 3rd frame of partial mode, signal Vg-a is the H level identical with polarity specification signal Pol, and signal Vg-b is the L level opposite with polarity specification signal Pol.Control signal Vg-c becomes the H level, then in common electrode drive circuit 170, the TFT175,176 of the 1st～320 row all becomes conducting, so the TFT173 of odd-numbered line, 174 gate electrode are applied disconnection, forward voltage respectively, on the other hand, the TFT173 of even number line, 174 gate electrode are applied conducting, off voltage respectively on the contrary.Therefore, in odd-numbered line, because the common electrode 108 of this odd-numbered line of conducting of TFT174, write the voltage Vsl that correspondingly is defined as the low level side with positive polarity, on the other hand, in even number line, because the common electrode 108 of this even number line of conducting of TFT 173, write the voltage Vsh that correspondingly is defined as high-order side with negative polarity, keep the voltage of the 1st frame respectively.

In the 4th frame, sweep signal Y81～Y160 become in order the H level during in, the sweep signal of odd-numbered line become the H level during, polarity specification signal Pol becomes the L level, so signal Vg-a becomes the L level, signal Vg-b becomes the H level of counter-rotating.In common electrode drive circuit 170, when the sweep signal of the odd-numbered line in display line becomes TFT 171,172 conductings of H level, this odd-numbered line, gate electrode to TFT 173,174 applies conducting, off voltage respectively, on the other hand, when the sweep signal of even number line becomes TFT 171,172 conductings of H level, this even number line, the gate electrode of TFT 173,174 is applied disconnection, forward voltage respectively.

Therefore, odd-numbered line at display line, because the conducting of TFT 173, the common electrode 108 of this odd-numbered line writes the voltage Vsh that correspondingly is defined as high-order side with negative polarity, on the other hand, even number line at display line, because the conducting of TFT 174, the common electrode 108 of this even number line writes the voltage Vsl that correspondingly is defined as the low level side with positive polarity.

In addition, in the 7th～the 10th frame, at each row, the voltage of implementing the relation that writes polarity of the same delegation in counter-rotating the 1st～the 4th frame writes.

Like this, according to the 2nd embodiment, under partial mode, even if whole row are being carried out beyond the 1st and the 7th frame that voltage writes, in the 2nd, the 3rd, the 8th and the 9th frame, still determine the current potential of common electrode 108, so correspondingly can suppress the reduction of display quality.And then, according to the 2nd embodiment, the display line in the partial mode to write polarity identical with the full frame pattern be capable inversion mode by the counter-rotating of every sweep trace, so but the display quality of retaining part pattern and full frame pattern identical.

(application variation)

In the 1st and the 2nd above-mentioned embodiment, so long as full frame pattern, can be made as the capable inversion mode that polarity is reversed line by line that writes, also can be made as row inversion mode, line by line and by the some inversion mode of row ground by the counter-rotating of pixel ground by row counter-rotatings to pixel.

In order to make it to become row inversion mode, some inversion mode, for example as shown in figure 16, every row is provided with two common electrode 108a, 108b, and as shown in figure 17, make the pixel 110 and common electrode 108a of odd number j row, the pixel 110 of even number (j+1) row and corresponding the getting final product of common electrode 108b difference.

And, in common electrode drive circuit 170, constitute and followingly get final product like this, with the TFT173,174 of each row is TFT173a, 173b and TFT174a, 174b as two series respectively, when the series of any one party was defined as common electrode 108 a side among voltage Vsl, the Vsh, the opposing party's series was defined as the opposing party among voltage Vsl, the Vsh with common electrode 108 arbitrarily.

At this, in order to be made as the row inversion mode, when for example odd column being made as positive polarity, even column is made as negative polarity to get final product, so when the sweep signal of each row becomes the H level, to correspondingly be defined as the voltage Vsl of low level side with corresponding common electrode 108a of odd column and positive polarity, will get final product with the voltage Vsh that corresponding common electrode 108b of even column and negative polarity correspondingly are defined as high-order side.

On the other hand, in order to be made as an inversion mode, the row inversion mode is combined and gets final product with the row inversion mode, so for example when the odd-numbered line odd column is made as positive polarity, the odd-numbered line even column is made as negative polarity, ensuing even number line odd column is made as negative polarity, the even number line even column is made as positive polarity.Therefore, when the sweep signal of odd-numbered line becomes the H level, to correspondingly be defined as the voltage Vsl of low level side with corresponding common electrode 108a of odd column and positive polarity, to correspondingly be defined as the voltage Vsh of high-order side with corresponding common electrode 108b of even column and negative polarity, on the other hand, when the sweep signal of ensuing even number line becomes the H level, to correspondingly be defined as voltage Vsh with corresponding common electrode 108a of odd column and negative polarity, will correspondingly be defined as voltage Vsl with corresponding common electrode 108b of even column and positive polarity and get final product.

In addition, in any one of row inversion mode and some inversion mode, 1 horizontal scanning line is applied select voltage during, exist to the data-signal of odd column and the relation of reversing mutually to the data-signal of even column.In addition, in order to prevent that liquid crystal capacitance 120 is applied flip-flop, must make reversal of poles with the frame period of regulation.

In addition, in the above-described embodiment, with shared signal Vc-a, Vc-b, signal Vg-a, Vg-b, be made as waveform as shown in Figure 4 respectively, but can make shared signal Vc-a, Vc-b by for example per image duration or each horizontal scan period (H) counter-rotating (replacement), and with this logic of specified signal Vg-a, Vg-b as one man of reversing.

Promptly, constitute and followingly get final product like this, promptly when the sweep signal to certain sweep trace becomes the H level, the common electrode of this row is made as and writes the polarity correspondent voltage to this row, even and if this sweep signal becomes the L level, the common electrode of this row still continues to maintain this voltage.

In the above-described embodiment, for the capable TFT 171,172 of i, when having selected i capable sweep trace, sweep signal Yi to become the H level, make it become conducting state.At this, the TFT 171,172 that i is capable, decision gives electric wire 162 for electric wire 161, second in the gate electrode connection first of TFT 173,174, the this point that makes any one party of TFT 173,174 become conducting state, makes any the opposing party become off-state is very important, as long as the capable common electrode 108 of i is defined as and writes the corresponding current potential of electrode,, be not so important then about when making TFT 171,172 conductings.

In addition, to write polarity be nonsensical because specify during vertical flyback, so the logical signal of polarity specification signal Pol, shared signal Vc-a, Vc-b etc. can be fixed on certain level.

And, in embodiment, liquid crystal capacitance 120 is made as normal black pattern, but also can be made as the normal white mode that under no-voltage applies state, becomes bright state.In addition, can constitute a point, carry out colour and show, append another color (for example dark green (C)), constitute a point by these four pixels, to improve color reprodubility but also can constitute by R (red), G (green), three pixels of B (indigo plant).

(the 3rd embodiment)

Then, the 3rd embodiment of the present invention is described.Figure 18 is the block diagram of the formation of the related electro-optical device of expression the 3rd embodiment of the present invention.

As shown in the drawing, electro-optical device 10 is to have viewing area 100, and the circumferential arrangement in this viewing area 100 has the panel of the peripheral circuit internally-arranged type of scan line drive circuit 140, common electrode drive circuit 170a, 170b, data line drive circuit 190 to constitute.In addition, control circuit 20 is connected by for example FPC (flexible print circuit) substrate with the panel of above-mentioned peripheral circuit internally-arranged type.

Viewing area 100 is the zones of arranging pixel 110, and in the present embodiment, the mode of extending with (X) direction of being expert at is provided with the sweep trace 112 from the 1st row to the 320th row respectively, in addition, is provided with 240 column data lines 114 in the mode of extending in row (Y) direction.And, with the sweep trace 112 of these the 1st～the 320th row and intersecting accordingly of the 1st～240 data line 114 that is listed as, be arranged with pixel 110 respectively.Therefore, in the present embodiment, in viewing area 100, pixel 110 is arranged in rectangular with vertical 320 row * horizontal strokes, 240 row, but the present invention is not limited to this arrangement.

In addition, in the present embodiment,, common electrode 108 is set on directions X respectively with extending about the sweep trace 112 of each article the 1st～320 row.Therefore, for common electrode 108, each sweep trace 112 with the 1st～320 row is provided with accordingly respectively.

At this, the detailed formation of pixel 110 is described.Figure 19 is the figure of the formation of remarked pixel 110, expression with i capable and below (i+1) row, j row of being adjacent and in corresponding 2 * 2 the formation of 4 pixels altogether of intersecting of right-hand (j+1) row that are adjacent.

In addition, i, (i+1) are the mark of general expression when arranging pixel 110 capable, i is 1,3,5 ..., the odd number arbitrarily in 319, and (i+1) be 2,4,6 with the continuous even number of i ..., the even number arbitrarily in 320.In addition, j, (j+1) are the mark of general expression when arranging the row of pixel 110, j is 1,3,5 ..., the odd number arbitrarily in 239, and (j+1) be with the continuous even number of j promptly 2,4,6 ..., the even number arbitrarily in 240.

Following only abbreviate as " TFT ") 116, liquid crystal capacitance (pixel capacitance) 120 and memory capacitance 130 as shown in figure 19, each pixel 110 has: the thin film transistor (TFT) of the n channel-type that plays a role as the pixel switch element (thin film transistor:.For each pixel 110, same each other in the present embodiment formation, so with the pixel that is positioned at the capable j row of i is that representative describes, in the pixel 110 of the capable j row of this i, the sweep trace 112 that the gate electrode of TFT 116 and i are capable is connected, the data line 114 of its source electrode and j row is connected on the other hand, and its drain electrode is connected respectively with as the pixel electrode 181 of an end of liquid crystal capacitance 120 and an end of memory capacitance 130.In addition, an other end of liquid crystal capacitance 120 and an other end of memory capacitance 130 are connected with common electrode 108 respectively.

In addition, in Figure 19, Yi, Y (i+1) represent sweep signal that the sweep trace 112 of i, (i+1) row is supplied with respectively, and in addition, Ci, C (i+1) represent the voltage of the common electrode 108 of i, (i+1) row respectively.About optical characteristics of liquid crystal capacitance 120 etc., explanation hereinafter.

Return Figure 18 and describe, control circuit 20 is exported various control signals and is carried out control of each one in the electro-optical device 10 etc.In addition, about various control signals, suitably explanation hereinafter.

In addition, this electro-optical device 10 is with following two kinds of patterns action, the pixel 110 of promptly using whole vertical 320 row * horizontal stroke, 240 row to arrange carry out the full frame pattern (first pattern) that image shows and only use in the above-mentioned arrangement, and the corresponding pixel 110 of a part of sweep trace effectively show, and make it not show the also partial mode (second pattern) of ineffective treatment for other pixel.In addition, in the following description, by way of exception treat, and in principle the full frame pattern is described about partial mode.

100 the periphery in the viewing area as mentioned above, is provided with the peripheral circuit of scan line drive circuit 140, common electrode drive circuit 170a, 170b, data line drive circuit 190 etc.

Wherein, scan line drive circuit 140, under the full frame pattern, in 1 image duration with sweep signal Y1, Y2, Y3 ..., Y320 is supplied to the 1st, 2,3 respectively ..., the sweep traces 112 of 320 row.Specifically, scan line drive circuit 140, as shown in figure 22, during 1 frame, press among Fig. 1 number from top to bottom the 1st, 2,3 ..., the orders of 320 row select sweep trace 112 line by line, to be made as the selection voltage Vdd suitable to the sweep signal of the sweep trace of having selected, will be made as the non-selection voltage suitable (earthing potential Gnd) to the sweep signal of in addition sweep trace with the L level with the H level.

At this, scan line drive circuit 140, for example by the beginning pulsed D y that is supplied with by control circuit 20 is shifted etc. in turn, thus make sweep signal Y1, Y2, Y3, Y4 ..., Y320 becomes the H level in proper order by this.In addition, in Figure 22, the timing that is changed to the L level to the sweep signal of certain sweep trace from the H level is roughly the same from the timing that the L level becomes the H level with the sweep signal to next sweep trace, but also can shorten become the H level during etc.

In the present embodiment, so-called 1 frame be meant in the full frame pattern, show 1 piece of image required during, be 16.7 milliseconds, as shown in figure 22, except become the H level becomes the L level to sweep signal Y320 effective scanning from sweep signal Y1 during, the Fa, also comprise retrace interval in addition.In addition, also retrace interval can be set.In addition, the sweep trace 112 of 1 row is horizontal scan period (H) during selecteed.

At this, under partial mode, the situation that does not show one piece of image in 1 frame is as described later arranged also, so exist in simple terms differ 16.7 milliseconds during situation.

On the other hand, scan line drive circuit 140, in partial mode, Figure 25 for example described later～shown in Figure 27, in the waveform of sweep signal Y1 in the full frame pattern～Y320, in a part of frame, output becomes the sweep signal of H level in a part all or only.

Common electrode drive circuit 170a, 170b drive the 1st～320 common electrode 108 of going, and are divided into 170a, 170b simply.

Wherein, common electrode drive circuit 170a is located between scan line drive circuit 140 and the viewing area 100 in the present embodiment, is made of the group with the TFT 171～174 of the n channel-type that is provided with accordingly of common electrode 108 of the 1st～320 row.

The connection of TFT 171～171, each row is identical, so describe with i behavior representative, the gate electrode of the TFT 171 (the first transistor) that i is capable is connected in the capable sweep trace of i 112, its source electrode is connected in first and gives electric wire 161, and its drain electrode is connected in the gate electrode of TFT 173.The gate electrode of the TFT 172 (transistor seconds) that this i is capable is connected in the capable sweep trace of i 112, and its source electrode is connected in second and gives electric wire 162, and its drain electrode is connected in the gate electrode of TFT 174.

The source electrode of the TFT 173 that i is capable (the 3rd transistor) is connected in the 3rd and gives electric wire 163, the source electrode of the TFT 174 that this i is capable (the 4th transistor) is connected in the 4th and gives electric wire 164, and the drain electrode of TFT 173,174 is connected to each other in the capable common electrode 108 of i.

Common electrode drive circuit 170b, relative viewing area 100 is arranged on the opposition side of common electrode drive circuit 170a, and the TFT 175 of the n channel-type that is provided with accordingly by the common electrode 108 with the 1st～320 row constitutes.At this, the gate electrode of the TFT 175 (the 5th transistor) of each row is connected in control line 166, and its source electrode is connected in signal wire 167, and its drain electrode is connected in common electrode 108.

Data line drive circuit 190, at being positioned at the pixel 110 that applies the sweep trace 112 of selecting voltage by scan line drive circuit 140, to data line 114 supply with the gray scale correspondent voltage of pixel promptly with by the specified data-signal that writes the polarity correspondent voltage of polarity specification signal Pol.

Data line drive circuit 190 has with the picture element matrix of vertical 320 row * horizontal strokes, 240 row and arranges corresponding storage area (omitting diagram), and in each storage area, the video data Da of the gray scale (brightness) of each self-corresponding pixel 110 is specified in storage.At this, data line drive circuit 190, before soon certain sweep trace 112 being applied selection voltage, read the video data Da of the pixel 110 that is positioned at this sweep trace 112 from storage area, and be transformed to and by the specified gray scale of this video data of reading and write the polarity correspondent voltage, select the timing of voltage as one man it to be supplied to data line 114 as data-signal with applying.Data line drive circuit 190 is implemented this supply action to 1～240 row that are positioned at selected sweep trace 112 respectively.

In addition, the video data Da that stores at storage area under the situation that displaying contents changes, conducts interviews and to its supply and rewrite after changing video data Da from control circuit 20.In addition, data line drive circuit 190 under partial mode, moves as described later.

In addition, control circuit 20 in the timing that the logic level of clock signal C ly changes, is supplied with latch pulse Lp to data line drive circuit 190.As mentioned above, scan line drive circuit 140, by the beginning pulsed D y etc. that is shifted in turn according to clock signal C ly, with sweep signal Y1, Y2, Y3, Y4 ..., Y320 is made as the H level in order, so select sweep trace during beginning regularly be the timing that the logic level of clock signal C ly changes.Therefore, data line drive circuit 190, for example by continuous counter latch pulse Lp during 1 frame, what select as can be known is the sweep trace of which row, and then the supply by latch pulse Lp is regularly, can know the beginning timing of its selection.

In addition, scan line drive circuit 140 even if under partial mode, is also implemented the shift motion of above-mentioned beginning pulsed D y etc., and only the part restriction is made as the sweep signal of H level.

In the present embodiment under the full frame pattern, if polarity specification signal Pol is the H level, it then is the signal of specifying positive polarity to write to the pixel that is applied in the sweep trace of selecting voltage, if L level, then be the signal of specifying negative polarity to write, be actually waveform as shown in figure 22 this pixel.Specifically, as shown in the drawing, during a certain frame (souvenir is " a n frame "), the subtend odd number (1,3,5 ..., 319) sweep signal of sweep trace of row applies and becomes the H level when selecting voltage, the subtend even number (2,4,6 ..., 320) sweep signal of the sweep trace of row applies and becomes the L level when selecting voltage.Therefore, in the present embodiment, under the full frame pattern, be the mode that writes the row counter-rotating that polarity reverses line by line (row counter-rotating, sweep trace counter-rotating) to pixel.

In addition, polarity specification signal Pol is under the full frame pattern, next frame (souvenir is " n+1 " frame), logic inversion when same row carries out comparison, the reason that writes reversal of poles like this are in order to prevent because the deterioration that applies the liquid crystal that is caused of flip-flop.

In addition, polarity specification signal Pol is under partial mode, Figure 25～shown in Figure 27 becomes the L level in the gamut of the 1st frame as described later, becomes the H level in during the part of the 4th frame, in the gamut of the 7th frame, become the H level, become the L level in during the part of the 10th frame.

At this, about the polarity that writes in the present embodiment, will be when keeping with the gray scale correspondent voltage at liquid crystal capacitance 120, the situation that the current potential that the current potential of pixel electrode 118 is compared common electrode 108 is in high-order side is called positive polarity, and the situation that will be in the low level side is called negative polarity.About voltage, unless otherwise specified, the L level of earthing potential Gnd and logic level is suitable, and as the benchmark of no-voltage.

Supply with signal Vg-a, Vg-b for electric wire 162 for electric wire 161 and second to first respectively by control circuit 20.At this, in the present embodiment, under the full frame pattern, signal Vg-a and the same waveform of polarity specification signal Pol, signal Vg-b is the waveform of logic inversion polarity specification signal Pol.

The Vdd suitable with the H level of logic level is when it is put on the gate electrode of TFT 173,174, will be made as the forward voltage of conducting (ON) state between the source electrode of this TFT 173,174, the drain electrode.In addition, the L level is earthing potential Gnd, even if be that it is put on TFT173,174 gate electrode, is the off voltage of non-conduction (OFF) state between the source electrode of this TFT 173,174, the drain electrode.

Supply with signal Vc-a, Vc-b for electric wire 164 for electric wire 163 and the 4th to the 3rd respectively by control circuit 20.In the present embodiment, no matter under the full frame pattern or under partial mode, shared signal Vc-a is fixed as voltage Vsl, in addition, Vc-b is fixed as voltage Vsh with the common voltage signal.Voltage Vsl, Vsh, (≤Vdd) such relation, voltage Vsl is the relatively low voltage of comparison with voltage Vsh (voltage Vsh is the relative higher voltage of comparison with voltage Vsl) (Gnd≤) Vsl＜Vsh.

In addition, supply with control signal Vg-c by 20 pairs of control lines of control circuit 166.Control signal Vg-c is the L level under the full frame pattern, and under partial mode, Figure 25～shown in Figure 27 is the H level at the 2nd, the 3rd, the 8th and the 9th frame only as described later.And, supply with shared signal Vc by 20 pairs of signal wires of control circuit 167.Shared signal Vc becomes voltage Vsh in the 2nd and the 3rd frame under partial mode, becomes voltage Vsl in the 8th and the 9th frame.

Also have, the pulse in the electro-optical device constitutes, a pair of substrate maintenance certain clearance applying that device substrate and relative substrate are constituted and enclose liquid crystal in this gap.In addition, on device substrate, be formed with above-mentioned sweep trace 112, data line 114, common electrode 108, pixel electrode 118 and TFT 116,171～175, fit in the mode that electrode forming surface is relative with relative substrate.Figure 20 plane earth is represented viewing area 100 in this formation and the boundary vicinity of common electrode drive circuit 170a, and Figure 21 plane earth is represented viewing area 100 in this formation and the boundary vicinity of common electrode drive circuit 170b.

According to Figure 20 and Figure 21 also as can be known, viewing area 100 is direction of an electric field that liquid crystal is applied FFS (fringe field switching, fringing field switches) patterns as the distortion of the IPS pattern of real estate direction.In addition, in the present embodiment, TFT 171～175th, and amorphous silicon type, its gate electrode are to compare the bottom gate polar form that semiconductor layer is positioned at downside (paper inboard).

Specifically, by becoming (the 1st) ITO (indiun tin oxide of first conductive layer, the indium sb oxide) composition of layer forms the electrode 108f of rectangular shape, and then the composition of the grid electrode layer by becoming second conductive layer, form the grid wiring of sweep trace 112, control line 166, bridging line 108e etc., be formed with gate insulating film (omitting diagram) thereon, and the semiconductor layer of TFT forms island.Then; forming protection insulation course (omitting diagram) afterwards; the composition of (the 2nd) the ITO layer by becoming the 3rd conductive layer forms the pixel electrode 118 of broach shape; and then; the composition of the metal level by becoming the 4th conductive layer forms source electrode, the drain electrode of TFT; and form data line 114, first and give electric wire 164 and signal wire 167 for electric wire the 163, the 4th for electric wire the 162, the 3rd for electric wire 161, second, also have various connection electrode.

In addition, in Figure 20 and Figure 21, * mark is the contact hole that is used to connect the wiring that comprises grid electrode layer and comprises the wiring layer of the 4th conductive layer.

Common electrode 108 among Figure 18 and Figure 19 in Figure 20 and Figure 21, is divided into the bridging line 108e that extends in parallel with sweep trace 112 and via the electrode 108f of the rectangular shape of the stacked pixel electrode 118 of protection insulation course.At this, be positioned at each other with the bridging line 108e of delegation and electrode 108f, have the part that partially overlaps mutually, conduct.Therefore, be positioned at bridging line 108e and electrode 108f with delegation, identical aspect electric, there is no need to distinguish, so only otherwise the explanation that relates to the structure aspect is not just distinguished both, nonoculture is a common electrode 108.

In the present embodiment, memory capacitance 130 is the capacitive components that lit-par-lit structure produced that clipped the protection insulation course by electrode 108f and pixel electrode 118.In addition, in the gap of device substrate and relative substrate, also enclose liquid crystal, so between pixel electrode 118 and electrode 108f, also produce capacitive component by the structure that liquid crystal constituted that clips as medium.In the present embodiment, will clip capacitive component that this liquid crystal constitutes as liquid crystal capacitance 120.

In this constituted, the corresponding electric field of sustaining voltage with the shunt capacitance of liquid crystal capacitance 120 and memory capacitance 130 produced along the device substrate face and on the direction vertical with the broach of pixel electrode 118, and the state of orientation of liquid crystal is changed.Thus, by the light quantity of polariton (omit diagram), the effective value that becomes with this sustaining voltage is worth accordingly.

In addition, in the present embodiment,,, then can also be other pattern if electrical equivalent circuit is a circuit as shown in figure 19 though, can also be the IPS pattern as the FFS pattern.

At this, the sustaining voltage of above-mentioned shunt capacitance is the potential difference of pixel electrode 118 and common electrode 108 (electrode 108f), so for the pixel with the capable j row of i is made as the purpose gray scale, as long as the capable sweep trace 112 of i is applied selection voltage Vdd so that TFT 116 becomes conducting (ON) state, and will make above-mentioned potential difference become data-signal Xj with the voltage of the corresponding value of the gray scale of pixel, the data line 114 that is listed as via j and be supplied to pixel electrode 118 at the TFT 116 of the capable j row of i conducting and get final product.

In addition, in the present embodiment, for the convenience that illustrates, be made as normal black pattern, if promptly this voltage effective value is near zero, then the optical transmission rate becomes minimum and carries out black display, on the other hand along with voltage effective value increases, the light quantity of transmission also increases, and the white that finally becomes the transmissivity maximum shows.

In addition, so the data line 114 of the common electrode 108 of each row and the 1st～240 row as shown in phantom in Figure 19, carries out capacitive coupling via stray capacitance mutually via intersections such as gate insulating films.

Figure 20 and formation shown in Figure 21, tentatively as an example about the type of TFT, can also be other structures, for example can be used as the top grid type from the configuration of gate electrode, can be used as the polysilicon type from technology.In addition, also can constitute, the composed component of common electrode drive circuit 170a, 170b is that TFT 171～175 does not implant on the substrate with same technology with viewing area 100, but the IC chip is installed on the device substrate.

Under situation about the IC chip being installed on the device substrate, scan line drive circuit 140, common electrode drive circuit 170a, 170b and data line drive circuit 190 can be integrated into semi-conductor chip together, also can be used as independent separately chip.On the other hand, about control circuit 20, also can be the formation of implant element substrate.

In addition, the bearing of trend of relative scanning line 112, common electrode drive circuit 170a is arranged on a side of scan line drive circuit 140, in addition, common electrode drive circuit 170b is arranged on the opposition side of scan line drive circuit 140, also can be to concern in contrast to this, both of common electrode drive circuit 170a, 170b can also be arranged in the same area.

About present embodiment, can be transmission-type, reflection-type, can also be so-called semi-transparent semi both combinations of transmission-type and reflection-type.Therefore, do not mention reflection horizon etc. especially.

Then, the situation to the full frame pattern in the action of the related electro-optical device 10 of present embodiment describes.

As mentioned above, in the present embodiment, when being made as the full frame pattern, control circuit 20 as shown in figure 22, difference output polarity specification signal Pol, signal Vg-a, Vg-b are fixed as voltage Vsl with shared signal Vc-a in the n frame, and shared signal Vc-b is fixed as voltage Vsh.

In the n frame,, at first will become the H level to the sweep signal Y1 of the 1st sweep trace 112 of going by scan line drive circuit 140.In addition, in the n frame, specify positive polarity to write in odd-numbered line, so become output latch pulse Lp in the timing of H level at sweep signal Y1, then data line drive circuit 190, will with voltage Vsl be benchmark exceed by the 1st row the 1st, 2,3 ..., data-signal X1, the X2 of the voltage of the high-order side of the specified voltage of the video data Da of pixels of 240 row, X3 ..., X240, be supplied to the 1st, 2,3 respectively ..., the data lines 114 of 240 row.Thus, for example being supplied to the data-signal Xj of the data line 114 of j row, is that comparison with voltage Vsl exceeds the voltage by the high-order side of the specified voltage of the video data Da of the pixel 110 of 1 row j row.

Sweep signal Y1 becomes the H level, then TFT 116 conductings in the pixel of 1 row 1 row～1 row, 240 row, so to its pixel electrode 118 apply data-signal X1, X2, X3 ..., X240.

On the other hand, sweep signal Y1 become the H level during, in common electrode drive circuit 170a, the 1st the row TFT 171,172 conductings.At this, sweep signal Y1 become the H level during, being supplied to the first signal Vg-a to electric wire 161 is the H level, being supplied to the second signal Vg-b to electric wire 162 is the L level, so TFT 171,172 by difference conducting the 1st row, thus, respectively the gate electrode of the 1st TFT 173 that goes is applied the forward voltage of H level, the gate electrode of TFT 174 is applied the off voltage of L level.Therefore, the TFT 173,174 of the 1st row, respectively conducting, disconnection are so the common electrode 108 of the 1st row is connected for electric wire 163 with the 3rd and becomes voltage Vsl.

Therefore, to the liquid crystal capacitance 120 of 1 row, 1 row～1 row, 240 row and the shunt capacitance of memory capacitance 130, write voltage respectively with the corresponding positive polarity of gray scale.

In addition, under the full frame pattern, control signal Vg-c is the L level, and in common electrode drive circuit 170b, the TFT 175 of all row disconnects, so do not become the reason of the voltage of decision common electrode 108.

Then, sweep signal Y1 becomes the L level, and sweep signal Y2 becomes the H level on the other hand.

At this, sweep signal Y1 becomes the L level, and then the TFT 116 in the pixel of 1 row, 1 row～1 row, 240 row disconnects.Therefore, in the pixel 110 of 1 row, 1 row～1 row, 240 row, each pixel electrode 118 becomes high impedance status.

On the other hand, in common electrode drive circuit 170a, sweep signal Y1 becomes the L level, and then the TFT 171,172 of the 1st row also disconnects, so the gate electrode of TFT 173,174 becomes high impedance status.But, because the gate electrode of TFT 173,174, by its stray capacitance remain on be about to become the state of high impedance status, promptly be respectively the state of H, L level, so TFT 173,174 continues to remain conducting, off-state.Therefore, the common electrode 108 of the 1st row even if sweep signal Y1 becomes the L level, still continues to be connected in the 3rd and gives electric wire 163, so keep voltage Vsl.Therefore, the other end of the liquid crystal capacitance 120 of 1 row, 1 row～1 row, 240 row and the shunt capacitance of memory capacitance 130 is kept voltage Vsl, and the voltage status that writes does not continue with changing.

In addition, in the n frame, specify negative polarity to write in even number line, so become output latch pulse Lp in the timing of H level at sweep signal Y2, then data line drive circuit 190, output with voltage Vsh be benchmark low by the 2nd row the 1st, 2,3 ..., data-signal X1, the X2 of the voltage of the low level side of the specified voltage of the video data Da of pixels of 240 row, X3 ..., X240.Thus, for example be supplied to the data-signal Xj of the data line 114 of j row, be comparison with voltage Vsh low by the voltage of the low level side of the specified voltage of the video data Da of the pixel 110 of 2 row j row.

Sweep signal Y2 becomes the H level, then TFT 116 conductings in the pixel of 2 row 1 row～2 row, 240 row, so to its pixel electrode 118 apply data-signal X1, X2, X3 ..., X240.

On the other hand, sweep signal Y2 become the H level during, in common electrode drive circuit 170a, the 2nd the row TFT 171,172 conductings.At this, sweep signal Y2 become the H level during, to be supplied to first respectively switches to the L level for the signal Vg-a of electric wire 161, switch to the H level for the signal Vg-b of electric wire 162 with being supplied to second, so TFT 173, the TFT 174 of the 2nd row, with the 1st the row opposite, respectively the disconnection, conducting.Therefore, the common electrode 108 of the 2nd row is connected for electric wire 164 with the 4th and becomes voltage Vsh.

Therefore, to the liquid crystal capacitance 120 of 2 row, 1 row～2 row, 240 row and the shunt capacitance of memory capacitance 130, write voltage respectively with the corresponding negative polarity of gray scale.

Then, sweep signal Y2 becomes the L level, and sweep signal Y3 becomes the H level on the other hand.At this, sweep signal Y2 becomes the L level, and then the TFT116 in the pixel of 2 row, 1 row～2 row, 240 row disconnects, and therefore, in the pixel 110 of 2 row, 1 row～2 row, 240 row, each pixel electrode 118 becomes high impedance status.

On the other hand, in common electrode drive circuit 170a, sweep signal Y2 becomes the L level, the TFT 171,172 of the 2nd row also disconnects, so the gate electrode of TFT 173,174 becomes high impedance status, but because its stray capacitance is maintained at L, H level respectively, so the TFT 173,174 of the 2nd row continues to keep disconnection, conducting state.Therefore, the common electrode 108 of the 2nd row even if sweep signal Y2 becomes the L level, still continues to be connected in the 4th and gives electric wire 164, so keep voltage Vsh.

Therefore, the other end of the liquid crystal capacitance 120 of 2 row, 1 row～2 row, 240 row and the shunt capacitance of memory capacitance 130 is kept voltage Vsh, and the voltage status that writes does not continue with changing.

In addition, sweep signal Y3 becomes the H level, then to the liquid crystal capacitance 120 of the 3rd row and the shunt capacitance of memory capacitance 130, write voltage respectively with the corresponding positive polarity of gray scale, then, sweep signal Y4 becomes the H level, then to the liquid crystal capacitance 120 of the 4th row and the shunt capacitance of memory capacitance 130, writes the voltage with the corresponding negative polarity of gray scale respectively.

Below, repeat same action up to the 320th row, thus, in the n frame, to the liquid crystal capacitance 120 of odd-numbered line and the shunt capacitance of memory capacitance 130, write respectively and the corresponding positive polarity voltage of gray scale,, write respectively and the corresponding reverse voltage of gray scale the liquid crystal capacitance 120 of even number line and the shunt capacitance of memory capacitance 130.Thus, in the shunt capacitance in whole pixels, write respectively and the gray scale correspondent voltage, so in viewing area 100, show the image of 1 piece (frame).

In ensuing (n+1) frame, polarity specification signal Pol, signal Vg-a, there is inverse relation in the logic level of Vg-b and n frame before, so believe 112 when selected in the scanning of odd-numbered line, with the corresponding common electrode 108 of the sweep trace of this selecteed odd-numbered line, be connected for electric wire 164 to become voltage Vsh with the 4th, even and if this sweep trace becomes non-selected (sweep signal is the L level), still keep this connection status, on the other hand, when the sweep trace 112 of even number line is selected, with the corresponding common electrode 108 of the sweep trace of this selecteed even number line, be connected for electric wire 163 to become voltage Vsl with the 3rd, even and if this sweep trace becomes non-selectedly, still keep this connection status.

Therefore, in (n+1) frame, to the liquid crystal capacitance 120 of odd-numbered line and the shunt capacitance of memory capacitance 130, write voltage respectively with the corresponding negative polarity of gray scale, to the even number line shunt capacitance, write the voltage with the corresponding positive polarity of gray scale respectively, keep the voltage status that writes respectively.

At this,, describe with reference to Figure 23 for writing of the related voltage of present embodiment.Figure 23 is that (i, (i+1 is j) with the figure of the relation of each sweep signal Yi, Y (i+1) j) and (i+1) go voltage Pix in the pixel electrode 118 of j row for voltage Pix in the pixel electrode 118 of the capable j of expression i row.In addition, the vertical engineer's scale of expression voltage in Figure 23, the vertical engineer's scale of comparing for convenience among Figure 22 amplifies.

In the n frame, specify positive polarity to write at the capable pixel of odd number i, so sweep signal Yi become the H level during, to the data line 114 of j row, supply with and compare this voltage Vsl and exceed data-signal Xj with the voltage (usefulness ↑ expression in Figure 23) of the high-order side of the gray scale correspondent voltage of the pixel of the capable j row of i.Thus, in the shunt capacitance of the liquid crystal capacitance 120 of the capable j of i row and memory capacitance 130, write the potential difference of the voltage Vsl of the voltage of data-signal Xj and common electrode 108, promptly with the corresponding positive polarity voltage of gray scale.

At this, sweep signal Yi becomes the L level, and then the pixel electrode 118 of the capable j row of i becomes high impedance status.Relative therewith, the common electrode 108 that odd number i is capable when sweep signal Yi becomes the H level, is connected in the 3rd and gives electric wire 163 in the n frame, so become voltage Vsl, this connection status lasts till when sweep signal Yi becomes the H level once more in ensuing (n+1) frame.Therefore, voltage Pix (the i of the pixel electrode 118 of the capable j row of i, j), therefore the not change of the voltage (voltage of data-signal Xj) when sweep signal Yi becomes the H level does not exert an influence to the voltage effective value (dash area) that is kept by liquid crystal capacitance 120 and memory capacitance 130.

In addition, in the n frame, specify negative polarity to write at the pixel of even number (i+1) row, so sweep signal Y (i+1) become the H level during, to the data line 114 of j row, supply with compare this voltage Vsh low with the data-signal Xj of the voltage (usefulness ↓ expression in Figure 23) of the low level side of the gray scale correspondent voltage of the pixel of (i+1) row j row.Thus, in the shunt capacitance of the liquid crystal capacitance 120 of (i+1) row j row and memory capacitance 130, write and the corresponding reverse voltage of gray scale.In addition, the common electrode 108 of even number (i+1) row, in the n frame when sweep signal Y (i+1) becomes the H level, be connected in the 4th and give electric wire 164, so become voltage Vsh, this connection status lasts till when sweep signal Y (i+1) becomes the H level once more in ensuing (n+1) frame, so, voltage Pix (i+1, j), therefore the not change of the voltage (voltage of data-signal Xj) when sweep signal Y (i+1) becomes the H level does not exert an influence to the voltage effective value (dash area) that is kept by liquid crystal capacitance 120 and memory capacitance 130.

And, in ensuing (n+1) frame, write reversal of poles, write so implement negative polarity at the capable pixel of odd number i respectively, implement positive polarity at the pixel of even number (i+1) row and write.

So, in the present embodiment, under the full frame pattern, write polarity and reverse by every sweep trace.

According to such embodiment, specified the common electrode 108 of the row that positive polarity writes, when selecting the sweep trace 112 of this row, become relatively low voltage Vsl, to exceed with the voltage of the high-order side of gray scale correspondent voltage than this voltage and supply with as data-signal, on the other hand, specified the common electrode 108 of the row that negative polarity writes, when selecting the sweep trace 112 of this row, become relative higher voltage Vsh, will than this voltage low supply with as data-signal with the voltage of the low level side of gray scale correspondent voltage.

Therefore, the voltage amplitude of data-signal, the situation narrow certain with the voltage of common electrode 108, so reduced the desired resistance to pressure of composed component of data line drive circuit 190, can correspondingly seek the summary that constitutes, and also can suppress because change in voltage and the electric energy that consumes in vain.

But, the common electrode 108 (bridging line 108e) of each row, as mentioned above via the data line 114 and the intersection such as gate insulating film of 1～240 row, so the change in voltage of these data lines 114, be that the variation of data-signal X1～X240 is passed to common electrode 108 via stray capacitance.

Therefore, common electrode 108 with which part is not electrically connected, and then is subjected to the influence that the change in voltage (change in voltage of data-signal X1～X240) of each data line is produced, its potential change.Common electrode 108, independent line by line in the present embodiment, so common electrode carries out potential change with different line by line amounts, there is the possibility of baneful influence higher to display quality.

Relative therewith, in the present embodiment, such as odd number i is capable, for example in the n frame when sweep signal Yi becomes the H level, TFT 171,172 conductings that i is capable, thereby make TFT 173,174 conductings, disconnection, and at the gate electrode of TFT 173,174 parasitic electric capacity, write H, L level respectively, thus, even if when sweep signal Yi becomes the L level, still keep the capable TFT of i 173,174 conductings, off-state, as a result, continue capable common electrode 108 of odd number i and the 3rd state of being connected for electric wire 163.On the other hand, in the n frame, the common electrode that continues even number (i+1) row is connected in the 4th state to electric wire 164.Therefore, in the present embodiment, the common electrode 108 of each row is in the state that applies voltage Vsl or voltage Vsh usually under the full frame pattern, do not become high impedance status, so the reduction by the display quality that variation in voltage caused of common electrode can be prevented trouble before it happens.

Then, the action to partial mode describes.Figure 24 is the figure of an example of the action of each frame under the situation of expression partial mode, in the present embodiment, under partial mode, implements 12 actions that frame is 1 unit with the from the 1st to the 12nd frame.

In this example, be illustrated in the 1st～80 row and the 161st～320 is gone as non-display line, make and the corresponding pixel ineffective treatment of this non-display line, go as display line the 81st～160, only use under the situation about effectively showing with the corresponding pixel of this display line, at the pixel of each sweep trace that is positioned at the 1st～320 row, what kind of polarity to carry out voltage with and write.

In addition, under partial mode, about being positioned at the pixel of display line, the situation that has any one two values of white of carrying out independent conducting or the black that disconnects to show, but at this, the situation of carrying out the gray scale demonstration is described.

In the drawings, with+be positive polarity ,-be negative polarity, the situation that voltage writes is carried out in expression respectively, but * expression do not carry out the state that voltage writes.

At this, in the 1st and the 7th frame of partial mode, the 1st～80 row and the 161st～320 row at non-display line, the voltage that carries out negative polarity and positive polarity respectively writes, but this voltage writes, to show invalidly in order making, to write forcibly and the suitable voltage of black (disconnection) at the pixel of non-display line.On the other hand, in the 1st, the 4th, the 7th and the 10th frame of partial mode, the 81st～160 row to display line carries out voltage with the order of negative polarity, positive polarity, positive polarity and negative polarity respectively and writes.Therefore, in the present embodiment, under partial mode, adjacent lines each other to write polarity identical mutually.

With reference to Figure 25～Figure 27 the waveform of sweep signal under the represented partial mode of such Figure 24 etc. is described.At this, Figure 25 is the figure of waveform etc. of the sweep signal Y1～Y320 of expression the 1st～the 4th frame, Figure 26 makes the figure of waveform etc. of the sweep signal Y1～Y320 of expression the 5th～the 8th frame, and Figure 27 is the figure of waveform etc. of the sweep signal Y1～Y320 of expression the 9th～the 12nd frame.

As shown in figure 25, in the 1st frame of partial mode, sweep signal Y1～Y320, identical with the full frame pattern.But, in the present embodiment, be fixed as the L level at the 1st frame Semi-polarity specification signal Pol, so in the non-display line of the 1st～80 row and the 161st～320 row, write the suitable voltage of black (disconnection) with negative polarity, display line at the 81st～160 row writes the gray scale correspondent voltage with negative polarity.

In the 2nd and the 3rd frame under partial mode, sweep signal Y1～Y320 does not become the H level, therefore, does not implement any write activity.

In the 4th frame under partial mode, only the related sweep signal Y81～Y160 of display line becomes the H level in order.In addition, in the 4th frame, sweep signal Y81～Y160 become the H level during, polarity specification signal Pol becomes the H level, so write gray scale correspondent voltage with positive polarity at the display line of the 81st～160 row.

Then, as shown in figure 26, in the 5th and the 6th frame under partial mode, with the 2nd and the 3rd frame similarly, sweep signal Y1～Y320 does not become the H level, therefore, does not implement any write activity.

In the 7th frame, sweep signal Y1～Y320 is identical with the full frame pattern.But, in the present embodiment, be fixed on the H level at the 7th frame Semi-polarity specification signal Pol, so in the non-display line of the 1st～80 row and the 161st～320 row, write the suitable voltage of black (disconnection) with positive polarity, display line at the 81st～160 row writes the gray scale correspondent voltage with positive polarity.

In the 8th frame and the 9th frame shown in Figure 27, sweep signal Y1～Y320 does not become the H level, therefore, does not implement any write activity.In the 10th frame under partial mode, only the related sweep signal Y81～Y160 of display line becomes the H level in order.In addition, in the 10th frame, sweep signal Y81～Y160 become the H level during, polarity specification signal Pol becomes the L level, so write gray scale correspondent voltage with negative polarity at the display line of the 81st～160 row.In addition, in the 11st frame and the 12nd frame, sweep signal Y1～Y320 does not become the H level, therefore, does not implement any write activity.

Below, in partial mode, repeat the action of the 1st～the 12nd frame.

Under the full frame pattern, implementing voltage frame by frame writes, but under partial mode, off voltage at the pixel of non-display line writes, implement with 1 such ratio of per 6 frames, the cycle that writes at the voltage of display line is to implement with 1 such ratio of per 3 frames, writes the electric energy that is consumed so suppress voltage.

But, under the full frame pattern, in common electrode drive circuit 170a, the TFT 173,174 that for example i is capable, remain on conducting or the off voltage that is applied to when sweep signal Yi becomes the H level on the gate electrode by stray capacitance, even if thereby during sweep signal Yi becomes the L level, the current potential of the capable common electrode of i 108 is determined.

But, in such partial mode, compare with the full frame pattern and become less because sweep signal becomes frequency that voltage that the H level implemented writes.Therefore, such possibility is arranged,,, become at last below the threshold value, and the situation of conducting state takes place to keep because electric leakage waits and slowly reduces by any one the forward voltage that gate electrode kept of TFT173 or 174.

For fear of such situation, also considered in the gate electrode additional capacitive element of TFT 173,174 formation with the influence that reduces electric leakage, but the extra space that is used to form this capacity cell must be arranged, correspondingly the outside of viewing area, so-called fringe region broadens.

So in the present embodiment, under partial mode, as mentioned above, control circuit 20 is supplied with control signal Vg-c and shared signal Vc.That is, control circuit 20 only is made as the H level with control signal Vg-c in the 3rd, the 8th and the 9th frame, shared signal Vc is made as voltage Vsh in the 2nd and the 3rd frame, is made as voltage Vsl in the 8th and the 9th frame.

In the 1st frame before, polarity specification signal Pol is the L level, so signal Vg-a is same L level, signal Vg-b is the H level of counter-rotating.Therefore, in common electrode drive circuit 170a, in odd number i is capable when sweep signal Yi becomes the H level during TFT 171,172 conductings, gate electrode to TFT 173,174 applies disconnection, forward voltage respectively, so common electrode 108 that this i is capable, write the voltage Vsh that correspondingly becomes high-order side with negative polarity, similarly, even if OK at even number (i+1), also the gate electrode to TFT 173,174 applies disconnection, forward voltage respectively, so the common electrode 108 of this (i+1) row becomes voltage Vsh.

In the 2nd and the 3rd frame, sweep signal does not become the H level, so also exist the grid voltage owing to leak electricity etc. of the TFT 173,174 of each row to reduce, can not keep the possibility of conducting state, in common electrode drive circuit 170b, TFT 175 of each row is because control signal Vg-c becomes the H level and conducting together, so no matter the grid voltage of TFT 173,174 is conducting/disconnection, whole common electrodes 108 and the 1st frame similarly are defined as the voltage Vsh of shared signal Vc.

In addition, in the 4th frame, sweep signal Y81～Y160 become in order the H level during polarity specification signal Pol become the H level, so signal Vg-a is the H level, signal Vg-b for the counter-rotating the L level.

In common electrode drive circuit 170a, when the related sweep signal of display line becomes the H level and makes TFT 171,172 conductings, gate electrode to TFT 173,174, apply conducting, off voltage respectively, thus, TFT 173,174 conductings respectively, disconnection are so the common electrode 108 of display line writes the voltage Vsl that correspondingly switches to the low level side with positive polarity.

On the other hand, the 7th～10 frame is implemented the action of the relation of the polarity in counter-rotating the 1st～the 4th frame.

Like this, according to present embodiment, under partial mode, even if all row are being carried out beyond the 1st and the 7th frame that voltage writes, in the 2nd, the 3rd, the 8th and the 9th frame, the current potential of common electrode 108 is also determined, so correspondingly, can suppress the reduction of display quality.

In the present embodiment, in the 2nd, the 3rd, the 8th and the 9th frame, control signal Vg-c is made as the H level, so that the current potential of common electrode 108 is determined, but as long as after all row being carried out the 1st (the 7th) frame that voltage writes, to for example can only in the 3rd and the 9th frame, control signal Vg-c being made as the H level in the forward frame of frame till the 4th (the 10th) that the voltage of display line only writes all or part of than carrying out.

(the 4th embodiment)

In the above-described 3rd embodiment, under the full frame pattern, it is the capable inversion mode that polarity is reversed line by line that writes to pixel, under partial mode, because display line becomes the common polarity that writes each other, so by the display quality of the shown pixel of the pixel of display line, compare variation with the situation of full frame pattern, this point is undeniable.

So, even if describe by the 4th embodiment that every sweep trace reverses under partial mode, still making display line write polarity each other.

Figure 28 is the block diagram of the formation of the related electro-optical device of expression the 4th embodiment.

Formation shown in this figure is that with the difference of Figure 18 in common electrode drive circuit 170b, the link of the source electrode of TFT 175 is divided into odd-numbered line and even number line.Specifically, the source electrode of the TFT 175 of odd-numbered line is connected in the first signal wire 167c that shared signal Vc-c is provided, and the source electrode of the TFT 175 of even number line is connected in provides the secondary signal of shared signal Vc-d line 167d.

In addition, Figure 29 is the viewing area 100 in the device substrate of expression the 4th embodiment and the planimetric map of the boundary vicinity of common electrode drive circuit 170b.

As shown in the drawing, the source electrode of the TFT 175 that odd number i is capable uses the part from signal wire 167 branches, and the source electrode of the TFT 175 of even number (i+1) row is connected in secondary signal line 167d via the wiring that is passed down through (ァ Application ダ one Network ロ ス) first signal wire 167c.

In addition, in the 4th embodiment, the action of full frame pattern, identical with the 3rd embodiment.But,, be that the center describes with the difference in the partial mode for the action of the 4th embodiment.

Figure 30 is the figure of an example that is illustrated in the action of each frame under the situation of partial mode.

Even if in the 4th embodiment, under partial mode, enforcement is with 12 actions that frame is 1 unit of the from the 1st to the 12nd, in addition the 1st～80 row and the 161st～320 is gone as non-display line, the 81st～160 row is carried out illustration as display line, and this point is identical with the 1st embodiment (with reference to Figure 23).

As shown in figure 30, writing polarity in the 1st frame under the partial mode, all is the polarity that writes of just now the full frame pattern of reversing for the both sides of display line and non-display line, specifies positive polarity to write to odd-numbered line respectively, and the dual numbers row specifies negative polarity to write.In addition, writing polarity in the 7th frame, is the polarity that writes polarity of counter-rotating the 1st frame.Any one of the 1st and the 7th frame all is the row inversion mode.

On the other hand, writing polarity in the 4th frame of display line, is the polarity that writes of counter-rotating the 1st frame, writes polarity in the 10th frame of display line, is the polarity that writes of counter-rotating the 7th frame, also all is the row inversion mode.

In addition, control circuit 20 in the 2nd and the 3rd frame, is made as voltage Vsl with shared signal Vc-c, and shared signal Vc-d is made as voltage Vsh, in the 8th and the 9th frame, shared signal Vc-c is made as voltage Vsh, and shared signal Vc-d is made as voltage Vsl.

With reference to Figure 31～Figure 33 the waveform of sweep signal under such partial mode shown in Figure 30 etc. is described.At this, Figure 31 is the figure of waveform etc. of the sweep signal Y1～Y320 of expression the 1st～the 4th frame, Figure 32 is the figure of waveform etc. of the sweep signal Y1～Y320 of expression the 5th～the 8th frame, and Figure 33 is the figure of waveform etc. of the sweep signal Y1～Y320 of expression the 9th～the 12nd frame.

As shown in these figures, under partial mode, sweep signal Y1～Y320 is identical with the partial mode of the 3rd embodiment.

In the 4th embodiment, the action of the 1st frame, except force to write the voltage suitable for non-display line, identical with the full frame pattern with black (disconnection).Therefore, the common electrode 108 that odd number i is capable writes the voltage Vsl that correspondingly becomes the low level side with positive polarity, and the common electrode 108 of even number (i+1) row writes the voltage Vsh that correspondingly becomes high-order side with negative polarity.

Then, in the 2nd and the 3rd frame of partial mode, signal Vg-c is the H level, in common electrode drive circuit 170b, the TFT 175 of the 1st～320 row all becomes conducting, so the common electrode 108 of odd-numbered line becomes the voltage Vsl of shared signal Vc-c, and the common electrode 108 of even number line, become the voltage Vsh of shared signal Vc-d, be defined as the voltage identical respectively and keep with the 1st frame.

In addition, in the 4th frame, sweep signal Y81～Y160 become in order the H level during in, the sweep signal of odd-numbered line become the H level during, polarity specification signal Pol becomes the L level, so the common electrode 108 by the common electrode drive circuit 170a odd-numbered line that display line is related writes the voltage Vsh that correspondingly is defined as high-order side with negative polarity, on the other hand, the common electrode 108 of the even number line that display line is related writes the voltage Vsl that correspondingly is defined as the low level side with positive polarity.

In the 7th～the 10th frame,, implement the action of the relation that writes polarity in counter-rotating the 1st～the 4th frame at each row.

Like this, according to the 4th embodiment, under partial mode, even if whole row are being carried out beyond the 1st and the 7th frame that voltage writes, in the 2nd, the 3rd, the 8th and the 9th frame, still determine the current potential of common electrode 108, so correspondingly can suppress the reduction of display quality.And then, according to the 4th embodiment, the display line in the partial mode to write polarity identical with the full frame pattern be capable inversion mode by the counter-rotating of every sweep trace, so but the display quality of retaining part pattern and full frame pattern identical.

(application variation)

In the 3rd and the 4th above-mentioned embodiment, so long as full frame pattern, can be made as the capable inversion mode that polarity is reversed line by line that writes, also can be made as row inversion mode, line by line and by the some inversion mode of row ground by the counter-rotating of pixel ground by row counter-rotatings to pixel.

In order to make it to become row inversion mode or some inversion mode, for example as shown in figure 34, every row is provided with two common electrode 108a, 108b, and as shown in figure 35, make the pixel 110 and common electrode 108a of odd number j row, the pixel 110 of even number (j+1) row and corresponding the getting final product of common electrode 108b difference.

And, in common electrode drive circuit 170a, constitute and followingly get final product like this, with the TFT173,174 of each row is TFT173a, 173b as two series respectively, with TFT174a, 174b, when the series of any one party is defined as common electrode 108a a side among voltage Vsl, the Vsh, common electrode 108 is defined as the opposing party among voltage Vsl, the Vsh in the opposing party's arbitrarily series.

In addition, in common electrode drive circuit 170b, make 175 liang of series of TFT turn to TFT 175a, 175b, make it corresponding with two common electrode 108a, 108b respectively.Specifically, the source electrode of TFT 175a is connected in common electrode 108a, and drain electrode is connected in the first signal wire 167c, and the source electrode of TFT175b is connected in common electrode 108b, and drain electrode is connected in secondary signal line 167d.

At this, in order to be made as the row inversion mode, for example when odd column is made as positive polarity, even column is made as negative polarity to get final product, so when the sweep signal of each row becomes the H level, to correspondingly be defined as the voltage Vsl of low level side with corresponding common electrode 108a of odd column and positive polarity, will get final product with the voltage Vsh that corresponding common electrode 108b of even column and negative polarity correspondingly are defined as high-order side.

On the other hand, in order to be made as an inversion mode, the row inversion mode is combined and gets final product with the row inversion mode, so for example when the odd-numbered line odd column is made as positive polarity, the odd-numbered line even column is made as negative polarity, ensuing even number line odd column is made as negative polarity, the even number line even column is made as positive polarity.Therefore, when the sweep signal of odd-numbered line becomes the H level, to correspondingly be defined as the voltage Vsl of low level side with corresponding common electrode 108a of odd column and positive polarity, to correspondingly be defined as the voltage Vsh of high-order side with corresponding common electrode 108b of even column and negative polarity, on the other hand, when the sweep signal of ensuing even number line becomes the H level, to correspondingly be defined as voltage Vsh with corresponding common electrode 108a of odd column and negative polarity, will correspondingly be defined as voltage Vsl with corresponding common electrode 108b of even column and positive polarity and get final product.

In addition, in any one of row inversion mode and some inversion mode, 1 horizontal scanning line is applied select voltage during, exist to the data-signal of odd column and the relation of reversing mutually to the data-signal of even column.In addition, in order to prevent that liquid crystal capacitance 120 is applied flip-flop, must make reversal of poles with the frame period of regulation.

In addition, in the above-described embodiment, with shared signal Vc-a, Vc-b, signal Vg-a, Vg-b, be made as waveform as shown in figure 22 respectively, but can make shared signal Vc-a, Vc-b by per image duration for example, each horizontal scan period (H) counter-rotating (replacement), and with this logic of specified signal Vg-a, Vg-b as one man of reversing.

Promptly, constitute and followingly get final product like this, promptly when the sweep signal to certain sweep trace becomes the H level, be about to common electrode at this and be made as and write the polarity correspondent voltage to this row, even and if this sweep signal becomes the L level, the common electrode of this row still continues to maintain this voltage.

In the above-described embodiment, for the capable TFT 171,172 of i, when having selected i capable sweep trace, sweep signal Yi to become the H level, make it become conducting state.At this, the TFT 171,172 that i is capable, decision is connected with first at the gate electrode of TFT 173,174 and gives electric wire 162 for electric wire 161, second, the this point that makes any one party of TFT 173,174 become conducting state, makes any the opposing party become off-state is very important, as long as the common electrode 108 that i is capable is defined as and writes the corresponding current potential of electrode,, be not so important then about when making TFT 171,172 conductings.

In addition, to write polarity be nonsensical because specify during vertical flyback, so polarity specification signal Pol, logical signals such as shared signal Vc-a, Vc-b can be fixed on certain level, their signal wire can be in high impedance status.

And, in embodiment, liquid crystal capacitance 120 is made as normal black pattern, but also can be made as the normal white mode that under no-voltage applies state, becomes bright state.In addition, can constitute a point, carry out colour and show, append another color (for example dark green (C)), constitute a point by these four pixels, to improve color reprodubility but also can constitute by R (red), G (green), three pixels of B (indigo plant).

(electronic equipment)

Next, describe as the example of the electronic equipment of display device having above-mentioned embodiment related electro-optical device 10.

Figure 36 is the figure of formation that expression has the mobile phone 1200 of the related electro-optical device of embodiment 10.As shown in the drawing, mobile phone 1200 possesses a plurality of action buttons 1202, also has receiving mouth 1204, and mouth piece 1206 also has above-mentioned electro-optical device 10.

In addition, as the electronic equipment that is suitable for electro-optical device 10, except mobile phone shown in Figure 36, can also enumerate equipment such as digital stillcamera, notebook computer, LCD TV, video recorder, guider, pager, electronic notebook, electronic calculator, word processor, worktable, videophone, POS terminal, touch panel.And what needn't illustrate is as the display device of these electronic equipments, can use above-mentioned electro-optical device 10.

Claims (15)

1. the driving circuit of an electro-optical device, described electro-optical device has: the multi-strip scanning line; Many data lines; The common electrode that is provided with accordingly with each bar of described multi-strip scanning line; And pixel;

Described pixel was provided with accordingly with intersecting of described sweep trace and described data line, and each pixel comprises:

The pixel switch element, the one end is connected with described data line, and becomes conducting state when described sweep trace being applied selection voltage; And

Pixel capacitance, the one end is connected with the other end of described pixel switch element, and the other end is connected with described common electrode;

Described pixel has and the corresponding gray scale of the sustaining voltage of this pixel capacitance;

Described driving circuit is characterised in that to possess:

Scan line drive circuit, its order in accordance with regulations applies described selection voltage to described multi-strip scanning line;

The common electrode drive circuit, it drives described a plurality of common electrodes each respectively; And

Data line drive circuit, it is via data line, to the corresponding pixel of the sweep trace that has applied described selection voltage, supply with data-signal with the gray scale correspondent voltage of this pixel;

Wherein, described common electrode drive circuit has:

On-off circuit, it is set to conducting or off-state according to the voltage that gate electrode kept, and this common electrode is applied the voltage of any side of low level side or high-order side when being set to described conducting state;

First applies circuit, and it is when applying described selection voltage with the paired sweep trace of this common electrode, and the gate electrode of described on-off circuit is applied the forward voltage that described on-off circuit is set at conducting state; And

Second applies circuit, its described sweep trace is not applied select voltage during, when the indication that has via the control line of regulation, the gate electrode of described on-off circuit is applied described forward voltage.

2. the driving circuit of the electro-optical device of putting down in writing according to claim 1 is characterized in that,

Described first applies circuit has first and transistor seconds,

Described on-off circuit has the 3rd and the 4th transistor,

Described second applies circuit has the 5th and the 6th transistor,

The gate electrode of described the first transistor is connected with described sweep trace, and first of its source electrode and the voltage of supplying with the side make described the 3rd transistor become conducting or off-state is connected to electric wire,

The gate electrode of described transistor seconds is connected with described sweep trace, and second of its source electrode and the voltage of supplying with the opposing party make described the 4th transistor become conducting or off-state is connected to electric wire,

The described the 3rd transistorized gate electrode is connected with the drain electrode of described the first transistor, and the 3rd of its source electrode and a side's who supplies with low level side or high-order side voltage is connected to electric wire,

The described the 4th transistorized gate electrode is connected with the drain electrode of described transistor seconds, and the 4th of its source electrode and the opposing party's who supplies with low level side or high-order side voltage is connected to electric wire,

The the described the 3rd and the 4th transistor drain electrode is connected with described common electrode each other,

The described the 5th transistorized gate electrode is connected with described control line, and its source electrode and described first and second is connected for a side of electric wire, and its drain electrode is connected with the described the 3rd transistorized gate electrode,

The described the 6th transistorized gate electrode is connected with described control line, and its source electrode and described first or second is connected for the opposing party of electric wire, and its drain electrode is connected with the described the 4th transistorized gate electrode.

3. the driving circuit of the electro-optical device of putting down in writing according to claim 2 is characterized in that,

Described common electrode drive circuit, in each of described sweep trace and common electrode, the described the 5th transistorized source electrode is connected in described first and gives electric wire, and the described the 6th transistorized source electrode is connected in described second and gives electric wire.

4. the driving circuit of the electro-optical device of putting down in writing according to claim 3 is characterized in that having:

First pattern that effectively shows with whole pixels; And

Only use second pattern that effectively shows with the corresponding pixel of a part of sweep trace;

Wherein, in described first pattern,

Described scan line drive circuit implements described multi-strip scanning line is applied in order the action of described selection voltage with the cycle of regulation,

When described sweep trace being applied selection voltage at every turn, will make described the 3rd transistor become the voltage reversal of conducting state and off-state and be supplied to described first and give electric wire,

At least one frame or more than the frame during, supply with a side's of described low level side or high-order side voltage to the described the 3rd to electric wire,

Described control line is supplied with the voltage that makes the described the 5th and the 6th transistor become off-state,

In described second pattern,

Described scan line drive circuit carries out described multi-strip scanning line is applied in order first action of described selection voltage with the cycle alternate repetition longer than the cycle of described regulation, apply second action of described selection voltage in order with sweep trace to a described part

The sweep trace to a described part apply described selection voltage during, when described first moves, apply a side who makes described the 3rd transistor become the voltage of conducting state or become the voltage of off-state to electric wire to described first, when described second moves, apply the opposing party who makes described the 3rd transistor become the voltage of conducting state or become the voltage of off-state to electric wire to described first

At least one frame or more than the frame during, supply with a side's of described low level side or high-order side voltage to the described the 3rd to electric wire,

During beginning to described second action part or all from described first release, make the described the 5th and the 6th transistor become the voltage of conducting state to described control line supply, during in addition, make the described the 5th and the 6th transistor become the voltage of off-state to described control line supply.

5. the driving circuit of the electro-optical device of putting down in writing according to claim 2 is characterized in that,

Described common electrode drive circuit, in described sweep trace and common electrode,

The 5th transistorized source electrode of odd-numbered line is connected in described second and gives electric wire, and the 6th transistorized source electrode of odd-numbered line is connected in described first and gives electric wire,

The 5th transistorized source electrode of even number line is connected in described first and gives electric wire, and the 6th transistorized source electrode of even number line is connected in described second and gives electric wire.

6. the driving circuit of the electro-optical device of putting down in writing according to claim 5 is characterized in that having:

First pattern that effectively shows with whole pixels; And

Only use second pattern that effectively shows with the corresponding pixel of a part of sweep trace;

In described first pattern,

Described scan line drive circuit implements described multi-strip scanning line is applied in order the action of described selection voltage with the cycle of regulation,

When described sweep trace being applied selection voltage at every turn, will make described the 3rd transistor become the voltage reversal of conducting state and off-state and be supplied to described first and give electric wire,

At least one frame or more than the frame during, supply with a side's of described low level side or high-order side voltage to the described the 3rd to electric wire,

Described control line is supplied with the voltage that makes the described the 5th and the 6th transistor become off-state,

In described second pattern,

Described scan line drive circuit carries out described multi-strip scanning line is applied in order first action of described selection voltage with the cycle alternate repetition longer than the cycle of described regulation, apply second action of described selection voltage in order with sweep trace to a described part

When described first and second action, when described sweep trace being applied selection voltage at every turn, will make described the 3rd transistor become the voltage reversal of conducting state and off-state and be supplied to described first and give electric wire,

At least one frame or more than the frame during, supply with a side's of described low level side or high-order side voltage to the described the 3rd to electric wire,

During beginning to described second action part or all from described first release, make the described the 5th and the 6th transistor become the voltage of conducting state to described control line supply, during in addition, make the described the 5th and the 6th transistor become the voltage of off-state to described control line supply.

7. electro-optical device is characterized in that possessing:

The multi-strip scanning line; Many data lines; The common electrode that is provided with accordingly with each bar of described multi-strip scanning line;

Pixel, it was provided with accordingly with intersecting of described sweep trace and described data line, and wherein each pixel comprises: the pixel switch element, the one end is connected with described data line, and becomes conducting state when described sweep trace being applied selection voltage; And pixel capacitance, the one end is connected with the other end of described pixel switch element, and the other end is connected with described common electrode; And wherein, described pixel has and the corresponding gray scale of the sustaining voltage of this pixel capacitance;

Scan line drive circuit, its order in accordance with regulations applies described selection voltage to described multi-strip scanning line;

The common electrode drive circuit, it drives described a plurality of common electrodes each respectively; And

Data line drive circuit, it is via data line, to the corresponding pixel of the sweep trace that has applied described selection voltage, supply with data-signal with the gray scale correspondent voltage of this pixel;

Wherein, described common electrode drive circuit has:

On-off circuit, it is set to conducting or off-state according to the voltage that gate electrode kept, and this common electrode is applied a side's of low level side or high-order side voltage when being set to described conducting state;

First applies circuit, and it is when applying described selection voltage with the paired sweep trace of this common electrode, and the gate electrode of described on-off circuit is applied the forward voltage that described on-off circuit is set at conducting state; And

Second applies circuit, its described sweep trace is not applied select voltage during, when the indication that has via the control line of regulation, the gate electrode of described on-off circuit is applied described forward voltage.

8. the driving circuit of an electro-optical device, described electro-optical device has: the multi-strip scanning line; Many data lines; The common electrode that is provided with accordingly with each bar of described multi-strip scanning line; And pixel;

Described pixel was provided with accordingly with intersecting of described sweep trace and described data line, and each pixel comprises:

The pixel switch element, the one end is connected with described data line, and becomes conducting state when described sweep trace being applied selection voltage; And

Pixel capacitance, the one end is connected with the other end of described pixel switch element, and the other end is connected with described common electrode;

Described pixel has and the corresponding gray scale of the sustaining voltage of this pixel capacitance;

Described driving circuit is characterised in that to possess:

Scan line drive circuit, its order in accordance with regulations applies described selection voltage to described multi-strip scanning line;

The common electrode drive circuit, it drives described a plurality of common electrodes each respectively; And

Data line drive circuit, it is via data line, to the corresponding pixel of the sweep trace that has applied described selection voltage, supply with data-signal with the gray scale correspondent voltage of this pixel;

Wherein, described common electrode drive circuit for each described common electrode, has:

On-off circuit, it is set to conducting or off-state according to the voltage that gate electrode kept, and this common electrode is applied the voltage of any side of low level side or high-order side when being set to described conducting state;

First applies circuit, and it is when applying described selection voltage with the paired sweep trace of this common electrode, and the gate electrode of described on-off circuit is applied the forward voltage that described on-off circuit is set at conducting state; And

Second applies circuit, and it when the indication that has via the control line of regulation, applies the voltage of any side of described low level side or high-order side to each of described common electrode once more after the selection voltage application of described sweep trace is finished.

9. the driving circuit of the electro-optical device of being put down in writing according to Claim 8 is characterized in that,

Described first applies circuit has first and transistor seconds,

Described on-off circuit has the 3rd and the 4th transistor,

Described second applies circuit has the 5th transistor,

In described the first transistor, its gate electrode is connected with described sweep trace, and first of its source electrode and the voltage of supplying with the side make described the 3rd transistor become conducting or off-state is connected to electric wire,

In described transistor seconds, its gate electrode is connected with described sweep trace, and second of its source electrode and the voltage of supplying with the opposing party make described the 4th transistor become conducting or off-state is connected to electric wire,

In described the 3rd transistor, its gate electrode is connected with the drain electrode of described the first transistor, and the 3rd of its source electrode and a side's who supplies with low level side or high-order side voltage is connected to electric wire,

In described the 4th transistor, its gate electrode is connected with the drain electrode of described transistor seconds, and the 4th of its source electrode and the opposing party's who supplies with low level side or high-order side voltage is connected to electric wire,

The the described the 3rd and the 4th transistor drain electrode is connected with described common electrode each other,

In described the 5th transistor, its gate electrode is connected with described control line, and its source electrode is connected with the signal wire of the voltage of any side of supplying with low level side or high-order side, and its drain electrode is connected with described common electrode.

10. the driving circuit of the electro-optical device of putting down in writing according to claim 9 is characterized in that,

The described the 5th transistorized source electrode is connected in common signal wire in each row of described sweep trace and common electrode.

11. the driving circuit of the electro-optical device of putting down in writing according to claim 10 is characterized in that having:

First pattern that effectively shows with whole pixels; And

Only use second pattern that effectively shows with the corresponding pixel of a part of sweep trace;

Wherein, in described first pattern,

Described scan line drive circuit implements described multi-strip scanning line is applied in order the action of described selection voltage with the cycle of regulation,

When described sweep trace being applied selection voltage at every turn, will make described the 3rd transistor become the voltage reversal of conducting state and off-state and be supplied to described first and give electric wire,

At least one frame or more than the frame during, supply with a side's of described low level side or high-order side voltage to the described the 3rd to electric wire,

Make described the 5th transistor become the voltage of off-state to described control line supply,

In described second pattern,

Described scan line drive circuit carries out described multi-strip scanning line is applied in order first action of described selection voltage with the cycle alternate repetition longer than the cycle of described regulation, apply second action of described selection voltage in order with sweep trace to a described part

The sweep trace to a described part apply described selection voltage during, when described first moves, apply a side who makes described the 3rd transistor become the voltage of conducting state or become the voltage of off-state to electric wire to described first, when described second moves, apply the opposing party who makes described the 3rd transistor become the voltage of conducting state or become the voltage of off-state to electric wire to described first

At least one frame or more than the frame during, supply with a side's of described low level side or high-order side voltage to the described the 3rd to electric wire,

During beginning to described second action part or all from described first release, make described the 5th transistor become the voltage of conducting state to described control line supply, during in addition, make described the 5th transistor become the voltage of off-state to described control line supply.

12. the driving circuit of the electro-optical device of putting down in writing according to claim 9 is characterized in that,

In described sweep trace and common electrode,

The 5th transistorized source electrode of odd-numbered line is connected with first signal wire of a side's who supplies with low level side or high-order side voltage,

The 5th transistorized source electrode of even number line is connected with the secondary signal line of the opposing party's who supplies with low level side or high-order side voltage.

13. the driving circuit of the electro-optical device of putting down in writing according to claim 12 is characterized in that having:

First pattern that effectively shows with whole pixels; And

Only use second pattern that effectively shows with the corresponding pixel of a part of sweep trace;

Wherein, in described first pattern,

Described scan line drive circuit implements described multi-strip scanning line is applied in order the action of described selection voltage with the cycle of regulation,

When described sweep trace being applied selection voltage at every turn, will make described the 3rd transistor become the voltage reversal of conducting state and off-state and be supplied to described first and give electric wire,

At least one frame or more than the frame during, supply with a side's of described low level side or high-order side voltage to the described the 3rd to electric wire,

Make described the 5th transistor become the voltage of off-state to described control line supply,

In described second pattern,

Described scan line drive circuit carries out described multi-strip scanning line is applied in order first action of described selection voltage with the cycle alternate repetition longer than the cycle of described regulation, apply second action of described selection voltage in order with sweep trace to a described part

When described first and second action, when described sweep trace being applied selection voltage at every turn, will make described the 3rd transistor become the voltage reversal of conducting state and off-state and be supplied to described first and give electric wire,

At least one frame or more than the frame during, supply with a side's of described low level side or high-order side voltage to the described the 3rd to electric wire,

During beginning to described second action part or all from described first release, make described the 5th transistor become the voltage of conducting state to described control line supply, during in addition, make described the 5th transistor become the voltage of off-state to described control line supply.

14. an electro-optical device is characterized in that possessing:

The multi-strip scanning line; Many data lines; The common electrode that is provided with accordingly with each bar of described multi-strip scanning line;

Pixel, it was provided with accordingly with intersecting of described sweep trace and described data line, and wherein each pixel comprises: the pixel switch element, the one end is connected with described data line, and becomes conducting state when described sweep trace being applied selection voltage; And pixel capacitance, the one end is connected with the other end of described pixel switch element, and the other end is connected with described common electrode; And wherein, described pixel has and the corresponding gray scale of the sustaining voltage of this pixel capacitance;

Scan line drive circuit, its order in accordance with regulations applies described selection voltage to described multi-strip scanning line;

The common electrode drive circuit, it drives described a plurality of common electrodes each respectively; And

Data line drive circuit, it is via data line, to the corresponding pixel of the sweep trace that has applied described selection voltage, supply with data-signal with the gray scale correspondent voltage of this pixel;

Wherein, described common electrode drive circuit has:

On-off circuit, it is set to conducting or off-state according to the voltage that gate electrode kept, and this common electrode is applied the voltage of any side of low level side or high-order side when being set to described conducting state;

First applies circuit, and it is when applying described selection voltage with the paired sweep trace of this common electrode, and the gate electrode of described on-off circuit is applied the forward voltage that described on-off circuit is set at conducting state; And

Second applies circuit, and it when the indication that has via the control line of regulation, applies the voltage of any side of described low level side or high-order side to each of described common electrode once more after the selection voltage application of described sweep trace is finished.

15. an electronic equipment is characterized in that having:

According to claim 7 or 14 electro-optical devices of being put down in writing.

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