JP2010107808A - Electro-optic device, drive circuit and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress a voltage amplitude in a data line with a simple configuration, and to prevent a system down phenomenon immediately after turning on a power supply. <P>SOLUTION: A pixel includes a pixel capacitance with one terminal connected to a pixel electrode and the other terminal connected to a common electrode 108. The common electrode 108 is provided according to each of 1 to 320 rows, and a common electrode drive circuit is provided in both sides of each common electrode 108 in 1 to 320 rows. The common electrode drive circuit includes a unit control circuit 152 corresponding to each common electrode 108, and each unit control circuit 152 includes a transmission gate 52 that is turned on when a scanning line immediately above or immediately below is selected, and a latch circuit 60 latching a voltage just before the transmission gate 52 is turned off and holding the common electrode 108 at the inverted voltage. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

The present invention relates to a technique for suppressing the voltage amplitude of a data line in an electro-optical device such as a liquid crystal.

In an electro-optical device such as a liquid crystal, a pixel capacitor (liquid crystal capacitor) is provided corresponding to the intersection of a scanning line and a data line. When this pixel capacitor needs to be AC driven, the voltage amplitude of the data signal is positive or negative. Across both polarities. For this reason, in the data line driving circuit for supplying the data signal to the data line, not only the withstand voltage corresponding to the voltage amplitude is required for the constituent elements, but also the power consumption is disadvantageous.
Therefore, the common electrode is individualized corresponding to the scanning line, and a voltage selection signal is generated according to the progress of selection of the scanning line, and the common electrode corresponding to the selected scanning line when the scanning line is selected. On the other hand, a technique is known in which one of binary voltages corresponding to the writing polarity is selected and applied in accordance with the voltage selection signal (see Patent Document 1).
See JP 2008-33296 A

By the way, since the common electrode has a large resistance component and capacitance component, in the configuration in which the common electrode is driven only on one side, waveform dullness occurs on the other side when the voltage is switched, resulting in display quality. May be reduced. For this reason, a configuration in which the common electrode is driven from both sides has also been proposed.
However, in the configuration in which the common electrode is driven from both sides, since the scanning line is not selected immediately after the power is turned on, the voltage selection signals on both sides may be different from each other. If the voltage selection signals are different on both sides, the high voltage of the binary voltage is applied to one side and the low voltage of the binary voltage is applied to the same common electrode on the other side. As a result, there was a concern that the system would go down immediately after the power was turned on.
The present invention has been made in view of such circumstances, and one of its purposes is to provide a technique that prevents a system failure immediately after power-on in a configuration in which a common electrode is driven from both sides. .

In order to achieve the above object, a drive circuit for an electro-optical device according to the present invention includes a plurality of scanning lines, a plurality of data lines, a common electrode provided corresponding to the plurality of scanning lines, and the plurality of scanning lines. The scanning lines and the plurality of data lines are respectively provided corresponding to the intersections, each of which is connected to the data line at one end and is connected to the one end and the other end when the scanning line is selected. A pixel switching element that is in a conductive state between the pixel switching element and a pixel that includes a pixel capacitor having one end connected to the other end of the pixel switching element and the other end connected to a common electrode. And a scanning line driving circuit for selecting the scanning lines in a predetermined order, and a binary voltage at a predetermined cycle with respect to the common electrode corresponding to the one scanning line in a period in which the one scanning line is selected. The common signal to be switched When a positive polarity is specified for the pixel corresponding to the one scanning line so that the pixel electrode is higher than the potential of the common electrode, the lower voltage of the binary voltages is specified. Is applied to the pixel corresponding to the one scanning line, and a negative polarity is designated such that the pixel electrode is on the lower side of the potential of the common electrode. A common electrode driving circuit for applying a side voltage, and a data line driving for supplying a data signal of a voltage corresponding to the gradation and polarity of the pixel to the pixel corresponding to the one scanning line via the data line The common electrode driving circuit includes a unit control circuit provided corresponding to each of the common electrodes on each of one end side and the other end side of the common electrode, and one common electrode The unit control circuit corresponding to An input terminal is connected to the signal line to which the common signal is supplied, and becomes conductive during a period in which a scanning line corresponding to the one common electrode or a scanning line separated by a predetermined row from the scanning line is selected. And a latch circuit that latches and applies the common signal to the one common electrode when the switch is turned on. According to the present invention, in the unit control circuit provided on each of the one end side and the other end side immediately after power-on or the like, one switch is turned on,
Even if the other switch is turned off, a short-circuit state is not generated between the binary voltages via the common electrode, so that system down can be prevented.

In the present invention, the common signal may have a cycle in which scanning lines are selected one by one, and the voltage is switched at a timing when none of the scanning lines is selected. According to this configuration, 1H inversion that inverts the writing polarity for each scanning line is possible.
In the present invention, the common signal includes a first common signal and a second common signal, and an input terminal of the switch in the unit control circuit supplies the first common signal every two scanning lines. The signal line and the signal line that supplies the second common signal may be alternately connected. According to this configuration, in addition to the 1H inversion, 2H inversion in which the writing polarity is inverted every time two scanning lines are selected can be dealt with.
Note that the present invention is not only a drive circuit for an electro-optical device, but also an electro-optical device.
It can also be conceptualized as an electronic device.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<First Embodiment>
First, a first embodiment of the present invention will be described. FIG. 1 is a block diagram showing the configuration of the electro-optical device according to the first embodiment of the invention.
As shown in this figure, the electro-optical device 10 has a display area 100, and a scanning line driving circuit 140, common electrode driving circuits 150L and 150R, and a data line driving circuit 190 are arranged around the display area 100. The peripheral circuit built-in panel configuration. The display control circuit 20 is different from the peripheral circuit built-in panel, for example, FPC (flexible printed cir
cuit) connected by board.

The display area 100 is an area in which the pixels 110 are arranged. In the present embodiment, the display area 100 is 3 from the 0th row.
While a total of 322 scanning lines 112 up to the 21st row extend in the horizontal (row) direction in the figure,
The 240 data lines 114 are provided so as to extend in the vertical (column) direction.
In FIG. 1, corresponding to the intersection of the scanning lines 112 of the 1st to 320th lines excluding the uppermost 0th line and the lowermost 321st line, and the data lines 114 of the 1st to 240th columns, Pixels 110 are arranged respectively. Therefore, in this embodiment, the pixels 110 are arranged in a matrix of 320 rows × 240 columns in the display region 100, but the present invention is not limited to this arrangement.

Note that the scanning lines 112 in the 0th and 321st rows do not correspond to the pixels 110, so
It will function as a dummy scanning line. Further, the common electrodes 108 are provided so as to extend in the row direction so as to correspond to the scanning lines 112 in the first to 320th rows, respectively. For this reason, in the present embodiment, the common electrode 108 is a dummy in the 0th row and the 32nd row.
The scanning lines 112 corresponding to the 1st to 320th scanning lines excluding the 1st row are provided.

Here, a detailed configuration of the pixel 110 will be described. FIG. 2 is a diagram illustrating the configuration of the pixel 110, and an intersection of the i-th row and the (i + 1) th row adjacent to the i-th row in the downward direction and the j-th column and the (j + 1) -th column adjacent to the j-th column in the right direction. A configuration for a total of 4 pixels of 2 × 2 corresponding to is shown.
Note that i and (i + 1) are 1 or more and 3 when generally indicating a row in which the pixels 110 are arranged.
Although it is an integer of 20 or less, when generally describing the row of the scanning line 112, since it is necessary to include the 0th and 321st rows which are dummy, it is an integer of 0 to 321. Also,
j and (j + 1) are symbols for generally indicating a column in which the pixels 110 are arranged, and are integers of 1 or more and 240 or less.

As shown in FIG. 2, each pixel 110 includes an n-channel thin film transistor (hereinafter simply referred to as “TFT”) 1 that functions as a pixel switching element.
16, a pixel capacity (liquid crystal capacity) 120, and an auxiliary capacity 130. Since each pixel 110 has the same configuration, the pixel 116 in the i row and j column will be explained as a representative example. In the pixel 110 in the i row and j column, the TFT 116 has its gate electrode connected to the scanning line 112 in the i row. The source electrode is connected to the data line 114 in the j-th column, and the drain electrode is connected to the pixel electrode 118 that is one end of the pixel capacitor 120 and one end of the auxiliary capacitor 130. The other end of the pixel capacitor 120 and the other end of the auxiliary capacitor 130 are connected to the i-th common electrode 108, respectively.
In FIG. 2, Yi and Y (i + 1) indicate scanning signals supplied to the scanning lines 112 in the i and (i + 1) th rows, respectively, and Com i and Com (i + 1) are The voltages of the common electrode 108 in the i and (i + 1) th rows are shown.

Although not particularly illustrated, the present embodiment has a configuration in which liquid crystal is sealed between an element substrate and a counter substrate, and is an FFS (fringe field switching) mode in which the electric field direction applied to the liquid crystal is the substrate surface direction. is there. More specifically, a common electrode is formed in a strip shape on the element substrate, and a comb-like pixel electrode is formed via an insulating layer, whereby, between the pixel electrode 118 and the common electrode 108, It becomes a kind of capacitance by the structure through the liquid crystal as a dielectric, and the electric field applied to the liquid crystal changes in the direction along the substrate surface according to the effective value of the voltage held by this capacitance component. Yes.
In the present embodiment, for convenience of explanation, when the effective voltage value held in the pixel capacitor 120 becomes a value close to zero, the light transmittance becomes the maximum white display, while the effective voltage value increases. It is assumed that the normally white mode in which the rate gradually decreases and finally the black display with the minimum transmittance is obtained.
The auxiliary capacitance 130 is a capacitance component generated by a stacked structure in which the pixel electrode 118 and the common electrode 108 are interposed via an insulating layer. Further, the pixel 110 may be in a mode other than the FFS mode as long as its electrical equivalent circuit is a circuit as shown in FIG.

Returning to FIG. 1 again, the display control circuit 20 outputs various control signals to control each part in the electro-optical device 10 and the like, and outputs the common signal Com to the common electrode drive circuit 15.
0L and 150R are supplied via a signal line 153.

As described above, peripheral circuits such as the scanning line driving circuit 140, the common electrode driving circuits 150L and 150R, and the data line driving circuit 190 are provided around the display region 100. Among these, the scanning line driving circuit 140 selects the scanning lines 112 in the order of 0, 1, 2, 3,..., 320, 321 rows counted from the top in FIG. The scanning signal for the selected scanning line is set to a selection voltage VH corresponding to the H level, and the scanning signals for the other scanning lines are set to the non-selection voltage VL corresponding to the L level.
Specifically, as shown in FIG. 4, the scanning line driving circuit 140 sequentially shifts the start pulse Dy supplied from the display control circuit 20 according to the clock signal Cly having a duty ratio of 50%, The width is narrower than a half cycle of the clock signal Cly, and is shifted forward in time, and output as scanning signals Y0, Y1, Y2, Y3, Y4,..., Y320, Y321.
Here, the frame period refers to a period required to display one frame of an image by driving the panel, and is the reciprocal if the vertical scanning frequency is 60 Hz.
7 milliseconds. In this embodiment, as shown in FIG. 4, such a frame period includes the vertical effective scanning period Fa from when the scanning signal Y1 becomes H level to when the scanning signal Y320 becomes L level, and other than that. Includes a vertical blanking period.
A period corresponding to a half cycle of the clock signal Cly is defined as a horizontal scanning period (H). In the horizontal scanning period (H), when a period in which the scanning signal is at the H level in the front in time is a horizontal effective scanning period, the remaining period is a horizontal blanking period.

Next, for convenience of explanation, among the control signals output from the display control circuit 20, the polarity designation signal Pol
The common signal Com will be described.
First, the polarity designation signal Pol is a signal that designates the writing polarity in the horizontal effective period as negative when the logic level is H level, and the writing polarity in the horizontal effective period when the logic level is L level. This signal specifies positive polarity.
In the present embodiment, the polarity designation signal Pol has a timing that precedes the timing at which the logic level of the clock signal Cly is switched every period in which the logic level is the same as that of the horizontal scanning period. Are switched during a horizontal blanking period in which all of the scanning signals to L are at L level. Therefore, in this embodiment, a scanning line (line) inversion method in which the polarity of writing to the pixel is inverted for each row over the period of the frame.

The polarity designation signal Pol is logically inverted when compared in the same horizontal effective period between adjacent frame periods. The reason for the logical inversion is to prevent the deterioration of the liquid crystal due to the application of a DC component. is there.
As for the writing polarity in the present embodiment, when the voltage corresponding to the gradation is held in the pixel capacitor 120, the potential of the pixel electrode 118 is higher than the potential of the common electrode 108. The case of the lower side is called negative polarity. Regarding the voltage, unless otherwise specified, the ground potential of the power supply (not shown) is used as a reference for the voltage zero.
Next, as shown in FIG. 4, the common signal Com is a signal synchronized with the polarity designation signal Pol, and if the polarity designation signal Pol is at the L level, the low-order voltage VcL among the binary voltages. When the polarity designation signal Pol is at the H level, the signal becomes the higher voltage VcH.

If the positive polarity writing is designated by the polarity designation signal Pol for the pixel 110 located on the scanning line 112 selected by the scanning line driving circuit 140, the data line driving circuit 190 uses the voltage VcL as a reference. If the designated gradation value becomes darker, and the negative polarity writing is designated, a voltage data signal that becomes lower as the designated gradation value becomes darker with respect to the voltage VcH. It is supplied via the data line 114. The data line driving circuit 190 executes this supply operation for each of the 1st to 240th columns positioned on the selected scanning line 112.
The data line driving circuit 190 has a configuration as follows. That is,
The data line driving circuit 190 has storage areas (not shown) corresponding to a matrix arrangement of 320 rows × 240 columns, and each storage area has a gradation (brightness) of the corresponding pixel 110.
Is stored. The display data Da stored in each storage area is rewritten by the display control circuit 20 by supplying the changed display data Da together with the address when the display contents are changed. The data line driving circuit 190 reads out the display data Da of the pixels 110 located on the selected scanning line 112 from the storage area, and
The read display data is converted into a data signal having a voltage corresponding to the designated polarity and supplied to the data line 114.

The common electrode drive circuit 150L is disposed on the left side in FIG. 1 with respect to the display region 100, and the common electrode drive circuit 150R is disposed on the right side in the display region 100. Each of the common electrode drive circuits 150L and 150R has a unit control circuit 152 corresponding to the first to 320th rows, and each unit control circuit 152 drives the common electrode 108 from both sides. In the present embodiment, the common electrode driving circuits 150L and 150R are connected to the display area 100.
However, the electrical configuration is the same. For this reason, the electrical configuration will be described by using the common electrode driving circuit 150L as a representative.

FIG. 3 is a diagram showing a configuration of the unit control circuit 152 corresponding to the i-th row and the (i + 1) -th row in the common electrode driving circuit 150L.
As shown in this figure, the unit control circuit 152 in each row includes a NOR circuit 51, a transmission gate 52, an inverter 53, and a latch circuit 60.
Of these, the unit control circuit 152 in the i-th row will be described. Of the two input terminals in the NOR circuit 51, one input terminal is the (i−1) -th row, which is one row above the i-th row. The scanning signal Y (i-1) is supplied to the scanning line 112, while the other input terminal is connected to the scanning line 112 in the (i + 1) th row below the scanning line Y (i + 1). i + 1) is supplied.
The output terminal of the NOR circuit 51 is connected to the inversion control terminal of the transmission gate 52 and the input terminal of the inverter 53, respectively. Here, for convenience, the inverter 5
When the output terminal 3 is expressed as P, the terminal P is connected to the forward rotation control terminal of the transmission gate 52.
Since the terminal P is an output terminal of the inverter 53 that logically inverts the output signal of the NOR circuit 51, a logical sum signal of the scanning signal Y (i-1) and the scanning signal Y (i + 1) is output. It is equivalent to the output terminal of the OR circuit.

The transmission gate 52 is a complementary analog switch whose input terminal is connected to the signal line 153 to which the common signal Com is supplied and whose output terminal is connected to the input terminal of the latch circuit 60. When the control terminal is at the H level (the inversion control terminal is at the L level), the input terminal and the output terminal are turned on (conductive), and the normal rotation control terminal is at the L level (the inversion control terminal is at the H level). At some point, it is turned off (non-conducting).

The latch circuit 60 includes inverters 62 and 64. An input terminal of the latch circuit 60 is an input terminal of the inverter 62, and an output terminal of the latch circuit 60 is an output terminal of the inverter 62. The output terminal of the inverter 62 is connected to the i-th common electrode 108 and the input terminal of the inverter 64, and the output terminal of the inverter 64 is connected to the input terminal of the inverter 62.
Note that, unlike the other logic circuits, the inverters 62 and 64 in the latch circuit 60 use the voltage VcL as the lower power supply and the voltage VcH as the higher power supply among the binary voltages that can be taken by the common signal Com. The threshold voltage of the inverters 62 and 64 is set between the voltages VcL and VcH.

The terminal P in the unit control circuit 152 in the i-th row is connected to the scanning signal Y (i−1) supplied to the scanning line 112 on the first row or the scanning signal Y (i +) supplied to the scanning line 112 on the lower row. When 1) becomes H level, it becomes H level. When the terminal P becomes H level, the transmission gate 52 is turned on, so that the voltage of the common signal Com supplied to the signal line 153 becomes the latch circuit 60.
And is applied to the i-th common electrode 108.
Note that when the terminal P becomes L level, the transmission gate 52 is turned off, but the common electrode 108 is held by the latch circuit 60 at a voltage just before the terminal P is turned off.
Needless to say, the unit control circuit 152 includes the common electrode driving circuits 150L and 150L.
In R, they are arranged on both the left and right sides of the common electrode 108, respectively.

Here, since the common signal Com is switched from one of the voltages VcL and VcH to the other for each horizontal scanning period, the same voltage is used when the scanning signal on the first row and the scanning signal on the first row are at the H level. is there. Further, the scanning signals Y0, Y1, Y2,..., Y319, Y320, Y321 sequentially become H level as shown in FIG.
Therefore, the common electrode 10 in the 320th row from the voltage Com1 of the common electrode 108 in the first row.
The voltage up to voltage Com320 of 8 is as shown in FIG. 4, and after the voltage is switched at the timing when the scanning signal on one row becomes H level, the scanning signal on one row again appears after the frame period elapses. The waveform is held until it becomes H level.

Next, the operation of the electro-optical device 10 according to this embodiment will be described.
First, the scanning signal Y0 becomes H level. Even if the scanning signal Y0 becomes H level, the scanning line 112 in the 0th row is a dummy and does not affect the voltage writing to the pixel 110 at all, but the first row in the common electrode driving circuits 150L and 150R. Since the terminal P of the unit control circuit 152 becomes H level, the transmission gate 52 is turned on. In this frame period, when the polarity designation signal Pol becomes H level in the horizontal effective scanning period in which the scanning signal Y0 becomes H level, the common signal Com becomes the higher voltage VcH in the horizontal effective scanning period. Since it is inverted in the latch circuit 60 in the first row, the common electrode 1 in the first row
The voltage Com1 of 08 becomes a voltage VcL obtained by inverting the voltage VcH of the common signal Com supplied to the feeder line 153.

Subsequently, the scanning signal Y0 becomes L level. Since the terminal P of the unit control circuit 152 in the first row becomes L level when the scanning signal Y0 becomes L level, the transmission gate 5
2 is once turned off, but the common electrode 108 in the first row is held at the immediately preceding voltage VcL by the latch circuit 60. Further, after the scanning signal Y0 becomes L level, the polarity designation signal Po
Since l is inverted to L level, the common signal Com switches to the voltage VcL.

Next, the scanning signal Y1 becomes H level. When the scanning signal Y1 becomes H level, 1 row, 1 column to 1
Since the TFTs 116 in the pixels in the row 240 column are turned on, these pixel electrodes 118 include
Data signals X1, X2, X3,..., X240 are applied. Since the polarity designation signal Pol is at the L level and the positive polarity writing is designated, the voltage of the common electrode 108 in the first row is applied to the pixel capacitor 120 and the auxiliary capacitor 130 in the first row and first column to the first row and 240 columns. A data signal having a voltage that becomes higher as a dark gradation value is specified is written to VcL.
On the other hand, when the scanning signal Y1 becomes H level, the terminal P of the unit control circuit 152 in the second row becomes H level and the transmission gate 52 is turned on, so that the voltage Com2 of the common electrode 108 in the second row is turned on. Becomes a voltage VcH obtained by inverting the voltage VcL of the common signal Com supplied to the feeder line 153.

Thereafter, the scanning signal Y1 becomes L level. When the scanning signal Y1 becomes L level, 1 row 1 column-
After the TFT 116 in the pixel in the first row and the 240th column is turned off, the written voltage is held by the parallel capacitor of the pixel capacitor 120 and the auxiliary capacitor 130, and has a transmittance corresponding to the held voltage.
Further, when the scanning signal Y1 becomes L level, the terminal P of the unit control circuit 152 in the second row.
However, the common electrode 108 in the second row is held at the immediately preceding voltage VcH by the latch circuit 60. Further, since the polarity designation signal Pol is inverted to H level after the scanning signal Y0 becomes L level, the common signal Com is switched to the voltage VcH.

Subsequently, the scanning signal Y2 becomes H level. When the scanning signal Y2 becomes H level, 2 rows and 1 column to
Since the TFTs 116 in the pixels of 2 rows and 240 columns are turned on, data signals X 1, X 2, X 3,..., X 240 are applied to these pixel electrodes 118. Since the polarity designation signal Pol is H level and negative polarity writing is designated, the voltage of the common electrode 108 in the second row is applied to the pixel capacitor 120 and the auxiliary capacitor 130 in the second row and first column to the second row and 240th column. With respect to VcH, a data signal having a voltage that becomes lower as a dark gradation value is designated is written.
On the other hand, when the scanning signal Y2 becomes H level, the terminal P of the unit control circuit 152 in the first row becomes H level again. However, in this embodiment, the line inversion method is used. Therefore, the common signal Com (polarity designation signal Pol) when the scanning signal Y2 becomes H level is the same level as when the scanning signal Y0 becomes H level, and the transmission gate 52 is turned on. However, the voltage Com1 of the common electrode 108 in the first row maintains the voltage VcL, and the voltage is not switched.
Further, when the scanning signal Y2 becomes H level, the terminal P of the unit control circuit 152 in the third row becomes H level, so the voltage Com3 of the common electrode 108 in the third row is the voltage VcH of the common signal Com.
The voltage VcL is obtained by inverting.

Thereafter, the scanning signal Y2 becomes L level. When the scanning signal Y2 becomes L level, 2 rows and 1 column to
After the TFT 116 in the pixel of 2 rows and 240 columns is turned off, the written voltage is held by the parallel capacitor of the pixel capacitor 120 and the auxiliary capacitor 130, and the transmittance according to the held voltage is obtained.
Further, when the scanning signal Y2 becomes L level, the terminal P of the unit control circuit 152 in the first row.
Becomes the L level again and the transmission gate 52 is turned off, but the common electrode 108 in the first row is held at the voltage VcL by the latch circuit 60. On the other hand, when the scanning signal Y2 becomes L level, the terminal P of the unit control circuit 152 in the third row also becomes L level, but the common electrode 108 in the third row is brought to the previous voltage VcL by the latch circuit 60. Retained.
Further, since the polarity designation signal Pol is inverted to L level after the scanning signal Y2 becomes L level, the common signal Com is switched to the voltage VcL.

Subsequently, the scanning signal Y3 becomes H level. When the scanning signal Y3 becomes H level, 3 rows 1 column-
The TFT 116 in the pixel of 3 rows and 240 columns is turned on, and the pixel capacitor 120 and the auxiliary capacitor 1
A data signal having a positive voltage corresponding to the gradation is written in 30. Also, the scanning signal Y3 is H
When the level is reached, the terminal P of the unit control circuit 152 in the second row again becomes the H level, but the voltage Com1 of the common electrode 108 in the second row maintains the voltage VcH, and the voltage is not switched.
When the scanning signal Y3 becomes H level, the terminal P of the unit control circuit 152 in the fourth row also becomes H level, so that the voltage Com4 of the common electrode 108 in the fourth row is equal to the voltage VcL of the common signal Com.
The voltage VcH is obtained by inverting the above.
Thereafter, the scanning signal Y3 becomes L level, and T in pixels in the 3rd row and the 1st column to the 3rd row and 240th column
After the FT 116 is turned off, the written voltage is applied to the pixel capacitor 120 and the auxiliary capacitor 130 thereafter.
Is held by the parallel capacitor, and has a transmittance according to the holding voltage.
At the time when the scanning signal Y3 becomes L level, the terminal P of the unit control circuit 152 in the second row.
Becomes the L level again, but the common electrode 108 in the second row is
held at cH. On the other hand, when the scanning signal Y3 becomes L level, the terminal P of the unit control circuit 152 in the fourth row also becomes L level, but the common electrode 108 in the fourth row is brought to the previous voltage VcH by the latch circuit 60. Retained.
Since the polarity designation signal Pol is inverted to H level after the scanning signal Y3 becomes L level,
The common signal Com is switched to the voltage VcH.

In this frame period, the same operation is repeatedly performed until the scanning signal Y321 becomes H level and becomes L level. As a result, in the odd row pixels,
The positive polarity voltage corresponding to the gradation is held, and in the even-numbered pixels, the negative polarity voltage corresponding to the gradation is held, and each has a transmittance corresponding to the gradation.
In the next frame period, the writing polarity is reversed in each row, and the negative polarity writing is designated for the pixels in the odd-numbered rows and the negative polarity writing is designated for the pixels in the even-numbered odd rows. It becomes operation.

FIG. 5 shows the waveforms of the scanning signal Yi in the i-th row and the voltage Comi of the i-th common electrode.
It is a figure which shows how the voltage Pix (i, j) of the pixel electrode 118 of i row j column changes.
As shown in this figure, the voltage Pix (i, j) of the pixel electrode 118 is the voltage VcL at the common electrode 108 if the positive polarity writing is designated when the scanning signal Yi becomes the H level. As a reference, the specified gradation value becomes a higher voltage (denoted by ↑ in the figure) as the specified gradation value becomes darker. If negative polarity writing is specified, the specified gradation value with reference to the voltage VcH It is shown that the voltage becomes lower (indicated by ↓ in the figure) as becomes darker.
Note that in the i-th row, the scanning signal Y (i−1) on the first row becomes the H level, whereby the voltage Comi of the common electrode is switched. However, in the i-th row, since the TFT 116 is off, the voltage of the pixel electrode 118 changes while the held voltage is maintained.

In this embodiment, the common electrode 108 of each row is made to swing with the voltages VcL and VcH, and the voltage of the data signal written to the pixel electrode is set to the high-order side when the low-order side voltage VcL is used. Since it is on the lower side when VcH is set, the voltage amplitude of the data signal becomes narrower than in the configuration in which the voltage of the common electrode is constant. For this reason, according to the present embodiment, not only the withstand voltage of the elements constituting the data line driving circuit 190 is reduced, but also the voltage amplitude in the data line 114 is narrowed. Is no longer consumed.

By the way, each common electrode 108 is either the voltage VcL or VcH. For this reason, first, a voltage selection signal is generated according to the progress of selection of the scanning line 112. Specifically, for example, when the scanning line of the previous row (or the own row) is selected, the logic of the polarity designation signal is selected. A first configuration has been conceived in which a voltage selection signal is generated by latching a level and one of the voltages is selected according to the logic level of the voltage selection signal.
However, since the common electrode has a large CR time constant due to the parasitic resistance of various capacitance components as well as the wiring resistance and the on-resistance of the transistor, in the configuration in which the selected voltage is applied only on one of the left and right sides, There is a possibility that a delay occurs on the other side of the common electrode and the target voltage does not change rapidly.
Then, next, a voltage selection signal is generated on each of the left and right sides of the common electrode according to the progress of selection of the scanning line 112, and the voltage is selected according to the logic level of the voltage selection signal. The configuration was considered.
However, this second configuration has the following problems. That is, the logic level of the voltage selection signal is indeterminate in a state where the scanning line has not yet been selected, such as immediately after the power is turned on. At this time, there is no problem if the logic levels of the voltage selection signals match on both the left and right sides of the common electrode. However, if they do not match, for example, as shown in FIG. In the case of the L level on the right side, the voltage VcH is selected on one side of the common electrode 108 and the voltage VcL is selected on the other side, resulting in a short-circuit state, so that a large current flows through the common electrode. This short-circuit state is resolved if at least one cycle of the scanning signals Y1 to Y320 reaches the H level, but if the capacity of the power supply circuit that supplies the voltages VcL and VcH is not sufficient, the system goes down before completing the cycle. It will end up.

On the other hand, in the present embodiment, since the voltage is not selected according to the logic level of the voltage selection signal corresponding to the progress state in which the scanning line 112 is selected, the terminal is selected even immediately after the power is turned on. The logic level of P is not inconsistent between the left side and the right side.
Even if there is a mismatch, as shown in FIG. 6A, only the transmission gate 52 whose terminal P is at the H level is turned on, and the transmission gate 52 whose terminal P is at the L level is off. Since it becomes a state, it does not become a short circuit state.
In the configuration in which such a latch circuit 60 is provided, the unit control circuit 15 immediately after the power is turned on or the like.
When the logic level of the terminal P in FIG. 2 is different between the left side and the right side, the transmission gate 52 having the L level is turned off, so that the common electrode 108 causes the transmission gate 52 having the H level to be connected. The inversion voltage of the common signal Com supplied through the terminal is determined.
Further, when the terminal P is at the L level on both the left side and the right side immediately after the power is turned on, the transmission gate 52 is turned off on both sides, so that the potential of the common electrode 108 becomes uncertain for a moment. The left and right latch circuits 60 immediately determine the voltage VcL if the potential is lower than the threshold value, and immediately determine the voltage VcH if the potential exceeds the threshold value.

Thus, according to the present embodiment, it is possible to avoid a system down immediately after power-on.

In the first embodiment, the unit control circuit 15 of the common electrode drive circuits 150L and 150R.
2 is common in each row, and the voltage level of the common signal Com is made to correspond to the logic level of the polarity designation signal Pol, but it may be configured as follows.
That is, as shown in FIG. 7, for the unit control circuits 152 in the even-numbered rows, the inverter 54 is inserted between the signal line 153 for supplying the common signal Com and the input terminal of the transmission gate 52. As shown in FIG. 8, the common signal Com is fixed to the voltage VcH over the frame period in which the positive polarity writing is designated for the odd-numbered row and the negative polarity writing is designated for the even-numbered row. It is good also as a structure switched to voltage VcL in a period.
Here, as with the inverters 62 and 64 in the latch circuit 60, the inverter 54 uses the voltages VcL and VcH as power sources, and the threshold voltage is also set between the voltages VcL and VcH.
For the inverter 54, if the voltages VcL and VcH of the common signal Com are switched,
The insertion may be performed not in even-numbered rows but in odd-numbered rows.

<Second Embodiment>
Next, an electro-optical device according to a second embodiment will be described. FIG. 9 is a block diagram illustrating a configuration of the electro-optical device according to the second embodiment.
In the first embodiment shown in FIG. 1, the write polarity is inverted one row at a time (1H inversion). However, in the second embodiment, the write polarity is inverted every two rows (2H inversion). It is a thing. For this reason, the second embodiment is different from the first embodiment in that the common signal is the first common signal C.
oma and the second common signal Comb (first difference) and the common electrode drive circuit 15
The difference is that the connection relationship of the unit control circuits 152 in 0L and 150R is different between the odd and even rows (second difference).
Since other points are common to the first embodiment, the description will focus on the first and second differences.

First, as described above, in the second embodiment, since the write polarity is inverted every two rows, the polarity designation signal Pol is 1, 2, 3, 4, 5 as shown in FIG.・ 6, 7 ・ 8
,..., 317, 318, 319, and 320, the same logical level is obtained in the horizontal effective scanning period, and the logical level is inverted every the same period as the two horizontal scanning periods. In addition,
Similar to the first embodiment, the logic level of the polarity specifying signal Pol is switched at a timing preceding the timing at which the logic level of the clock signal Cly is switched.
Here, in order to describe the writing polarity in the second embodiment, an integer p of 1 to 80 is used. When the integer p is used, the same polarity writing is designated for the odd (4p-3) and even (4p-2) rows. The next two rows, odd (4p-1) and even (4p) rows, have opposite writing polarities to the (4p-3) and (4p-2) rows. Is specified.

Next, the first difference will be described.
As shown in FIG. 11, the first common signal Coma and the second common signal Comb
This is a signal that makes cL and VcH mutually exclusive and is switched every frame period.
More specifically, positive writing is designated for odd (4p-3) and even (4p-2) rows, and for odd (4p-1) and even (4p) rows. In the frame period in which negative polarity writing is designated, the first common signal Coma becomes the voltage VcH, and the second common signal Comb
Is at the voltage VcL, while negative writing is designated for the odd (4p-3) and even (4p-2) rows, and the odd (4p-1) and even (4p) rows On the other hand, in the frame period in which the positive polarity writing is designated, the first common signal Coma becomes the voltage VcL, and the second common signal Co
mb becomes the voltage VcH.

Next, the second difference will be described.
FIG. 10 shows the unit control circuit 152 in the odd (4p-3) th and even (4p-2) th rows and the odd (4p-1) th and even (4p) in the common electrode driving circuit 150L (150R). It is a figure which shows a structure with the unit control circuit 152 of the line.
As shown in this figure, the input terminal of the transmission gate 52 in the unit control circuit 152 in the odd (4p-3) and even (4p-2) rows is the first common signal C.
The second common signal Comb is supplied to the input terminal of the transmission gate 52 in the unit control circuit 152 in the odd (4p-1) th and even (4p) th rows connected to the signal line 155 supplied with oma. Connected to the signal line 156.

10 is the same as that of the second embodiment in that the transmission gate 52 shown in FIG. 10 is turned on when the logic level of the terminal P is H level and turned off when the terminal P is L level.
For this reason, the terminal P in the unit control circuit 152 in the odd (4p-3) th row is (
Only in the horizontal effective scanning period in which the (4p-4) th row and the (4p-2) th row below the first row are selected, the H level is set, and the transmission gate 52 is turned on. Therefore, the odd-numbered (4p-3) -th common electrode has a voltage obtained by taking in the voltage of the first common signal Coma during the period when the transmission gate 52 is in the ON state and inverting it.

For the common electrode 108 in the even (4p-2) th row, the transmission gate 5
The voltage of the first common signal Coma during the period in which 2 is in the on state is taken in by the latch circuit 60 and inverted.
On the other hand, the terminal P in the unit control circuit 152 in the odd (4p-1) th row is (4p on the first row).
-2) It becomes H level only in the horizontal effective scanning period in which the row and the (4p) row below the row are selected, and the transmission gate 52 is turned on. However, odd numbers (4p-
1) Since the input terminal of the transmission gate 52 is connected to the signal line 156 to which the second common signal Comb is supplied in the first row, the common electrode 10 in the odd (4p-1) th row.
8 is the second common signal C during the period when the transmission gate 52 is in the ON state.
The voltage of omb is taken in by the latch circuit 60 and inverted.
The common electrode 108 in the even (4p) -th row also has a voltage obtained by taking in the voltage of the second common signal Comb during the period when the transmission gate 52 is turned on and inverting it.

Therefore, the common electrode 10 in the 320th row from the voltage Com1 of the common electrode 108 in the first row.
The voltage up to voltage Com320 of 8 is as shown in FIG. 11. If the positive writing is designated in the horizontal effective scanning period in which the scanning line is selected, the scanning line on one row is selected in advance. If the voltage VcH is sometimes switched to the voltage VcL and negative polarity writing is designated, the voltage VcL is switched to the voltage VcH when a scanning line on one row is selected in advance.
In the second embodiment, such a switching operation is executed alternately every two rows.
The write operation in each row is the same as in the first embodiment.

In the second embodiment, in order to perform so-called 2H inversion driving, the first common signal Coma and the second common signal Comb have waveforms as shown in FIG. 11, but the common signal Com shown in FIG. As described above, when the common signal is switched every 1H period, 1H is the same as that of the first embodiment.
Inversion driving can be performed. That is, in the second embodiment, 1H inversion and 2H inversion can be switched depending on the waveforms of the first common signal Coma and the second common signal Comb.

An important point in the drive method for amplitude of the common electrode in binary is that, in the i-th common electrode 108, when the scanning signal Yi becomes H level, positive writing is designated. This means that the voltage VcL is on the lower side, and the voltage VcH is higher if the negative polarity writing is specified.
For this reason, in the first and second embodiments, the terminal P in the unit control circuit 152 in the i-th row may be directly connected to the scanning line 112 in the i-th row to supply the scanning signal Yi. However, in this configuration, the write polarity designated by the polarity designation signal Pol has a relationship in which the logic level is inverted.

In the first and second embodiments, the scanning line 112 is set to (0), 1, 2, 3,.
318, 319, 320, (321) The case of selecting (scanning) from the top to the bottom in the order of the row is shown, but conversely, (312), 320, 319, 318, ..., 3, 2, 1, (0
) It may be configured to scan from the bottom to the top in the order of the line.
In other words, in the first and second embodiments, the terminal P is set when the upper scanning line or the lower scanning line is selected so that both the downward scanning and the upward scanning can be dealt with. Since the NOR circuit 51 and the inverter 53 are applied so as to be at the H level, and the circuit corresponds only to one of the scanning directions, the terminal P is connected to the scanning line selected before the own row. Is enough.

Since various capacitances are parasitic on the common electrode 108 in each row, the voltage immediately before the transmission gate 52 is turned off can be held without the latch circuit 60.
However, since the common electrode 108 in which the transmission gate 52 is turned off is not electrically connected to any signal line 153 (155, 156) (high impedance state), noise or the like is superimposed. In some cases, the display quality may be affected by fluctuations from the voltages VcL and VcH. For this reason, it is preferable to provide the latch circuit 60.

Furthermore, although the pixel capacitor 120 is in the normally white mode, it may be in a normally black mode in which the pixel capacitor 120 becomes dark when no voltage is applied. R (red), G (green),
Color display may be performed by forming one dot with three B (blue) pixels, and adding another color, and forming one dot with these four or more pixels. It is good also as a structure which improves property.

The constituent elements of the common electrode driving circuits 150L and 150R may not be the same TFT as the pixel switching element in the display region 100, but may be configured so that separate IC chips are mounted on both the left and right sides. Further, the present embodiment may be a reflective type instead of a transmissive type, or may be a semi-transmissive / semi-reflective type that combines a transmissive type and a reflective type.

<Electronic equipment>
Next, an electronic apparatus having the electro-optical device 10 according to the above-described embodiment as a display device will be described. FIG. 12 is a diagram illustrating a configuration of a mobile phone 1200 using the electro-optical device 10 according to the embodiment.
As shown in this figure, a cellular phone 1200 includes the electro-optical device 10 described above together with a plurality of operation buttons 1202, an earpiece 1204 and a mouthpiece 1206. Note that the components of the electro-optical device 10 corresponding to the display region 100 do not appear as appearance.

As an electronic apparatus to which the electro-optical device 10 is applied, in addition to the mobile phone shown in FIG. 12, a digital still camera, a notebook computer, a liquid crystal television, a viewfinder type (
Or a monitor direct view type video recorder, a car navigation device, a pager, an electronic notebook, a calculator, a word processor, a workstation, a videophone, a POS terminal, a device equipped with a touch panel, and the like. And as a display device for these various electronic devices,
Needless to say, the above-described electro-optical device 10 is applicable.

1 is a diagram illustrating a configuration of an electro-optical device according to a first embodiment. It is a figure which shows the structure of the pixel in the same electro-optical apparatus. It is a figure which shows the structure of the unit control circuit in the same electro-optical apparatus. FIG. 6 is a diagram for explaining an operation of the electro-optical device. It is a figure for demonstrating writing operation | movement of the same electro-optical apparatus. It is a figure which shows the case where the operation | movement of the same unit control circuit differs in both sides. It is a figure which shows the deformation | transformation structure in the same electro-optical apparatus. It is a figure for demonstrating operation | movement of the deformation | transformation structure. It is a figure which shows the structure of the electro-optical apparatus which concerns on 2nd Embodiment. It is a figure which shows the structure of the unit control circuit in the same electro-optical apparatus. FIG. 6 is a diagram for explaining an operation of the electro-optical device. It is a figure which shows the mobile telephone using the electro-optical apparatus which concerns on embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Electro-optical apparatus, 20 ... Display control circuit, 51 ... NOR circuit, 52 ... Transmission gate, 60 ... Latch circuit, 100 ... Display area, 108 ... Common electrode, 110 ... Pixel, 112 ... Scan line, 114 ... Data 116, TFT, 120, pixel capacity, 130, auxiliary capacity, 140, scanning line drive circuit, 150R, 150L, common electrode drive circuit, 152
Unit control circuit, 1200 ... mobile phone

Claims (5)

A plurality of scan lines;
Multiple data lines,
A common electrode provided corresponding to the plurality of scanning lines;
Respectively provided corresponding to the intersection of the plurality of scanning lines and the plurality of data lines,
Each is
A pixel switching element having one end connected to the data line and in a conductive state between the one end and the other end when the scanning line is selected;
A pixel capacitor having one end connected to the other end of the pixel switching element and the other end connected to a common electrode;
A pixel containing
A drive circuit for an electro-optical device having:
A scanning line driving circuit for selecting the scanning lines in a predetermined order;
A common signal in which a binary voltage is switched at a predetermined period is supplied to a common electrode corresponding to the one scanning line in a period in which the one scanning line is selected, and a pixel corresponding to the one scanning line is supplied to
When the positive polarity is specified such that the pixel electrode is on the higher side than the potential of the common electrode, the pixel corresponding to the one scanning line is applied while applying the lower side voltage among the binary voltages. In addition, when a negative polarity is specified such that the pixel electrode is on the lower side than the potential of the common electrode, a common electrode driving circuit that applies a higher voltage among the binary voltages; and
A data line driving circuit for supplying a data signal of a voltage corresponding to the gradation and polarity of the pixel to the pixel corresponding to the one scanning line via the data line;
Comprising
The common electrode drive circuit is
A unit control circuit provided corresponding to each of the common electrodes on each of one end side and the other end side of the common electrode,
The unit control circuit corresponding to one common electrode is
An input terminal is connected to the signal line to which the common signal is supplied, and becomes conductive when a scanning line corresponding to the one common electrode or a scanning line separated by a predetermined row from the scanning line is selected. A switch,
A latch circuit that latches the common signal and applies it to the one common electrode when the switch is turned on;
A drive circuit for an electro-optical device, comprising: 2. The drive circuit for an electro-optical device according to claim 1, wherein the common signal is a cycle in which scanning lines are selected one by one, and the voltage is switched at a timing when none of the scanning lines is selected. The common signal includes a first common signal and a second common signal,
The input terminal of the switch in the unit control circuit is alternately connected to the signal line supplying the first common signal and the signal line supplying the second common signal for every two scanning lines. The drive circuit of the electro-optical device according to claim 1. A plurality of scan lines;
Multiple data lines,
A common electrode provided corresponding to the plurality of scanning lines;
Respectively provided corresponding to the intersection of the plurality of scanning lines and the plurality of data lines,
Each is
A pixel switching element having one end connected to the data line and in a conductive state between the one end and the other end when the scanning line is selected;
A pixel capacitor having one end connected to the other end of the pixel switching element and the other end connected to a common electrode;
A pixel containing
A scanning line driving circuit for selecting the scanning lines in a predetermined order;
A common signal in which a binary voltage is switched at a predetermined period is supplied to a common electrode corresponding to the one scanning line in a period in which the one scanning line is selected, and a pixel corresponding to the one scanning line is supplied to
When the positive polarity is specified such that the pixel electrode is on the higher side than the potential of the common electrode, the pixel corresponding to the one scanning line is applied while applying the lower side voltage among the binary voltages. In addition, when a negative polarity is specified such that the pixel electrode is on the lower side than the potential of the common electrode, a common electrode driving circuit that applies a higher voltage among the binary voltages; and
A data line driving circuit for supplying a data signal of a voltage corresponding to the gradation and polarity of the pixel to the pixel corresponding to the one scanning line via the data line;
Comprising
The common electrode drive circuit is
A unit control circuit provided corresponding to each of the common electrodes on each of one end side and the other end side of the common electrode,
The unit control circuit corresponding to one common electrode is
An input terminal is connected to the signal line to which the common signal is supplied, and becomes conductive during a period in which a scanning line corresponding to the one common electrode or a scanning line separated by a predetermined row from the scanning line is selected. A switch,
A latch circuit that latches the common signal and applies it to the one common electrode when the switch is turned on;
An electro-optical device comprising:   An electronic apparatus having the electro-optical device according to claim 4.

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