JP2009086171A - Electro-optical device, method of driving electro-optical device, and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the degradation of display quality due to operations of a simplified circuit configuration when employing a driving system which individually controls potentials of respective holding capacitor lines. <P>SOLUTION: In a normal display mode of sequentially selecting scan lines by sequential supply of a scan signal, a potential of a holding capacitor line corresponding to a scan line in a row preceding a selected scan line is shifted from a first potential on the high voltage side to a second potential on the low voltage side synchronously with the scan signal of the selected scan line when a pixel potential connected to the scan line in the preceding row is negative, and the potential of the holding capacitor line corresponding to the scan line in the preceding row is shifted from the second potential on the low voltage side to the first potential on the high voltage side synchronously with the scan signal of the selected scan line when the pixel potential connected to the scan line in the preceding row is positive. In a partial display mode of partially selecting scan lines by partial supply of the scan signal, potentials of all holding capacitor lines are kept at the first potential. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

 The present invention relates to an electro-optical device, a driving method of the electro-optical device, and an electronic apparatus.

  Conventionally, a general active matrix type liquid crystal display device supports a plurality of data lines and scanning lines, a storage capacitor line provided corresponding to each of the scanning lines, and an intersection of the data line and the scanning line. A liquid crystal capacitor having a liquid crystal sandwiched between a pixel electrode and a counter electrode, a storage capacitor having one end connected to the storage capacitor line and the other end connected to the pixel electrode, via a scanning line And a pixel having a switching element (TFT: Thin Film Transistor) for switching connection / disconnection between the data line and the pixel electrode in accordance with the supplied scanning signal.

  As one of the driving methods of the liquid crystal display device having such a configuration, a common voltage is supplied to the counter electrode and all the storage capacitor lines, and the common voltage is swung in a scanning cycle (one frame period / total number of scanning lines). (Transition of the potential between a low potential and a high potential) and a data signal that is similarly swung in the scanning cycle is supplied to the data line, whereby the pixel potential (the potential of the counter electrode is changed for each scanning line). A line inversion driving method is known in which the polarity of the reference pixel electrode potential) is inverted. As described above, when the common voltage is swung, the gradation display is realized by fixing the swing amount of the common voltage and controlling the swing amount of the data signal according to the gradation data.

On the other hand, in recent years, as described in Patent Document 1 below, a common voltage, which is a DC voltage, is supplied to the counter electrode, and the potential of each storage capacitor line is individually swung to increase the voltage amplitude of the data signal. Attention has been focused on a capacitive line individual drive method that can reduce power consumption by reducing the power consumption.
JP 2002-196358 A

  By the way, in the past, when the above-described individual capacitive line driving method is adopted in a liquid crystal display device using an LTPS (Low Temperature Poly Silicon) transistor as a pixel switching element, holding for individually swinging the potential of each holding capacitive line The capacitor line driving circuit is formed on the circuit board by LTPS-CMOS transistors. However, when the storage capacitor line driving circuit is configured by LTPS-CMOS transistors, there is a problem that the circuit configuration becomes complicated, resulting in an increase in power consumption and a wide frame area.

  Therefore, a liquid crystal display device using an a-Si (amorphous silicon) transistor as a pixel switching element employs a capacitor line individual drive system, and the storage capacitor line drive circuit is configured by an a-Si transistor, thereby simplifying the circuit configuration. For example, in the display mode in which only a few lines of scanning lines are selected and the voltage holding period of the pixel is long as in the partial display mode, the operation of the simplified circuit configuration is performed. As a result, there has been a problem that the charge stored in the storage capacitor leaks through the storage capacitor line driving circuit, and the display quality deteriorates.

  The present invention has been made in view of such circumstances, and a case in which a driving system that individually controls the potential of each storage capacitor line is employed in an electro-optical device that uses an a-Si transistor as a switching element of a pixel. An object of the present invention is to prevent display quality deterioration caused by the operation of the simplified circuit configuration.

 In order to achieve the above object, an electro-optical device according to the present invention includes a plurality of data lines and scanning lines, a storage capacitor line provided corresponding to each of the scanning lines, the data lines, and the scanning lines. A pixel capacitor having an electro-optic material sandwiched between the pixel electrode and the counter electrode, one end connected to the storage capacitor line and the other end connected to the pixel electrode An electro-optical device comprising: a storage capacitor, a pixel having a switching element that switches connection / disconnection between the data line and the pixel electrode in accordance with a scanning signal supplied via the scanning line, A first power supply line maintained at a first potential on the high voltage side to be applied to the storage capacitor line, and a second power supply line maintained at a second potential on the low voltage side to be applied to the storage capacitor line And the pole whose logic level is inverted every frame A polarity signal line for supplying a signal, an inverted polarity signal line for supplying an inverted polarity signal that is a logically inverted signal of the polarity signal, a gate control signal line for supplying a gate control signal, and a transistor A third power supply line maintained at a gate-on potential and the storage capacitor line are provided correspondingly, a source electrode is connected to the first power supply line, and a drain electrode is connected to the storage capacitor line of this row. The source electrode is connected to one of the polarity signal line or the inverted polarity signal line if the first storage capacitor and the storage capacitor line of the current row are odd rows, and the source electrode is connected to the polarity signal line if it is an even row. Alternatively, the second transistor is connected to the other of the inverted polarity signal lines, the drain electrode is connected to the gate electrode of the first transistor, and the gate electrode is connected to the scanning line of the next row. And a third transistor in which the source electrode is connected to the second power supply line, the drain electrode is connected to the storage capacitor line of the bank, and the source electrode is the polarity signal if the storage capacitor line of the bank is an odd row. Line or one of the inverted polarity signal lines, and if it is an even row, the source electrode is connected to the other of the polarity signal line or the inverted polarity signal line, and the drain electrode is connected to the gate electrode of the third transistor. A fourth electrode having a gate electrode connected to the scanning line of the previous row and a source electrode connected to the other of the polarity signal line or the inverted polarity signal line if the storage capacitor line of the row is an odd row; If the row is an even row, the source electrode is connected to one of the polarity signal line or the inverted polarity signal line, the drain electrode is connected to the gate electrode of the third transistor, and the gate electrode is connected to the next row. The fifth transistor connected to the scanning line and the source electrode is connected to the other of the polarity signal line or the inverted polarity signal line if the storage capacitor line of the row is an odd row, and the source electrode if the row is an even row. Is connected to one of the polarity signal line or the inverted polarity signal line, a drain electrode is connected to a gate electrode of the first transistor, and a gate transistor is connected to the previous scanning line; A storage capacitor having a seventh electrode having a source electrode connected to the third power supply line, a drain electrode connected to the gate electrode of the first transistor, and a gate electrode connected to the gate control signal line; And a drive circuit.

 In the electro-optical device having such a feature, in the normal display mode in which each scanning line is sequentially selected by sequentially supplying scanning signals, the selected scanning is synchronized with the scanning signal of the selected scanning line. If the pixel potential connected to the scanning line in the previous row is negative, the potential of the storage capacitor line corresponding to the scanning line in the previous row is changed from the first potential on the high voltage side to the second potential on the low voltage side. If the pixel potential connected to the previous scanning line is positive, the potential of the storage capacitor line corresponding to the previous scanning line is transitioned from the second potential to the first potential. Here, when the potential of the storage capacitor line is changed from the first potential to the second potential, the first transistor is turned off, the third transistor is turned on, and the potential of the storage capacitor line is changed to the second potential. In the case of transition from the potential to the first potential, the first transistor is turned on and the third transistor is turned off.

  In such a normal display mode, each scanning line is sequentially selected at about 60 Hz, that is, every 1/60 seconds. Therefore, the gate potential of the first transistor is the next due to the parasitic capacitance of its own gate electrode. It is kept at the high level until the frame and the on state is continued. However, in the partial display mode in which the scanning lines are partially selected by partially supplying the scanning signal, the selection frequency of the non-selected row is about once every ½ second, that is, the voltage holding period of the pixel becomes long. Therefore, in the operation of the simplified circuit configuration used in the invention, the high-level potential cannot be held due to the charge leakage of the parasitic capacitance of the gate electrode (becomes off state), and the storage capacitor line is in the high impedance state. End up. At this time, if the potential of the data line changes, for example, a display defect such as flickering occurs. Further, when the voltage holding period becomes longer as described above, the potential of the holding capacitor line is changed due to the leakage current, and image sticking or the like occurs. Such a problem can be avoided by applying a large capacitance to the gate electrode of the first transistor. However, the occupied area of the storage capacitor line driving circuit becomes large and the frame area becomes wide. is there.

  Therefore, in the partial display mode, by supplying a gate control signal having an ON potential to the gate control signal line, the fifth transistor is turned on in all the storage capacitor line driver circuits, and the third power supply line and The gate electrode of the first transistor is connected, and the first transistor is also turned on. That is, all the storage capacitor lines are connected to the first power supply line and are maintained at the first potential on the high voltage side. Thereby, in the partial display mode, the potential change of the storage capacitor line can be suppressed, and the occurrence of burn-in can be prevented. Further, flickering can be prevented by controlling the amplitude of the data signal to change during this period.

In the electro-optical device according to the present invention, the odd-numbered capacitance line potential detection line for detecting the potential of the odd-numbered storage capacitance line and the even-numbered capacitance line for detecting the potential of the even-numbered storage capacitance line. The odd-numbered rows for correcting the voltage waveforms of the first power supply line and the second power supply line corresponding to the odd-numbered storage capacitor lines so as to cancel the voltage waveform distortion of the potential detection lines and the odd-numbered capacity line potential detection lines. An even number for correcting the voltage waveforms of the first power supply line and the second power supply line corresponding to the even-numbered storage capacitor lines so as to cancel the voltage waveform distortion of the voltage distortion correction circuit and the even-numbered capacity line potential detection lines. A row voltage distortion correction circuit, and each of the storage capacitor driving circuits has a source electrode connected to the storage capacitor line of the current row, and if the storage capacitor line of the current row is an odd number, the drain electrode is the odd-numbered capacity line. If it is connected to a potential detection line Is connected in-electrode and the even-numbered row capacitance line potential detection line, with the eighth transistor having a gate electrode connected with the Bank of scanning lines, it is preferable.
As a result, display unevenness and the like due to voltage waveform distortion of the storage capacitor line occurring in the voltage writing period of each pixel can be prevented, and higher display quality can be achieved.

Also, in the electro-optical device according to the present invention, the odd-numbered voltage distortion correction circuit has a first power supply corresponding to an odd-numbered storage capacitor line with the first potential as an input of a non-inverting input terminal. A first operational amplifier connected to one end of a line; and the second potential is input to a non-inverting input terminal, and an output terminal is connected to one end of a second power supply line corresponding to an odd-numbered storage capacitor line. In response to the second operational amplifier and the polarity signal or the inverted polarity signal, the odd row capacitance line potential detection line is connected to the inverting input terminal of the first operational amplifier, or the second operational amplifier A switching circuit that switches whether to connect to the inverting input terminal, wherein the even-numbered row voltage distortion correction circuit accepts the first potential as an input to the non-inverting input terminal, and an output terminal corresponds to a holding capacitor line in the even-numbered row Connected to one end of the first power line A first operational amplifier; a second operational amplifier having the second potential as an input to a non-inverting input terminal and an output terminal connected to one end of a second power supply line corresponding to an even-numbered storage capacitor line; Whether to connect the even-row capacitor line potential detection line to the inverting input terminal of the first operational amplifier or to the inverting input terminal of the second operational amplifier according to the polarity signal or the inverted polarity signal It is preferable to include a switch circuit that switches between the two.
This simplifies the circuit configuration of the odd-numbered row voltage distortion correction circuit and the even-numbered row voltage distortion correction circuit to prevent display unevenness caused by the voltage waveform distortion of the storage capacitor line that occurs in the voltage writing period of each pixel. Can contribute to cost reduction.

 On the other hand, the driving method of the electro-optical device according to the present invention includes a plurality of data lines and scanning lines, a storage capacitor line provided corresponding to each of the scanning lines, and an intersection of the data line and the scanning line. A pixel capacitor provided corresponding to the location and having an electro-optic material sandwiched between the pixel electrode and the counter electrode, one end connected to the storage capacitor line and the other end connected to the pixel electrode A driving method of an electro-optical device including a capacitor and a pixel having a switching element that switches connection / disconnection of the data line and the pixel electrode according to a scanning signal supplied via the scanning line, In the normal display mode in which each scanning line is sequentially selected by sequentially supplying scanning signals, the pixels connected to the scanning line in the previous row of the selected scanning line in synchronization with the scanning signal of the selected scanning line. If the potential is negative If the potential of the storage capacitor line corresponding to the scanning line in the previous row is changed from the first potential on the high voltage side to the second potential on the low voltage side, and the pixel potential connected to the scanning line in the previous row is positive In the partial display mode in which the potential of the storage capacitor line corresponding to the scanning line of the previous row is changed from the second potential to the first potential and the scanning signal is partially supplied to partially select the scanning line. The potentials of all the storage capacitor lines are maintained at the first potential.

  According to the driving method of the electro-optical device having such characteristics, in the partial display mode, since all the storage capacitor lines are maintained at the first potential on the high voltage side, the potential change of the storage capacitor lines is suppressed. And the occurrence of burn-in can be prevented. Further, flickering can be prevented by controlling the amplitude of the data signal to change during this period.

Furthermore, an electronic apparatus according to the present invention includes the above-described electro-optical device.
According to the electronic apparatus having such a feature, since an electro-optical device with high display quality can be used as the display unit, it is possible to improve the quality of the electronic apparatus itself.

  Hereinafter, an electro-optical device, an electro-optical device driving method, and an electronic apparatus according to an embodiment of the invention will be described with reference to the drawings.

Electro-optical device
(First embodiment)
First, a first embodiment of an electro-optical device according to the invention will be described. As an electro-optical device according to the present invention, a liquid crystal display device using liquid crystal as an electro-optical material will be described as an example. FIG. 1A is a plan view of the liquid crystal display device LD1 according to the present embodiment as viewed from the counter substrate side, and FIG. 1B is a cross-sectional view taken along line AA in FIG.

  As shown in FIGS. 1A and 1B, the liquid crystal display device LD1 according to the present embodiment includes a sealing material 12 in which a circuit board 10 and a counter substrate 11 forming a pair are photo-curing sealing materials. The liquid crystal 13 is sealed and held in a region that is bonded and partitioned by the sealing material 12. The sealing material 12 is formed in a frame shape closed in a region within the substrate surface.

  A window frame 14 made of a light shielding material is formed in a region inside the region where the sealing material 12 is formed on the counter substrate 11 side. An area surrounded by the window frame 14 is an image display area. In the area outside the sealing material 12 on the circuit board 10 side, the data line driving circuit 15 and the mounting terminal 16 are arranged along one side of the circuit board 10, and the scanning line is formed along two sides adjacent to the one side. A drive circuit 17 is arranged. The data line driving circuit 15 and the scanning line driving circuit 17 are driver ICs, and are electrically connected to data lines and scanning lines described later via an anisotropic conductive adhesive film. On the remaining one side of the circuit board 10, a plurality of wirings 18 are provided for connecting between the scanning line driving circuits 17 provided on both sides of the image display area. Further, at least one corner of the counter substrate 11 is provided with an inter-substrate conductive material 19 for establishing electrical continuity between the circuit board 10 and the counter substrate 11.

  Although details will be described later, on the circuit board 10, m scanning lines extending in the X direction in the drawing, n data lines extending in the Y direction, and scanning lines correspond to each. The pixel electrode (reference numeral 20 in the figure), one end of which is connected to the storage capacitor line and the other end of the pixel electrode 20 is provided corresponding to the intersection of the storage capacitor line and the data line and the scanning line. And a pixel circuit having a switching element (hereinafter referred to as a pixel TFT) that switches connection / disconnection between the data line and the pixel electrode 20 in accordance with a scanning signal supplied via the scanning line. Is formed. The pixel TFT is an N-channel a-Si (amorphous silicon) MOS transistor.

  At one end of each storage capacitor line, a storage capacitor line driving circuit configured by an a-Si transistor as in the pixel TFT and various signal lines for supplying various signals to the storage capacitor line driving circuit are formed. On the other hand, a counter electrode 21 for applying a common voltage Vcom is formed on the counter substrate 11, thereby holding the liquid crystal 13 between the pixel TFT, the storage capacitor, and the pixel electrode 20 and the counter electrode 21. Thus, the pixels having the liquid crystal capacitance are formed in a matrix of m rows × n columns.

    In the liquid crystal display device LD1, depending on the type of the liquid crystal 13 to be used, that is, depending on the operation mode such as TN (Twisted Nematic) mode, STN (Super Twisted Nematic) mode, or normally white mode / normally black mode. A retardation plate, a polarizing plate, and the like are arranged in a predetermined direction, but are not shown here. In the case where the liquid crystal display device LD1 is configured for color display, for example, red (R), green (G), blue (B) in the region of the counter substrate 11 that faces each pixel electrode 20 of the circuit substrate 10. The color filter is formed together with the protective film.

  FIG. 2 is a circuit configuration diagram of the liquid crystal display device LD1. As shown in FIG. 2, one end is connected to the scanning line driving circuit 17 and m scanning lines Y1 to Ym extending in the X direction, and one end is connected to the data line driving circuit 15 and extending in the Y direction. There are n existing data lines X1 to Xn and storage capacitor lines CS1 to CSm extending in the X direction and provided corresponding to the scanning lines Y1 to Ym, respectively. The pixel TFT 30, the liquid crystal capacitor CL, and a pixel having a storage capacitor CH in which one end is connected to the storage capacitor line and the other end is connected to the pixel electrode 20 are formed at the intersection of the scanning line and the scanning line. For example, the pixel corresponding to the intersection of the scanning line Y1 and the data line X1 is representatively described. One end of the storage capacitor CH is connected to the storage capacitor line CS1, and the gate electrode of the pixel TFT 30 is connected to the scan line Y1. The source electrode is connected to the data line X1, and the drain electrode is connected to the other end of the storage capacitor CH and the pixel electrode 20 constituting the liquid crystal capacitor CL.

  The scanning line driving circuit 17 sequentially outputs pulsed scanning signals G1, G2,..., Gm having an ON potential Vgon for turning on the pixel TFT 30 in order of the scanning lines Y1, Y2,. To do. The data line driving circuit 15 receives data signals (analog voltage signals) S1, S2,..., Sm corresponding to gradation data (data defining brightness for each pixel) supplied from a control circuit (not shown). Output to each data line X1, X2,..., Xm.

  At one end of each of the storage capacitor lines CS1 to CSm, storage capacitor line drive circuits CD1 to CDm for individually controlling the potentials of these storage capacitor lines are formed. The storage capacitor line drive circuits CD1 to CDm are the first power supply line 40 maintained at the high voltage side potential Vc2 (first potential) and the first power line 40 maintained at the low voltage side potential Vc1 (second potential). 2 power lines 41, a polarity signal line 42 for supplying a polarity signal POL whose logic level is inverted every frame, and an inversion polarity for supplying an inverted polarity signal XPOL which is a logic inversion signal of the polarity signal POL. The signal line 43, the gate control signal line 44 for supplying the gate control signal Cntg, and the third power supply line 45 maintained at the ON potential Vgon of the transistor are connected. Note that the high level potentials of the polarity signal POL and the inverted polarity signal XPOL are set to be equal to the ON potential Vgon of the transistor.

  Hereinafter, detailed circuit configurations of the storage capacitor line drive circuits CD1 to CDm will be described with reference to FIG. In FIG. 3, for convenience of explanation, the storage capacitor line CSi−1 corresponding to the i-th scanning line Yi that is an arbitrary odd-numbered row and the scanning lines Yi−1 and Yi + 1 that are the even-numbered rows before and after that. The storage capacitor line drive circuits CDi−1, CDi, CDi + 1 provided at one end of CSi, CSi + 1 are representatively illustrated, and regarding the data lines, an arbitrary jth column data line Xj and j + 1 column Only the eye data line Xj + 1 is shown.

  As shown in FIG. 3, the storage capacitor line drive circuits CDi−1, CDi, and CDi + 1 are each an N-channel a-Si (amorphous silicon) MOS transistor, a first transistor T1, and a second transistor, like the pixel TFT 30. Transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, and seventh transistor T7. However, the connection relationship between the first transistor T1 to the seventh transistor T7 is different between the odd-numbered storage capacitor line driving circuit CDi and the even-numbered storage capacitor line driving circuits CDi−1 and CDi + 1.

  In the odd-numbered storage capacitor line drive circuit CDi, the source electrode of the first transistor T1 is connected to the first power supply line 40, the drain electrode is connected to the storage capacitor line CSi, and the gate electrode is the second transistor T2. , The drain electrode of the sixth transistor T6, and the drain electrode of the seventh transistor T7. The source electrode of the second transistor T2 is connected to the inverted polarity signal line 43, the drain electrode is connected to the gate electrode of the first transistor T1, and the gate electrode is connected to the scanning line Yi + 1 of the next row i + 1.

  The source electrode of the third transistor T3 is connected to the second power supply line 41, the drain electrode is connected to the storage capacitor line CSi, and the gate electrodes are the drain electrode of the fourth transistor T4 and the drain electrode of the fifth transistor T5. Connected with. The source electrode of the fourth transistor T4 is connected to the inverted polarity signal line 43, the drain electrode is connected to the gate electrode of the third transistor T3, and the gate electrode is connected to the scanning line Yi-1 of the previous row i-1. ing.

  The source electrode of the fifth transistor T5 is connected to the polarity signal line 42, the drain electrode is connected to the gate electrode of the third transistor T3, and the gate electrode is connected to the scanning line Yi + 1 of the next row i + 1. The source electrode of the sixth transistor T6 is connected to the polarity signal line 42, the drain electrode is connected to the gate electrode of the first transistor T1, and the gate electrode is connected to the scanning line Yi-1 of the previous row i-1. Yes. The source electrode of the seventh transistor T7 is connected to the third power supply line 45, the drain electrode is connected to the gate electrode of the first transistor T1, and the gate electrode is connected to the gate control signal line 44.

  On the other hand, the storage capacitor line drive circuit CDi-1 in the even-numbered row is different from the storage capacitor line drive circuit CDi in that the drain electrode of the first transistor T1 and the drain electrode of the third transistor T3 hold. A point connected to the capacitor line CSi-1, a point where the gate electrodes of the second transistor T2 and the fifth transistor T5 are connected to the scanning line Yi of the next row i, a fourth transistor T4 and a sixth transistor The gate electrode of the transistor T6 is connected to the scanning line Yi-2 of the previous row i-2, the source electrodes of the second transistor T2 and the fourth transistor T4 are connected to the polarity signal line 42, The source electrodes of the fifth transistor T5 and the sixth transistor T6 are connected to the inverted polarity signal line 43.

  The storage capacitor line drive circuit CDi + 1 is similar to the storage capacitor line drive circuit CDi-1. However, the drain electrode of the first transistor T1 and the drain electrode of the third transistor T3 are connected to the storage capacitor line CSi + 1, and the gate electrodes of the second transistor T2 and the fifth transistor T5 are connected to the next row i + 2. The difference is that it is connected to the scanning line Yi + 2, and that the gate electrodes of the fourth transistor T4 and the sixth transistor T6 are connected to the scanning line Yi of the previous row i.

  In this way, each of the storage capacitor line drive circuits CDi−1, CDi, CDi + 1 is not the own row, but the second transistor T2 and the fifth transistor T5 that are turned on / off according to the potential of the scanning line of the next row. In the odd-numbered storage capacitor line drive circuit CDi, the polarity signal line 42 is connected to the gate electrode of the third transistor T3, and the inverted polarity signal line 43 is On the other hand, the polarity signal line 42 is connected to the gate electrode of the first transistor T1 and the inverted polarity in the storage capacitor line drive circuits CDi−1 and CDi + 1 in the even-numbered rows connected to the gate electrode of the first transistor T1. The signal line 43 is connected to the gate electrode of the third transistor T3.

  Each of the storage capacitor line drive circuits CDi−1, CDi, CDi + 1 includes a fourth transistor T4 and a sixth transistor T6 that are turned on / off according to the potential of the scanning line of the previous row, not the own row. When these are turned on, in the odd-numbered storage capacitor line drive circuit CDi, the polarity signal line 42 is connected to the gate electrode of the first transistor T1, and the inverted polarity signal line 43 is third. On the other hand, in the even-numbered storage capacitor line drive circuits CDi−1 and CDi + 1, the polarity signal line 42 is connected to the gate electrode of the third transistor T3 and the inverted polarity signal line. 43 is connected to the gate electrode of the first transistor T1.

  Next, the operation (driving method) of the liquid crystal display device LD1 according to the first embodiment configured as described above will be described. In the following, for convenience of explanation, the operation of the liquid crystal display device LD1 will be described with reference to the circuit configuration shown in FIG.

<Operation in normal display mode>
First, the operation in the normal display mode will be described. Here, the normal display mode refers to a mode in which scanning signals are sequentially supplied to all scanning lines.
4 shows the scanning signal Gi-1 supplied to the scanning line Yi-1 shown in FIG. 3, the scanning signal Gi supplied to the scanning line Yi, the scanning signal Gi + 1 supplied to the scanning line Yi + 1, and the scanning line. The scanning signal Gi + 2 supplied to Yi + 2, the polarity signal POL, the inverted polarity signal XPOL, the potential VCHI-1 of the storage capacitor line CSi-1, the potential VCHI of the storage capacitor line CSi, and the potential VCHI + 1 of the storage capacitor line CSi + 1. It is a timing chart which shows the time correspondence with these.

  Here, as shown in FIG. 4, before the Nth frame is started, that is, immediately after the data signal corresponding to the grayscale data of the (N-1) th frame is written to all the pixels, the storage capacitor line The potential VCHi-1 of CSi-1 is maintained at Vc2, the potential VCHi of the storage capacitor line CSi is maintained at Vc1, the potential VCHi + 1 of the storage capacitor line CSi + 1 is maintained at Vc2, and the polarity signal POL is at a high level. It is assumed that the transistor ON potential Vgon and the inverted polarity signal XPOL are at a low level (transistor OFF potential Vgoff).

  That is, the gate electrodes of the first transistors T1 of the storage capacitor line drive circuits CDi−1 and CDi + 1 are maintained at a high level (transistor on-potential Vgon) due to their own parasitic capacitance, and the gate electrodes of the third transistors T3 are The gate electrode of the first transistor T1 of the storage capacitor line driving circuit CDi maintains the low level (transistor off potential Vgoff). The gate electrode of the third transistor T3 is kept at a high level (on-potential Vgon of the transistor).

  In this state, writing of the data signal of the Nth frame is started, the scanning signal Gi-1 having the on potential Vgon is output to the scanning line Yi-1 at the time t1, and the scanning signal having the on potential Vgon at the time t2. Gi is output to the scanning line Yi, the scanning signal Gi + 1 having the ON potential Vgon is output to the scanning line Yi + 1 at time t3, and the scanning signal Gi + 2 having the ON potential Vgon is sequentially output to the scanning line Yi + 2 at time t4. Suppose. Simultaneously with the start of the Nth frame, the polarity signal POL transitions from a high level to a low level, and the inverted polarity signal XPOL transitions from a low level to a high level.

  At time t1, when the scanning signal Gi-1 transitions to the on potential Vgon, all the pixel TFTs 30 connected to the scanning line Yi-1 are turned on. Hereinafter, a period in which the pixel TFT 30 is in an on state is referred to as a data writing period. In such a data writing period, for example, the potential of the data line Xj (data signal Sj) and the counter electrode are applied to the liquid crystal capacitor CL in the pixel corresponding to the intersection of the data line Xj and the scanning line Yi-1 shown in FIG. The charge corresponding to the potential difference from the common potential Vcom of 21 is charged, and the storage capacitor CH is charged according to the potential difference between the potential of the data line Xj and the potential Vc2 of the storage capacitor line CSi-1. . When the scanning signal Gi-1 transitions to the off potential Vgoff and the data writing period ends, all the pixel TFTs 30 connected to the scanning line Yi-1 are turned off, and scanning is performed at time t5 in the next N + 1th frame. Until the signal Gi-1 transitions to the on potential Vgon, the pixels connected to the scanning line Yi-1 enter the data holding period.

  In such a period during which the scanning signal Gi-1 is at the ON potential Vgon (data writing period), the fourth transistor T4 and the sixth transistor T6 in the storage capacitor line driving circuit CDi in the next row i are in the on state. The polarity signal line 42 and the gate electrode of the first transistor T1 are connected, and the inverted polarity signal line 43 and the gate electrode of the third transistor T3 are connected. At this time, since the polarity signal POL is at the low level and the inverted polarity signal XPOL is at the high level, the ON state of the third transistor T3 is maintained and the potential VCHI of the storage capacitor line CSi is also maintained at Vc1. Therefore, even if the scanning signal Gi-1 becomes the ON potential Vgon, the storage capacitor line CSi of the next row i is not affected.

  Subsequently, when the scanning signal Gi transits to the on potential Vgon at time t2, all the pixel TFTs 30 connected to the scanning line Yi are turned on, while the second transistor T2 of the storage capacitor line driving circuit CDi-1 is turned on. And the fifth transistor T5 is turned on. As a result, the polarity signal POL is input to the gate electrode of the first transistor T1 of the storage capacitor line drive circuit CDi-1, and the inverted polarity signal XPOL is input to the gate electrode of the third transistor T3. Since XPOL is at a higher level, the third transistor T3 is turned on, the storage capacitor line CSi-1 and the second power supply line 41 are connected, and the potential VCHi-1 of the storage capacitor line CSi-1 is The transition is from Vc2 to Vc1.

  That is, the potential of the pixel connected to the scanning line Yi-1 (the potential of the pixel electrode 20 based on the potential of the counter electrode 21: hereinafter referred to as pixel potential) is equal to the potential VCHi-1 of the storage capacitor line CSi-1. Shift to the low potential side according to the change ΔV (= Vc2−Vc1). Details of the behavior of the pixel potential will be described later.

  In the data writing period of the scanning line Yi, for example, the liquid crystal capacitor CL in the pixel corresponding to the intersection of the data line Xj and the scanning line Yi shown in FIG. 3 is opposed to the potential of the data line Xj (data signal Sj). A charge corresponding to the potential difference between the electrode 21 and the common potential Vcom is charged, and the storage capacitor CH is charged according to the potential difference between the potential of the data line Xj and the potential Vc1 of the storage capacitor line CSi. When the scanning signal Gi changes to the off potential Vgoff and the data writing period ends, all the pixel TFTs 30 connected to the scanning line Yi are turned off, and the scanning signal Gi is turned on at time t6 in the next N + 1 frame. Until transition to the potential Vgon, the pixels connected to the scanning line Yi enter the data holding period.

  In such a period during which the scanning signal Gi is at the ON potential Vgon (data writing period), the fourth transistor T4 and the sixth transistor T6 in the storage capacitor line driving circuit CDi + 1 in the next row i + 1 are in the ON state, and the polarity The signal line 42 and the gate electrode of the third transistor T3 are connected, and the inverted polarity signal line 43 and the gate electrode of the first transistor T1 are connected. At this time, since the polarity signal POL is at the low level and the inverted polarity signal XPOL is at the high level, the ON state of the first transistor T1 is maintained, and the potential VCHi + 1 of the storage capacitor line CSi + 1 is also maintained at Vc2. Therefore, even if the scanning signal Gi becomes the ON potential Vgon, the storage capacitor line CSi + 1 in the next row i + 1 is not affected.

Subsequently, at time t3, when the scanning signal Gi + 1 transitions to the on potential Vgon, all the pixel TFTs 30 connected to the scanning line Yi + 1 are turned on, while the second transistor T2 and the second transistor T2 of the storage capacitor line driving circuit CDi are turned on. 5 transistor T5 is turned on. As a result, the inverted polarity signal XPOL is input to the gate electrode of the first transistor T1 of the storage capacitor line drive circuit CDi, and the polarity signal POL is input to the gate electrode of the third transistor T3. Therefore, the first transistor T1 is turned on, the storage capacitor line CSi and the first power supply line 40 are connected, and the potential VCHI of the storage capacitor line CSi changes from Vc1 to Vc2. Become.
That is, the potential of the pixel connected to the scanning line Yi shifts to the high potential side according to the change ΔV of the potential VCHi of the storage capacitor line CSi.

  In the data writing period of the scanning line Yi + 1, for example, the liquid crystal capacitor CL in the pixel corresponding to the intersection of the data line Xj and the scanning line Yi + 1 shown in FIG. 3 is opposed to the potential of the data line Xj (data signal Sj). Charges corresponding to the potential difference between the electrode 21 and the common potential Vcom are charged, and the storage capacitor CH is charged according to the potential difference between the potential of the data line Xj and the potential Vc2 of the storage capacitor line CSi + 1. When the scanning signal Gi + 1 changes to the off potential Vgoff and the data writing period ends, all the pixel TFTs 30 connected to the scanning line Yi + 1 are turned off, and the scanning signal Gi + 1 is turned on at time t7 in the next N + 1 frame. The pixels connected to the scanning line Yi + 1 enter the data holding period until the potential Vgon is changed.

  During the period in which the scanning signal Gi + 1 is at the ON potential Vgon (data writing period), the fourth transistor T4 and the sixth transistor T6 in the storage capacitor line driving circuit CDi + 2 (not shown) in the next row i + 2 Although turned on, the storage capacitor line CSi + 2 is not affected as described above.

Subsequently, at time t4, when the scanning signal Gi + 2 transitions to the on potential Vgon, all the pixel TFTs 30 connected to the scanning line Yi + 2 are turned on, while the second transistor T2 and the second transistor T2 of the storage capacitor line driving circuit CDi + 1 are turned on. 5 transistor T5 is turned on. As a result, the polarity signal POL is input to the gate electrode of the first transistor T1 of the storage capacitor line drive circuit CDi + 1, and the inverted polarity signal XPOL is input to the gate electrode of the third transistor T3. Therefore, the third transistor T3 is turned on, the storage capacitor line CSi + 1 and the second power supply line 41 are connected, and the potential VCHi + 1 of the storage capacitor line CSi + 1 transits from Vc2 to Vc1. Become.
That is, the potential of the pixel connected to the scanning line Yi + 1 is shifted to the low potential side in accordance with the change ΔV of the potential VCHi + 1 of the storage capacitor line CSi + 1.

  When the data writing period of the scanning line Yi + 2 ends, the pixels connected to the scanning line Yi + 2 enter the data holding period until the scanning signal Gi + 2 transitions to the on potential Vgon at time t8 in the next N + 1 frame. Further, in the period (data writing period) in which the scanning signal Gi + 2 is at the ON potential Vgon, the fourth transistor T4 and the sixth transistor in the storage capacitor line driving circuit CDi + 3 (not shown) in the next row i + 3. Although T6 is turned on, it does not affect the storage capacitor line CSi + 3 as described above.

  Here, the behavior of the pixel potential will be described in detail with reference to FIG. In FIG. 5, for the convenience of explanation, the behavior of the pixel potential relating to the pixel Pji corresponding to the intersection of the data line Xj and the scanning line Yi is representatively illustrated. In addition, although the potential Vc1 on the low voltage side of the storage capacitor line CSi and the common potential Vcom of the counter electrode 21 are actually different values, they are treated as being equal to each other for the sake of simplicity. Further, it is assumed that the pixel potential Vp of the pixel Pij is held at a potential on the negative polarity side with respect to the common potential Vcom before the Nth frame is started, that is, in the (N−1) th frame.

  First, at time t2, when the scanning signal Gi transitions to the on potential Vgon, the pixel TFT 30 of the pixel Pji is turned on, and charges corresponding to the potential of the data signal Sj are applied to the liquid crystal capacitor CL and the holding capacitor CH of the pixel Pji. Charged. Here, since the pixel potential Vp of the pixel Pji was negative in the previous (N−1) th frame, data having the potential VSH for inverting the pixel potential Vp to the positive side in the current Nth frame. A signal Sj is supplied. Note that a writing voltage charged in the liquid crystal capacitor CL and the holding capacitor CH is V0.

  When the scanning signal Gi changes to the off potential Vgoff, the data writing period ends, and when the scanning signal Gi + 1 changes to the on potential Vgon at time t3, the potential VCHi of the storage capacitor CSi changes from the low potential Vc1 to the high potential Vc2. Transition. As a result, the charging voltage in the storage capacitor CH is shifted to the high potential side by the change ΔV (= Vc2−Vc1) of the potential VCHi of the storage capacitor line CSi. Here, since the storage capacitor CH and the liquid crystal capacitor CL are connected, charge is transferred from the storage capacitor CH to the liquid crystal capacitor CL. Then, when the potential difference between the holding capacitor CH and the liquid crystal capacitor CL disappears, the charge transfer ends, so the charging voltage of the liquid crystal capacitor CL and the holding capacitor CH in the Nth frame finally becomes the voltage V1. Since the charging voltage V1 continues to be held in the liquid crystal capacitor CL in the data holding period, the charging voltage V1 is substantially held in the liquid crystal capacitor CL from the time when the pixel TFT 30 is on (data writing period). It can be regarded as a thing.

Here, the charging voltage V1 can be expressed by the following equation (1), where Cstg is the capacitance value of the storage capacitor CH and Clc is the capacitance value of the liquid crystal capacitor CL.
V1 = V0 + ΔV · {Cstg / (Cstg + Clc)} (1)

When the storage capacitor Cstg is sufficiently larger than the liquid crystal capacitor Clc, the above equation (1) can be approximated as the following (2).
V1 = V0 + ΔV (2)

  That is, the final charging voltage V1 (that is, the pixel potential Vp) of the liquid crystal capacitor CL in the Nth frame is the change ΔV (= Vc2−Vc1) of the potential VCHI of the storage capacitor line CSi from the writing voltage V0 in the data writing period. It is simplified as a shift to the higher potential side.

  The case where the pixel potential Vp is inverted to the positive polarity side in the Nth frame has been described above. Hereinafter, the case where the pixel potential Vp is inverted to the negative polarity side in the next N + 1 frame will be described. When the scanning signal Gi transitions to the on potential Vgon at the time t6 of the (N + 1) th frame, the pixel TFT 30 of the pixel Pji is turned on, and the charge corresponding to the potential of the data signal Sj is applied to the liquid crystal capacitor CL and the holding capacitor CH of the pixel Pji. Is charged. Here, since the pixel potential Vp of the pixel Pji was positive in the previous Nth frame, in this N + 1th frame, the data signal Sj having the potential VSL for inverting the pixel potential Vp to the negative polarity side. Is supplied. Here, the writing voltage charged in the liquid crystal capacitor CL and the holding capacitor CH is V0 (however, the potential on the negative polarity side with respect to the common potential Vcom).

  When the scanning signal Gi changes to the off potential Vgoff, the data writing period ends, and when the scanning signal Gi + 1 changes to the on potential Vgon at time t7, the potential VCHi of the storage capacitor CSi changes from the high potential Vc2 to the low potential Vc2. Transition. As a result, the charging voltage in the storage capacitor CH is shifted to the low potential side by the change ΔV of the potential VCHi of the storage capacitor line CSi. Here, charge is transferred until the potential difference between the holding capacitor CH and the liquid crystal capacitor CL disappears, and the charging voltage of the liquid crystal capacitor CL and the holding capacitor CH in the (N + 1) th frame is finally the voltage V1 (however, with respect to the common potential Vcom). To negative potential). As described above, the final charging voltage V1 (that is, the pixel potential Vp) of the liquid crystal capacitor CL in the (N + 1) th frame is lower than the write voltage V0 in the data write period by the change ΔV of the potential VCHi of the storage capacitor line CSi. It is simplified as a shift to.

  As described above, the behavior of the pixel potential Vp has been described by paying attention to the pixel Pji connected to the scanning line Yi. However, in the pixels connected to the preceding and subsequent scanning lines Yi−1 and Yi + 1, the behavior opposite to that of the scanning line Yi is obtained. Become. That is, the pixel potential Vp of the pixels connected to the scanning lines Yi−1 and Yi + 1 is held at a positive potential with respect to the common potential Vcom in the (N−1) th frame, and is negative in the Nth frame. In the N + 1th frame, it is inverted again to the positive polarity side.

  As described above, in the normal display mode, the potentials of the storage capacitor lines CS1 to CSm are individually controlled to shift the pixel potential Vp to the high potential side or the low potential side, thereby reducing the voltage amplitude of the data signal. Therefore, low power consumption can be achieved.

  In the above embodiment, the case where the scanning direction is changed from the scanning line Y1 to Ym (when the scanning signals are supplied in the order of G1, G2,..., Gm) has been described, but the reverse scanning direction, that is, the scanning direction. Can be dealt with without any problem even when the scanning line Ym → Y1 (when the scanning signals are supplied in the order of Gm, Gm−1,..., G1).

<Operation in partial display mode>
Next, the operation in the partial display mode will be described. In the normal display mode described above, each scanning line is sequentially selected at about 60 Hz, that is, every 1/60 seconds. Therefore, the gate potential of the first transistor T1 is the next due to the parasitic capacitance of its own gate electrode. It is kept at the high level until the frame and the on state is continued. However, in the case of the so-called partial display mode in which only a few scanning lines are selected, the selection frequency of non-selected rows is about once every ½ second, that is, the data holding period becomes long. In the simplified circuit configuration used in FIG. 1, the first transistor T1 cannot hold the high level potential due to the charge leakage of the parasitic capacitance of the gate electrode (becomes off), and the storage capacitor line is in the high impedance state. End up. At this time, if the potential of the data line changes, for example, a display defect such as flickering occurs. In addition, when the data retention period becomes longer as described above, the potential of the storage capacitor line changes due to the leakage current, and burn-in or the like occurs. Such a problem can be avoided by applying a large capacitance to the gate electrode of the first transistor T1, but the occupied area of the storage capacitor line driving circuit becomes large, and the frame area becomes wide. There is.

  Therefore, in the liquid crystal display device LD1 according to the present embodiment, in the partial display mode, the gate control signal Cntg having the ON potential Vgon is supplied to the gate control signal line 44 during a period when no scanning line is selected. . Accordingly, in all the storage capacitor line drive circuits CD1 to CDm, the seventh transistor T7 is turned on, the third power supply line 45 and the gate electrode of the first transistor T1 are connected, and the first transistor T1 is connected. Is also turned on. That is, all the storage capacitor lines CS1 to CSm are connected to the first power supply line 40 and maintained at the high potential Vc2. Thereby, in the partial display mode, the potential change of the storage capacitor line can be suppressed, and the occurrence of burn-in can be prevented. Further, flickering can be prevented by controlling the amplitude of the data signal to change during this period.

  As described above, according to the liquid crystal display device LD1 according to the present embodiment, when the storage capacitor line driving circuit is configured using the simplified circuit configuration used in the present invention, it occurs in the display mode with a long data retention period. It is possible to prevent display quality deterioration.

(Second Embodiment)
Next, a liquid crystal display device according to a second embodiment will be described. FIG. 6 shows a circuit configuration diagram of a liquid crystal display device LD2 according to the second embodiment. In FIG. 6, the same components as those of the liquid crystal display device LD1 of the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

  As shown in FIG. 6, the liquid crystal display device LD <b> 2 according to the second embodiment is different from the first embodiment in that the odd row capacitance line potential detection line 60, the even row capacitance line potential detection line 61, and the odd row voltage. The distortion correction circuit 70 and the even-numbered row voltage correction circuit 80 are provided, and the eighth transistor T8 is newly provided in each of the storage capacitor line drive circuits CD1 to CDm.

  The odd-numbered rows will be described using the storage capacitor line drive circuit CDi as a representative example. The source electrode of the eighth transistor T8 is connected to the storage capacitance line CSi, and the drain electrode is connected to the odd-number row capacitance line potential detection line 60. The gate electrode is connected to the scanning line Yi.

  The odd row voltage distortion correction circuit 70 includes an analog switch circuit 70a, a first operational amplifier 70b, and a second operational amplifier 70c. When the polarity signal POL is at a high level, the analog switch circuit 70a electrically connects the odd-numbered capacitor line potential detection line 60 and the inverting input terminal of the first operational amplifier 70b, and the polarity signal POL is at a low level. In this case, the odd-numbered capacitor line potential detection line 60 and the inverting input terminal of the second operational amplifier 70c are electrically connected.

  The non-inverting input terminal of the first operational amplifier 70b is supplied with the high potential Vc2, the inverting input terminal is connected to the analog switch circuit 70a, and the output terminal is connected to the first power supply line 40 corresponding to the retention capacitor line in the odd row. It is connected. The non-inverting input terminal of the second operational amplifier 70c is supplied with the low potential Vc1, the inverting input terminal is connected to the analog switch circuit 70a, and the output terminal is connected to the second power supply line 41 corresponding to the odd-numbered storage capacitor lines. It is connected.

  On the other hand, regarding the even-numbered row, the holding capacitor line drive circuit CDi-1 will be described as a representative example. The source electrode of the eighth transistor T8 is connected to the holding capacitor line CSi-1, and the drain electrode is the even-row capacitor line potential. Connected to the detection line 61, the gate electrode is connected to the scanning line Yi-1.

  The even row voltage distortion correction circuit 80 includes an analog switch circuit 80a, a first operational amplifier 80b, and a second operational amplifier 80c. When the polarity signal POL is at a low level, the analog switch circuit 80a electrically connects the even-row capacitor line potential detection line 61 and the inverting input terminal of the first operational amplifier 80b, and the polarity signal POL is at a high level. In this case, the even-numbered capacitance line potential detection line 61 and the inverting input terminal of the second operational amplifier 80c are electrically connected.

  The non-inverting input terminal of the first operational amplifier 80b is supplied with the high potential Vc2, the inverting input terminal is connected to the analog switch circuit 80a, and the output terminal is connected to the first power supply line 40 corresponding to the even-numbered storage capacitor lines. It is connected. The non-inverting input terminal of the second operational amplifier 80c is supplied with the low potential Vc1, the inverting input terminal is connected to the analog switch circuit 80a, and the output terminal is connected to the second power supply line 41 corresponding to the even-numbered storage capacitor lines. It is connected.

  Next, the operation of the thus configured liquid crystal display device LD2 according to the second embodiment will be described. Note that the basic operation of the liquid crystal display device LD2 according to the second embodiment is the same as that of the first embodiment. Therefore, hereinafter, the characteristics of the liquid crystal display device LD2 according to the second embodiment will be described with reference to FIG. A typical operation will be described.

  As shown in FIG. 4, first, at time t1, when the scanning signal Gi-1 transitions to the on potential Vgon, all the pixel TFTs 30 connected to the scanning line Yi-1 are turned on, for example, scanning with the data line Xj. The liquid crystal capacitor CL in the pixel corresponding to the intersection with the line Yi-1 is charged with a charge corresponding to the potential difference between the potential of the data line Xj (data signal Sj) and the common potential Vcom of the counter electrode 21, and The storage capacitor CH is charged with a charge corresponding to the potential difference between the potential of the data line Xj and the potential Vc2 of the storage capacitor line CSi-1.

  At this time, since the eighth transistor T8 of the storage capacitor line drive circuit CDi-1 is turned on, the storage capacitor line CSi-1 and the even-row capacitor line potential detection line 61 are electrically connected. On the other hand, since the low level polarity signal POL is input to the analog switch circuit 80a of the even row voltage distortion correction circuit 80, the even row capacitance line potential detection line 61 and the inverting input terminal of the first operational amplifier 80b are connected. Electrically connected. That is, the storage capacitor line CSi-1 and the inverting input terminal of the first operational amplifier 80b are electrically connected.

  Here, as shown in FIG. 7, when waveform distortion occurs in the potential of the even-numbered row capacitor line potential detection line 61, that is, the potential Vc2 of the storage capacitor line CSi-1, the output terminal of the first operational amplifier 80b Vc 2 having a voltage waveform that cancels the waveform distortion is supplied to the first power supply line 40. That is, even when waveform distortion occurs in the potential Vc2 of the storage capacitor line CSi-1 during the data writing period of the pixels connected to the scanning line Yi-1, the waveform distortion is even-numbered row voltage distortion correction circuit 80. Therefore, a desired charge voltage can be obtained and display unevenness can be prevented.

  On the other hand, when the scanning signal Gi transitions to the on potential Vgon at time t2, all the pixel TFTs 30 connected to the scanning line Yi are turned on. For example, in the pixel corresponding to the intersection of the data line Xj and the scanning line Yi. The liquid crystal capacitor CL is charged with a charge corresponding to the potential difference between the potential of the data line Xj (data signal Sj) and the common potential Vcom of the counter electrode 21, and the storage capacitor CH holds the potential of the data line Xj. Charge corresponding to the potential difference from the potential Vc1 of the capacitor line CSi is charged.

  At this time, since the eighth transistor T8 of the storage capacitor line driving circuit CDi is turned on, the storage capacitor line CSi and the odd-numbered capacitor line potential detection line 60 are electrically connected. On the other hand, since the low-level polarity signal POL is input to the analog switch circuit 70a of the odd row voltage distortion correction circuit 70, the odd row capacitance line potential detection line 60 and the inverting input terminal of the second operational amplifier 70c are connected. Electrically connected. That is, the storage capacitor line CSi and the inverting input terminal of the second operational amplifier 70c are electrically connected.

  Here, when a waveform distortion occurs in the potential of the odd-numbered capacitor line potential detection line 60, that is, the potential Vc1 of the storage capacitor line CSi, a voltage waveform that cancels the waveform distortion from the output terminal of the second operational amplifier 70c. Is supplied to the second power supply line 41. In other words, even if waveform distortion occurs in the potential Vc1 of the storage capacitor line CSi during the data writing period of the pixels connected to the scanning line Yi, the waveform distortion is caused by the odd-numbered row voltage distortion correction circuit 70. Therefore, a desired charging voltage can be obtained, and display unevenness can be prevented.

  As described above, according to the liquid crystal display device LD2 according to the second embodiment, it is possible to prevent display unevenness due to the voltage distortion of the storage capacitor line that occurs in the data writing period, and the same as in the first embodiment. In addition, it is possible to prevent deterioration in display quality that occurs in a display mode with a long data retention period.

  In the above, one embodiment of the electro-optical device according to the present invention has been described by exemplifying a liquid crystal display device. However, the present invention is not limited to this, and those using other electro-optical materials such as an organic EL display device and a PDP You may apply to (plasma display) etc.

  In the above embodiment, the source electrodes of the second transistor T2 and the fourth transistor T4 are connected to the inverted polarity signal line 43 in the odd-numbered storage capacitor line driving circuit, and the fifth transistor T5 and the sixth transistor T5 are connected. The source electrode of the transistor T6 and the polarity signal line 42 are connected, while the source electrodes of the second transistor T2 and the fourth transistor T4 and the polarity signal line 42 are connected in the even-numbered storage capacitor line driving circuit. Although the configuration in which the source electrodes of the fifth transistor T5 and the sixth transistor T6 and the inverted polarity signal line 43 are connected is illustrated, the reverse configuration may be employed. That is, in the storage capacitor line driving circuit in the odd-numbered rows, the source electrodes of the second transistor T2 and the fourth transistor T4 are connected to the polarity signal line 42, and the source electrodes of the fifth transistor T5 and the sixth transistor T6 are connected. Are connected to the inverted polarity signal line 43, and in the even-numbered storage capacitor line driving circuit, the source electrodes of the second transistor T2 and the fourth transistor T4 and the inverted polarity signal line 43 are connected to each other. The source electrodes of the transistor T5 and the sixth transistor T6 may be connected to the polarity signal line 42.

〔Electronics〕
Next, a specific example of an electronic apparatus including the above electro-optical device will be described.
FIG. 7A is a perspective view showing an example of a mobile phone. In FIG. 7A, reference numeral 100 denotes a mobile phone body, and reference numeral 101 denotes a liquid crystal display unit including the liquid crystal display device of the above embodiment. FIG. 7B is a perspective view showing an example of a portable information processing apparatus such as a word processor or a personal computer. In FIG. 7B, reference numeral 200 denotes an information processing apparatus, 201 denotes an input unit such as a keyboard, 202 denotes an information processing body, and 203 denotes a liquid crystal display unit including the liquid crystal display device of the above embodiment. FIG. 7C is a perspective view showing an example of a wristwatch type electronic apparatus. In FIG.7 (c), the code | symbol 300 shows a wristwatch main body, 301 shows the liquid crystal display part provided with the liquid crystal display device of the said embodiment. Although the electronic apparatus of the present embodiment includes a liquid crystal display device, it may include other electro-optical devices such as an organic EL display device and a PDP. Further, the electronic device is not limited to these, and can be applied to various electronic devices having a display function. For example, in addition to these, a fax machine with a display function, a finder for a digital camera, a portable TV, an electronic notebook, an electric bulletin board, a display for advertising, etc. are also included.

1 is an external view of a liquid crystal display device LD1 according to a first embodiment of the present invention. 1 is a circuit configuration diagram of a liquid crystal display device LD1 according to a first embodiment of the present invention. 1 is a detailed circuit configuration diagram of a liquid crystal display device LD1 according to a first embodiment of the present invention. FIG. 7 is a first operation explanatory diagram of the liquid crystal display device LD1 according to the first embodiment of the present invention. FIG. 6 is a second operation explanatory diagram of the liquid crystal display device LD1 according to the first embodiment of the present invention. It is a detailed circuit block diagram of liquid crystal display device LD2 which concerns on 2nd Embodiment of this invention. It is an example of the electronic device which concerns on this invention.

Explanation of symbols

  LD1, LD2, LD3, LD4 ... liquid crystal display device, 10 ... circuit board, 11 ... counter substrate, 12 ... sealing material, 13 ... liquid crystal, 14 ... window frame, 15 ... data line driving circuit, 16 ... mounting terminal, 17 ... Scanning line driving circuit, 18 ... wiring, 19 ... inter-substrate conductive material, 20 ... pixel electrode, 21 ... counter electrode, Y1 to Ym ... scanning line, X1 to Xn ... data line, CS1 to CSm ... holding capacitor line, 30 ... Pixel TFT, CL ... Liquid crystal capacitor, CH ... Holding capacitor, CD1 to CDm ... Holding capacitor line drive circuit, 40 ... First power line, 41 ... Second power line, 42 ... Polar signal line, 43 ... Inverted polarity signal Lines 44... Gate control signal lines 45. Third power lines 60. Odd-row capacitance line potential monitoring lines 61. Even-row capacitance line potential monitoring lines 70. Odd-row voltage distortion correction circuits 80. Voltage correction circuit, T1... First transistor, T ... second transistor, T3 ... third transistor, T4 ... fourth transistors, T5 ... fifth transistor, T6 ... sixth transistors, T7 ... seventh transistor, T8 ... eighth transistor

Claims (5)

A plurality of data lines and scanning lines, a storage capacitor line provided corresponding to each of the scanning lines, a pixel electrode and a counter electrode provided corresponding to the intersection of the data line and the scanning line A pixel capacitor having an electro-optical material sandwiched between them, a storage capacitor having one end connected to the storage capacitor line and the other end connected to the pixel electrode, and a scanning signal supplied via the scanning line An electro-optical device comprising a pixel having a switching element that switches connection / disconnection between the data line and the pixel electrode in response.
A first power supply line maintained at a first voltage on the high voltage side to be applied to the storage capacitor line;
A second power supply line maintained at a second potential on the low voltage side to be applied to the storage capacitor line;
A polarity signal line for supplying a polarity signal whose logic level is inverted every frame;
An inverted polarity signal line for supplying an inverted polarity signal that is a logically inverted signal of the polarity signal;
A gate control signal line for supplying a gate control signal;
A third power supply line maintained at the gate on potential of the transistor;
Provided corresponding to each of the storage capacitor lines,
A first transistor having a source electrode connected to the first power supply line and a drain electrode connected to the storage capacitor line of the bank;
If the storage capacitor line of this row is an odd row, the source electrode is connected to one of the polarity signal line or the inverted polarity signal line, and if it is an even row, the source electrode is the other of the polarity signal line or the inverted polarity signal line. A second transistor in which a drain electrode is connected to a gate electrode of the first transistor, and a gate electrode is connected to a scanning line of the next row;
A third transistor having a source electrode connected to the second power supply line and a drain electrode connected to the storage capacitor line of the bank;
If the storage capacitor line of this row is an odd row, the source electrode is connected to one of the polarity signal line or the inverted polarity signal line, and if it is an even row, the source electrode is the other of the polarity signal line or the inverted polarity signal line. A fourth transistor in which the drain electrode is connected to the gate electrode of the third transistor, and the gate electrode is connected to the scanning line of the previous row;
If the storage capacitor line of this row is an odd row, the source electrode is connected to the other of the polarity signal line or the inverted polarity signal line, and if it is an even row, the source electrode is one of the polarity signal line or the inverted polarity signal line. A fifth transistor in which the drain electrode is connected to the gate electrode of the third transistor, and the gate electrode is connected to the scanning line of the next row;
If the storage capacitor line of this row is an odd row, the source electrode is connected to the other of the polarity signal line or the inverted polarity signal line, and if it is an even row, the source electrode is one of the polarity signal line or the inverted polarity signal line. A sixth transistor in which the drain electrode is connected to the gate electrode of the first transistor, and the gate electrode is connected to the scanning line of the previous row;
A storage capacitor having a seventh electrode having a source electrode connected to the third power supply line, a drain electrode connected to the gate electrode of the first transistor, and a gate electrode connected to the gate control signal line; A drive circuit;
An electro-optical device comprising: Odd-numbered capacitance line potential detection line for detecting the potential of the odd-numbered storage capacitor line;
An even-numbered capacity line potential detection line for detecting the potential of the even-numbered capacity line;
An odd-row voltage distortion correction circuit for correcting voltage waveforms of the first power supply line and the second power supply line corresponding to the odd-numbered storage capacitor lines so as to cancel the voltage waveform distortion of the odd-numbered capacity line potential detection lines; ,
An even-numbered row voltage distortion correction circuit for correcting voltage waveforms of the first power supply line and the second power supply line corresponding to the even-numbered storage capacitor lines so as to cancel the voltage waveform distortion of the even-numbered capacitance line potential detection lines; With
Each of the storage capacitor driving circuits includes:
If the source electrode is connected to the storage capacitor line of this row, and the storage capacitor line of this row is an odd row, the drain electrode is connected to the odd row capacitance line potential detection line, and if it is an even row, the drain electrode is connected to the even row capacitance An eighth transistor connected to the line potential detection line and having a gate electrode connected to the scan line of the bank;
The electro-optical device according to claim 1. The odd row voltage distortion correction circuit includes:
A first operational amplifier having the first potential as an input of a non-inverting input terminal and an output terminal connected to one end of a first power supply line corresponding to an odd row of storage capacitor lines;
A second operational amplifier having the second potential as an input of a non-inverting input terminal and an output terminal connected to one end of a second power supply line corresponding to an odd row of storage capacitor lines;
According to the polarity signal or the inverted polarity signal, whether to connect the odd-numbered capacitor line potential detection line to the inverting input terminal of the first operational amplifier or to the inverting input terminal of the second operational amplifier. A switch circuit for switching,
The even row voltage distortion correction circuit includes:
A first operational amplifier having the first potential as an input of a non-inverting input terminal and an output terminal connected to one end of a first power supply line corresponding to a storage capacitor line in an even row;
A second operational amplifier in which the second potential is input to a non-inverting input terminal, and an output terminal is connected to one end of a second power supply line corresponding to an even-numbered storage capacitor line;
Whether to connect the even-row capacitor line potential detection line to the inverting input terminal of the first operational amplifier or to the inverting input terminal of the second operational amplifier according to the polarity signal or the inverted polarity signal. A switch circuit for switching,
The electro-optical device according to claim 2. A plurality of data lines and scanning lines, a storage capacitor line provided corresponding to each of the scanning lines, a pixel electrode and a counter electrode provided corresponding to the intersection of the data line and the scanning line A pixel capacitor having an electro-optical material sandwiched between them, a storage capacitor having one end connected to the storage capacitor line and the other end connected to the pixel electrode, and a scanning signal supplied via the scanning line A driving method of an electro-optical device including a pixel having a switching element that switches connection / disconnection between the data line and the pixel electrode in response.
In the normal display mode in which each scanning line is sequentially selected by sequentially supplying scanning signals,
In synchronization with the scanning signal of the selected scanning line, if the pixel potential connected to the scanning line of the previous row of the selected scanning line is negative, the storage capacitor line corresponding to the scanning line of the previous row is If the potential is changed from the first potential on the high-voltage side to the second potential on the low-voltage side and the pixel potential connected to the scanning line in the previous row is positive, the storage capacitor line corresponding to the scanning line in the previous row Transition from the second potential to the first potential,
In the partial display mode in which scanning lines are partially selected by partially supplying scanning signals,
Maintaining the potentials of all the storage capacitor lines at the first potential;
A driving method for an electro-optical device.   An electronic apparatus comprising the electro-optical device according to claim 1.

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