JP2006235267A - Method and device for driving semiconductor device, and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To use an element which is small in size and low in breaking strength with respect to an AC driving method for a liquid crystal display device. <P>SOLUTION: One electrode 36a of a pixel capacitor 36 in a pixel cell 30 is connected to a pixel electrode 34a of a liquid crystal cell 34, the other electrode 36 is connected to the source electrode 33S of a pixel transistor 33, and a signal line 14 is connected to the drain electrode 33D of the pixel transistor 33. An AC potential corresponding to an input signal is sampled in the liquid crystal cell 34 through the pixel transistor 33 and pixel capacitor 36. A potential applied to the pixel cell 30 is nearly equal to an input video signal amplitude Va. A cell can be made small-sized by lowering the dielectric strength of a transistor for a switch used for the cell and further the dielectric strength of an element used for a driver for signal supply can also be lowered. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device driving method, a driving device, and a semiconductor device. More specifically, a display device (electro-optical device) such as an active matrix system having a pixel transistor typified by a liquid crystal display (LCD) on a semiconductor substrate, and a drive for driving a matrix pixel array. The present invention relates to a method and a driving apparatus, and more particularly, to an improvement of a pixel structure suitable for low voltage driving and a corresponding driving technique.

  When driving a display device such as a liquid crystal display device, a display drive circuit corresponding to the response speed of the device is used. The display drive method is roughly divided into a simple matrix method and an active matrix method.

  In the simple matrix method, basically, a liquid crystal composition layer (liquid crystal layer) is sandwiched between a pair of insulating substrates, at least one of which is made of a transparent glass plate, plastic substrate, or the like. This is also called a liquid crystal cell, and the voltage is selectively applied to the various pixel-forming electrodes formed on the insulating substrate of the liquid crystal panel to change the alignment direction of the liquid crystal molecules that make up the liquid crystal composition of the predetermined pixel portion. In this manner, the pixel is formed.

  On the other hand, in the active matrix system, various electrodes and active elements for pixel selection are formed, and by selecting the active element, the alignment direction of the liquid crystal molecules of the pixel between the pixel electrode connected to the active element and the reference electrode is changed. This is a form in which the pixels are formed by changing the shape.

  For example, in general, in a display device driven by an active matrix system, a plurality of scanning lines (also referred to as gate lines) and a plurality of signal lines (also referred to as data lines) are arranged vertically and horizontally, and correspond to each intersection. The pixel electrode is formed via a switching element made of a thin film transistor (TFT) such as a thin film diode (TFD) or a field effect transistor (FET).

  Among these, the scanning signal is sequentially supplied to each scanning line by the scanning line driving unit. On the other hand, each signal line is driven by a signal line driver. That is, the signal line driving unit supplies the sampling control signal to the sampling switch that samples the image signal supplied to the image signal line for each data line in synchronization with the sequential supply operation of the scanning signal. It is configured.

  In such an active matrix display device, each drive unit is usually divided into a vertical drive unit and a horizontal drive unit. In general, the scanning line driving unit is a vertical driving unit, and the signal line driving unit is a horizontal driving unit. Here, the vertical driving unit sequentially selects each pixel through the scanning line. The horizontal drive unit writes an image signal to the selected pixel through the signal line.

  Various driving methods and pixel circuit structures corresponding to the driving have been proposed (see, for example, Patent Documents 1 and 2).

Japanese Patent No. 299725 JP 2002-278517 A

  On the other hand, in recent years, there has been a demand for higher definition for active matrix liquid crystal display devices. Here, the high definition of the liquid crystal panel leads to an increase in the number of pixels, and the chip size of the semiconductor substrate of the high definition active matrix type liquid crystal display device tends to be enlarging, so the semiconductor chip size is reduced. For this purpose, downsizing of the pixel cell is required.

  Also, the FET used as a pixel switch on the semiconductor substrate must have a process breakdown voltage (gate oxide breakdown voltage, PN junction breakdown voltage, etc.) that is equal to or greater than the voltage amplitude of the image data signal input from the outside of the semiconductor substrate. It is generally known that the minimum layout design rule of the FET is determined by the breakdown voltage, and it is difficult to reduce the size of the FET used for the pixel switch.

  FIG. 4 is a diagram showing an equivalent circuit of a general pixel cell disclosed in Patent Document 1 and the like. The pixel cell 70 includes, for example, an NMOS pixel transistor 72 composed of a thin film transistor (TFT), a liquid crystal cell 74 in which a pixel electrode 74 a is connected to the source electrode 72 S of the pixel transistor 72, and a source electrode of the pixel transistor 72. The pixel capacitor (retention capacitor) 76 has one electrode 76a connected to 72S. In short, in addition to the liquid crystal cell 74, one pixel transistor 72 as a pixel switch and a pixel capacitor 76 are provided.

  In the pixel transistor 72, the gate electrode 72 </ b> G is connected to the scanning line (gate line) 92, and the drain electrode 72 </ b> D is connected to the signal line (data line) 94. A gate driving signal Vg72 is supplied to the scanning line 92 from a vertical driving unit (scanning line driving unit) (not shown), and a pixel corresponding to an input video signal from a horizontal driving unit (signal line driving unit) (not shown) to the signal line 94. A signal Vsig is supplied.

  For example, the counter electrode 74b of the liquid crystal cell 74 is commonly connected to each pixel cell 70 with respect to a common line (not shown). A common voltage (counter electrode voltage) for fixed driving or inversion (alternating current) driving is applied to the counter electrode 74 b of the liquid crystal cell 74 through the common line in common to each pixel cell 70.

  In addition, the other electrode 76 b of the pixel capacitor 76 is commonly connected to each pixel cell 70 with respect to the capacitor line 98. A reference voltage (counter electrode voltage) that is fixedly driven via the capacitor line 98 is applied to the electrode 76b in common for each pixel cell 70. The reference voltage may be a common voltage as with the counter electrode 74b of the liquid crystal cell 74, or may be a ground (GND) voltage.

  FIG. 5 is a timing chart for explaining one method for driving the pixel cell 70 shown in FIG. As the pixel signal Vsig, a constant common voltage (counter electrode voltage) Vcom is applied to the counter electrode 74b serving as a reference electrode in order to perform alternating driving in which the polarity of the voltage applied to the liquid crystal layer is periodically reversed. In order to apply positive and negative signal voltages to the electrode 74a, positive and negative voltages (a magnitude of 2Va as a whole) having a magnitude of Va are supplied to the common voltage Vcom. That is, in the driving method of the pixel cell 70 shown in FIG. 5, since data inversion cannot be performed in the pixel cell 70, it is necessary to input the pixel signal Vsig with data inverted with respect to the common voltage Vcom by an external driver. . For example, in the illustrated example, the transition is to + Va at time t63, and the transition is to −Va at time t73. Here, the purpose of AC driving is to prevent deterioration due to application of a DC voltage to the liquid crystal.

  Here, when driving a pixel cell 70 composed of a total of two elements, one pixel switch and one pixel capacitor, typically, the gate electrode 72G of the pixel transistor 72 is a gate drive supplied to the scanning line 92. It is controlled by the signal Vg72.

  Specifically, as shown in FIG. 5, when the gate drive signal Vg72 becomes H (high) level (t64 to t66, t74 to t76), the pixel transistor 72 becomes conductive, and the signal is transmitted through the pixel transistor 72. The potential of the pixel signal Vsig supplied to the line 94 is sampled by the pixel capacitor 76, and the potential Vs72 of the source electrode 72S of the pixel transistor 72 is made substantially the same as the potential of the pixel signal Vsig (t65, t75). That is, the written pixel signal is accumulated as charges in the liquid crystal cell 74 and the pixel capacitor 76, and the projection light reflected from the surface of the pixel electrode is modulated by the liquid crystal in which the charges are accumulated, and display is performed. This display is maintained until it is rewritten next time.

Although the structure and driving method of the pixel cell 70 are the simplest, since the drain electrode 72D, the source electrode 72S, and the pixel capacitor 76 of the pixel transistor 72 are driven via the signal line 94, the input video signal When the amplitude is Va, the source potential Vs72 and the drain potential Vd72 of the pixel transistor 72 are 2 × Va or more. Therefore, the pixel transistor 72 needs to have a gate breakdown voltage V _GSS and a source / drain breakdown voltage V _{DSS of} at least 2 × Va or more.

  That is, in the AC driving method described above, the pixel transistor 72 used as the drive circuit needs to have a high breakdown voltage so as to withstand a potential difference between the highest voltage on the positive polarity side and the lowest voltage on the negative polarity side. Further, the gate drive signal Vg72 (scanning signal) for controlling on / off of the pixel transistor 72 also requires a high voltage.

  However, in a high withstand voltage circuit, it is difficult to finely form each part constituting the circuit, and the circuit scale becomes large. Even if an increase in the number of pixels is required, the minimum size of the pixel cell is determined by the minimum layout design rule of an active element such as an FET within a limited pixel area. It is difficult to form a high withstand voltage configuration used as a pixel switch, and the AC driving method described above is unsuitable for the purpose of reducing the pixel cell size (reducing the pixel size), and reducing the chip size. It is difficult.

  The technique described in Patent Document 2 has been proposed as a technique for solving such a problem. The technique described in Patent Document 2 allows a pixel voltage control signal to be supplied to a pixel capacitor and fluctuates the voltage of the pixel electrode, thereby enabling AC driving with a low breakdown voltage driving circuit. The scale is reduced to enable high-speed driving.

  FIG. 6 is a diagram showing an equivalent circuit of a pixel cell shown in Patent Document 2 in which a terminal on one side of the pixel capacitor is configured to be AC driven. Similar to the structure shown in FIG. 4, the pixel cell 80 includes an NMOS pixel transistor 82, a liquid crystal cell 84 in which the pixel electrode 84 a is connected to the source electrode 82 S of the pixel transistor 82, and the source of the pixel transistor 82. The pixel capacitor 86 has one electrode 86a connected to the electrode 82S.

  Although the circuit configuration is not different from that shown in FIG. 4, the other electrode 86 b of the pixel capacitor 86 is supplied with a pixel potential control signal Vcs for AC driving the electrode 86 b via the capacitor line 98, thereby The difference is that the voltage of the pixel electrode 84a is varied.

  FIG. 7 is a timing chart for explaining one method of driving the pixel cell 80 shown in FIG. In FIG. 7, the period from time t80 to time t90 is the time when the pixel signal Vsig corresponding to the input video signal is in the positive polarity input signal mode, that is, in the positive polarity mode in which the potential Vs32 of the source electrode 32S is positive.

  When the input video signal amplitude is Va, the gate electrode 82G of the pixel transistor 82 is controlled by the gate drive signal Vg82 supplied to the scanning line 92.

  Specifically, as shown in FIG. 7, the low voltage side (for example, GND level) in AC driving is output as the pixel potential control signal Vcs at time t82. Next, in this state, when the gate drive signal Vg82 as a scanning signal becomes H (high) level (t84 to t86), the pixel transistor 82 becomes conductive (on state), and the signal line passes through the pixel transistor 82. The potential of the pixel signal Vsig supplied to 94 is sampled in the pixel capacitor 86, and the potential Vs82 of the source electrode 82S of the pixel transistor 82 is made substantially the same as the potential of the pixel signal Vsig.

  Next, after the sampling is completed, the gate drive signal Vg82 as the scanning signal is set to the L (low) level (t86). Then, the pixel transistor 82 is turned off (off state), and the pixel electrode 84a is disconnected from the signal line 94 that supplies voltage. The liquid crystal display device displays gradation according to the voltage Va written to the pixel electrode 84a.

  After this sampling is completed, the pixel potential control signal Vcs supplied to the capacitor line 98 connected to the other electrode 86b of the pixel capacitor 86 is further boosted to the high voltage side (for example, the common voltage Vcom) in AC driving (t88). ).

  When the pixel potential control signal Vcs is changed from GND to the common voltage Vcom, the pixel capacitor 86 plays a role of a coupling capacitor, and the potential of the pixel electrode 84a, that is, the source electrode 72S of the pixel transistor 82, according to the fluctuation amplitude of the pixel potential control signal Vcs. Can be raised by the common voltage Vcom. Thus, a positive voltage Va with respect to the common voltage Vcom can be generated in the pixel cell 80.

  Next, when the pixel signal Vsig corresponding to the input video signal after time t90 is in the negative polarity input signal mode, that is, in the negative polarity mode in which the potential Vs32 of the source electrode 32S is negative, the pixel potential control signal Vcs is set to the common voltage. In the state of Vcom, the gate drive signal Vg82 as the scanning signal is set to the H (high) level (t94 to t96).

  Then, the pixel transistor 82 is turned on (on state), and the potential of the pixel signal Vsig supplied to the signal line 94 is sampled in the pixel capacitor 86 via the pixel transistor 82, and the potential of the source electrode 82 s of the pixel transistor 82. Vs82 is made substantially the same as the potential of the pixel signal Vsig (for example, common voltage Vcom−input video signal amplitude Va). As a result, a negative voltage Va with respect to the common voltage Vcom can be generated in the pixel cell 80. At this time, the potential Vs82 applied to the source electrode 82s of the pixel transistor 82 is 2 × Va or more as in the conventional case.

  In this way, by generating positive and negative signals with respect to the common voltage Vcom, it becomes possible to form the peripheral circuit of the liquid crystal cell 84 with a low withstand voltage element, and to reduce the pixel size and the circuit scale of the drive circuit. Can be small.

  That is, the amplitude of the signal line 94 connected to the drain electrode 82d of the pixel transistor 82 can be equal to or less than the common voltage Vcom or the video signal amplitude Va, and the potential Vd82 applied to the drain electrode 82d of the pixel transistor 82 is equal to the common voltage. The pixel transistor 82 can be reduced in size, and the pixel transistor 82 can be reduced in size by lowering the breakdown voltage of the pixel transistor 82. Naturally, since the pixel signal Vsig supplied from the voltage selection circuit (not shown) to the signal line 94 is a signal with a narrow amplitude on the positive polarity side, the voltage selection circuit can also be a low breakdown voltage circuit. Furthermore, if the voltage selection circuit can be driven at a low voltage, the shift register and other peripheral circuits can be low voltage circuits, and the entire liquid crystal display device can be configured with a low voltage circuit.

  However, the potential Vs82 applied to the source electrode 82s of the pixel transistor 82 still needs to be 2 × Va or more as in the conventional case, and (2Va) is provided between the drain electrode 82d and the source electrode 82s of the pixel transistor 82. The voltage in the range of −Vcom) to (−2Va) is applied, and the breakdown voltage between the source and drain of the pixel transistor 82 cannot be lowered.

  In addition, it is necessary to change the drive waveform of the pixel signal Vsig corresponding to the input video signal amplitude Va to “GND + Va” and “common voltage Vcom−Va” according to the AC drive cycle of the pixel potential control signal Vcs. There is a problem that it is essential to develop a dedicated driver IC. A more complicated circuit configuration is required than a driver for inputting the pixel signal Vsig in the driving method of FIG. 5 by inverting the data with respect to the common voltage Vcom.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a new mechanism that can be driven with a low withstand voltage and can reduce the circuit size of the pixel size. For example, a novel pixel cell structure that does not require a special circuit for a driver for supplying a pixel signal to a signal line and a method for driving the same while realizing alternating drive with a low-breakdown-voltage drive circuit. Objective.

  In the semiconductor device driving method according to the present invention, a plurality of cells including switch means and a storage element are arranged on a substrate, and a write electrode formed so as to form a first storage element (write capacitor) And a counter capacitor and a storage capacitor in which one electrode is connected to the write electrode and the other electrode is connected to the output end side of the switch means so as to form a second memory element , The electrode on one side of the storage capacitor in the cell is connected to one write electrode of the write capacitor, the other electrode of the storage capacitor is connected to the switch means, and the input signal is passed through the switch means and the storage capacitor. The corresponding potential is sampled in the write capacitor. Preferably, an AC potential corresponding to the input signal is sampled in the write capacitor.

  More specifically, it is a method for driving a semiconductor device in which a signal supplied via a signal line is written to a memory element by on / off control of the switch means, and the signal is supplied to the signal line and the switch means Is turned on, and the positive polarity signal writing step for writing the signal supplied via the signal line to the first memory element via the holding capacitor and the switch means off while maintaining the signal in the supplied state. A positive signal holding step of holding the signal supplied via the signal line in the first memory element by setting the state is assumed.

  Further, the switch means is temporarily turned on while maintaining the signal in the supply state, and then the signal is supplied via the signal line by keeping the switch means in the on state and making the signal non-supply state. A negative polarity signal writing step for writing a signal having a reverse polarity to the first storage element, and a signal supplied via the signal line by turning off the switch means while maintaining the signal in a non-supply state. And a negative polarity signal holding step for holding a signal having the opposite polarity to the first storage element.

  Moreover, the semiconductor device driving device according to the present invention is a device suitable for carrying out the semiconductor device driving method according to the present invention, and includes a control unit that repeatedly executes the above steps. .

  The semiconductor device according to the present invention is a device to which the driving method of the semiconductor device according to the present invention is applied, and the display function is formed so as to form the composition related to the display function and the first memory element. One electrode is connected to the write electrode, and the other electrode of the switch means is formed so as to form a second memory element, with the write electrode and the counter electrode formed so as to sandwich the composition related to A storage capacitor connected to the output end side, one terminal of the second memory element is connected to a write electrode forming the first memory element, and the other terminal of the second memory element is a switch It was assumed that it was connected to the signal line through the means.

  More specifically, one terminal of the memory element is connected to a voltage supply line for supplying a predetermined voltage via the first switch means, and the other terminal of the memory element is a signal via the second switch means. It shall be connected to the line.

  Further, the invention described in the dependent claims defines a further advantageous specific example of the semiconductor device according to the present invention.

  For example, it is preferable that the control unit for supplying a control signal for ON / OFF control of the switch unit to the switch unit is also an integral configuration further provided on the same substrate.

  Further, it is preferable that the control unit always applies a predetermined fixed voltage to the voltage supply line when performing the on / off control of the switch means according to the above-described steps.

  According to the present invention, the electrode on one side of the storage capacitor in the cell is connected to one write electrode of the write capacitor, the other electrode of the storage capacitor is connected to the switch means, and the switch means and the storage capacitor are connected. Since the potential corresponding to the input signal is sampled in the write capacitor, the potential applied to the cell can be suppressed to the minimum potential corresponding to the input signal, as will be described in detail later. In the conventional configurations of Patent Documents 1 and 2, a voltage that is twice as high as that of the input video signal amplitude Va is required to be approximately the same as the input video signal amplitude Va.

  As a result, the cell can be reduced in size by lowering the withstand voltage of the switch transistor used in the cell, and the withstand voltage of the element used in the signal supply driver can be lowered, and the driving method is also improved. It can be simple, and the overall cost of the apparatus can be reduced.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

<Overall configuration of liquid crystal display device>
FIG. 1 is a diagram showing an outline of the overall configuration of an embodiment of a liquid crystal display device using a liquid crystal cell as an electro-optical element, to which a driving device according to the present invention is applied.

  As shown in FIG. 1, a liquid crystal display device 1 includes a pixel array unit 3, a vertical drive unit 5 as a first control unit, a horizontal drive unit 6 as a second control unit, and a level shifter unit on a substrate 2. (L / S) 7, external connection terminal portions (pad portions) 8, and the like are integrated. That is, peripheral drive circuits such as the vertical drive unit 5, the horizontal drive unit 6, and the level shifter unit 7 are formed on the same substrate 2 as the pixel array unit 3.

  The pixel array unit 3 is driven by the vertical drive unit 5 from both the left and right sides. Various pulse signals are supplied to the terminal portion 8 from a driving IC arranged outside the liquid crystal display device 1.

  As an example, in addition to the shift start pulse IN, necessary pulse signals such as a clock pulse CK and a clock pulse xCK (a logically inverted CK), a standby signal STB (or xSTB obtained by logically inverting STB), an enable pulse EN, etc. Supplied.

  Each terminal of the terminal unit 8 is connected to the vertical driving unit 5 and the horizontal driving unit 6 via the wiring 9. For example, each pulse supplied to the terminal unit 8 is supplied to the vertical driving unit 5 and the horizontal driving unit 6 through a buffer after the voltage level is internally adjusted by the level shifter unit 7.

  In the illustrated example, only the vertical drive unit 5 is interposed via the level shifter unit 7. The vertical drive unit 5 scans the pixel array unit 3 line-sequentially, and the horizontal drive unit 6 writes an image signal in the pixel array unit 3 in synchronization with this.

  Although not shown, the pixel array unit 3 has a panel structure including a pair of substrates 2 and a liquid crystal held between them. For example, pixels including pixel transistors and the like are two-dimensionally arranged in a matrix on a transparent insulating substrate, for example, a first glass substrate (driving side substrate), and scanning lines are wired for each row with respect to this pixel array. In addition, a signal line is wired for each column. The first glass substrate is disposed to face the second glass substrate (opposite side substrate) with a predetermined gap, and is bonded together with a sealant (not shown). Then, the liquid crystal material is sealed in a region inside the position of the sealant.

  In the pixel array section 3, scanning lines (gate lines) 12 and signal lines (data lines) 14 are formed. A pixel electrode and a thin film transistor (TFT) for driving the pixel electrode are formed at the intersection between the two. A pixel cell 30 is composed of a combination of a pixel electrode and a thin film transistor. Further, a precharge line 18 is also formed as a configuration unique to the present embodiment.

  The vertical driving unit 5 sequentially selects each pixel cell 30 via the scanning line 12. The horizontal driving unit 6 writes an image signal to the selected pixel cell 30 via the signal line 14.

  For example, the vertical drive unit 5 includes a combination of logic gates (including latches), and selects each pixel cell 30 of the pixel array unit 3 in units of rows. Although FIG. 1 shows a configuration in which the vertical drive unit 5 is disposed only on one side of the pixel array unit 3, a configuration in which the vertical drive unit 5 is disposed on both the left and right sides with the pixel array unit 3 in between is adopted. Is also possible.

  The horizontal driving unit 6 includes a shift register, a sampling switch (horizontal switch), and the like, and writes a video signal in units of pixels to each pixel cell 30 in a row selected by the vertical driving unit 5.

  In this example, dot sequential driving is described in which a video signal is written to each pixel cell 30 in the selected row in units of pixels. It is also possible to take sequential driving.

<Circuit configuration of pixel cell>
FIG. 2 is a circuit diagram illustrating an example of a circuit configuration of each pixel cell 30 (pixel circuit) included in the pixel array unit 3. As apparent from FIG. 2, the pixel cell 30 has two pixel transistors 32 and 33 of NMOS type configured by, for example, thin film transistors (TFTs), and a pixel electrode 34 a connected to the source electrode 32 S of the pixel transistor 32. The liquid crystal cell 34 and the pixel capacitor 36 which is a storage capacitor for extending the data retention time in parallel with the liquid crystal cell 34 are configured. Here, the liquid crystal cell 34 means a liquid crystal capacitance as a writing capacitance generated between the pixel electrode 34a and a counter electrode 34b formed opposite to the pixel electrode 34a.

  In the pixel transistor 32 that is the first pixel switch, the gate electrode 32G is connected to the first scanning line 12a, and the drain electrode 32D is connected to the precharge line 18 that is a voltage supply line for supplying a predetermined voltage. Has been. A reference voltage (hereinafter also referred to as a precharge voltage Vpc) that is always driven at a fixed voltage is applied to each drain cell 32D when the pixel transistors 32 and 33 are controlled to be turned on / off via the precharge line 18. 30 common is given. The precharge voltage Vpc is, for example, a common voltage similar to the counter electrode 34b of the liquid crystal cell 34.

  Further, the counter electrode 34b of the liquid crystal cell 34 is commonly connected to each pixel cell 30 with respect to a common line (not shown). A common voltage (counter electrode voltage) that is fixedly driven via a common line is applied to the counter electrode 34 b of the liquid crystal cell 34 in common for each pixel cell 70.

  In the pixel capacitor 36, one electrode 36a is connected to the pixel electrode 34a and the source electrode 32S of the pixel transistor 32, and the other electrode 36b is a source electrode 33S that is an output terminal of the pixel transistor 33 that is a second pixel switch. It is connected to the.

  In the pixel transistor 33 that is the second pixel switch, the gate electrode 33G that is the control end is connected to the second scanning line 12b, and the drain electrode 33D that is the input end is connected to the signal line.

  In the pixel cell 30 of the present embodiment having such a configuration, one electrode 36a of the pixel capacitor 36 in the pixel cell 30 is connected to the pixel electrode 34a, and the other electrode 36b is connected to the pixel transistor 33. The video data is sampled in the liquid crystal cell 34 or the pixel capacitor 36 through the pixel transistor 33, and thus the voltage of the pixel electrode 34a is varied.

  For example, the conduction and non-conduction of the pixel transistor 32 is controlled by the gate drive signal Vg32 via the first scanning line 12a connected to the gate electrode 32G. When the gate drive signal Vg32 becomes H (high), the pixel transistor 32 becomes conductive, and the source electrode 32S is connected to the precharge line 18. As a result, the liquid crystal cell 34 and the pixel capacitor 36 are sampled to the precharge voltage Vpc supplied to the precharge line 18 via the pixel transistor 32.

  The conduction and non-conduction of the pixel transistor 33 is controlled by the gate drive signal Vg33 through the second scanning line 12b connected to the gate electrode 33G. When the gate drive signal Vg33 becomes H (high), the pixel transistor 33 becomes conductive, and the source electrode 33S is connected to the signal line. As a result, the liquid crystal cell 34 and the pixel capacitor 36 are sampled to the pixel signal Vsig supplied to the signal line 14 via the pixel transistor 33.

  By the combination of the above operations, the source electrode 32S connected to the pixel electrode 34a is AC driven via the pixel capacitor 36. Hereinafter, the operation will be described in detail.

<Driving method of pixel cell>
FIG. 3 is a timing chart for explaining one method of driving the pixel cell 30 shown in FIG. The period t12 to t22 is in the positive polarity mode in which the potential Vs32 of the source electrode 32S is positive.

<Positive polarity mode; positive polarity signal writing step and positive polarity signal holding step>
As shown in FIG. 3, in the positive polarity mode in which the potential Vs32 of the source electrode 32S is positive, the pixel signal Vsig is first stopped within the active period (t10 to t28) of the input video signal amplitude Va. (The minimum voltage Vmin is supplied to the signal line 14), and both the gate drive signal Vg32 as the first scanning signal and the gate drive signal Vg33 as the second scanning signal are set to the H (high) level (t12).

  Then, the pixel transistors 32 and 33 are both turned on, and the source electrode 32S and one electrode 36a of the pixel capacitor 36 are connected to the precharge line 18 via the pixel transistor 32, whereby the precharge voltage Vpc (here, common) is established. On the other hand, the other electrode 36b of the pixel capacitor 36 is connected to the signal line 14 through the pixel transistor 33 while being sampled to the voltage Vcom), and the pixel signal Vsig (here, the minimum voltage Vmin) is supplied to the signal line 14. ) Is sampled.

  Next, the pixel signal is written and held in the liquid crystal cell 34. However, in this case, the gate drive signal Vg32 is first returned to the L (low) level, and then the gate drive signal Vg33 is returned to the L (low) level. This is because when the gate drive signal Vg32 is later returned to the L level, even if the corner pixel signal is written into the liquid crystal cell 34, a potential change corresponding to the signal appears only on the other electrode 36b side of the pixel capacitor 36. This is because the potential of the pixel electrode 34a cannot be changed.

  That is, first, in a state where the gate drive signal Vg33 as the second scanning signal is maintained at the H (high) level, the gate drive signal Vg32 as the first scanning signal is set to the L (low) level and the input video signal A pixel signal Vsig (minimum voltage Vmin + Va) corresponding to the amplitude Va is supplied (t14).

  As a result, the pixel transistor 32 is turned off, and the liquid crystal cell 34 and the pixel capacitor 36 are sampled to the pixel signal Vsig (minimum voltage Vmin + Va) supplied to the signal line 14 via the pixel transistor 33.

  At this time, since the other electrode 36b of the pixel capacitor 36 changes from the minimum voltage Vmin to “minimum voltage Vmin + Va”, the pixel capacitor 36 serves as a coupling capacitor and the pixel transistor 32 is turned off. According to the fluctuation amplitude (= Va) of the signal Vsig, the potential of the pixel electrode 34a, that is, the potential Vs32 of the source electrode 32S of the pixel transistor 32 can be increased by the input video signal amplitude Va. Therefore, a positive voltage Va can be created in the pixel cell 30 with respect to the common voltage Vcom.

  Next, the first drive signal Vg32 as the first scanning signal is maintained at the L (low) level and the pixel signal Vsig (minimum voltage Vmin + Va) corresponding to the input video signal amplitude Va is supplied. The gate drive signal Vg32 as the scanning signal is set to L (low) level (t16). Thereby, the pixel transistor 33 is turned off. That is, the written positive pixel signal is accumulated as charges in the liquid crystal cell 34 and the pixel capacitor 36, and the projection light reflected on the surface of the pixel electrode is modulated by the liquid crystal in which the charges are accumulated, and display is performed. . This display is maintained until it is rewritten next time.

<Negative polarity mode; negative polarity signal writing step and negative polarity signal holding step>
Next, in the negative polarity mode in which the potential Vs32 of the source electrode 32S has a negative polarity, first, the pixel signal Vsig (minimum voltage Vmin + Va) corresponding to the input video signal amplitude Va is supplied as the first scanning signal. Both the gate drive signal Vg32 and the gate drive signal Vg33 as the second scanning signal are set to the H (high) level (t22).

  Then, both the pixel transistors 32 and 33 become conductive, and the source electrode 32S and one electrode 36a of the pixel capacitor 36 are connected to the precharge line 18 via the pixel transistor 32, whereby the precharge voltage Vpc (here, the common voltage). Vcom), while the other electrode 36b of the pixel capacitor 36 is connected to the signal line 14 via the pixel transistor 33, the pixel signal Vsig (here, the minimum voltage Vmin + Va) supplied to the signal line 14 ) Is sampled.

  Next, in a state where the gate drive signal Vg33 as the second scanning signal is maintained at the H (high) level, the gate drive signal Vg32 as the first scanning signal is set to the L (low) level and the pixel signal Vsig is changed to the pixel signal Vsig. Stop (t24).

  At this time, the minimum voltage Vmin of the pixel signal Vsig is supplied to the signal line 14. Thereby, the pixel transistor 32 is turned off, and the liquid crystal cell 34 and the pixel capacitor 36 are sampled to the pixel signal Vsig (minimum voltage Vmin) supplied to the signal line 14 via the pixel transistor 33.

  At this time, since the other electrode 36b of the pixel capacitor 36 changes from “minimum voltage Vmin + Va” to the minimum voltage Vmin, the pixel capacitor 36 serves as a coupling capacitor and the pixel transistor 32 is turned off. According to the fluctuation amplitude (= Va) of the pixel signal Vsig, the potential of the pixel electrode 34a, that is, the potential Vs32 of the source electrode 32S of the pixel transistor 32 can be lowered by the input video signal amplitude Va. Therefore, a negative voltage Va with respect to the common voltage Vcom can be generated in the pixel cell 30.

  When writing of the negative voltage into the pixel cell 30 (the liquid crystal cell 34 and the pixel capacitor 36) is completed, both the gate drive signal Vg32 as the first scan signal and the gate drive signal Vg33 as the second scan signal are set to L. The input video signal amplitude Va may be stopped while maintaining the (low) level (t28). The written negative pixel signal is accumulated as a charge in the liquid crystal cell 34 and the pixel capacitor 36, and the projection light reflected on the surface of the pixel electrode is modulated by the liquid crystal in which the charge is accumulated, and display is performed. This display is maintained until it is rewritten next time.

  In this way, by generating positive and negative signals with respect to the common voltage Vcom, it becomes possible to form the peripheral circuit of the liquid crystal cell 34 with a low withstand voltage element, and to reduce the pixel size and the circuit scale of the drive circuit. Can be small.

  For example, when the amplitude of the input video signal is Va, the potential of the precharge line 18 connected to the drain electrode 82d of the pixel transistor 32 can be fixed to the common voltage Vcom, and the drain electrode 32d and the source electrode 32s. The potential difference VDS can be suppressed to the range of (+ Va) to (−Va). In this way, the breakdown voltage between the source and drain of the pixel transistor 32 can be reduced by half, and the pixel transistor 32 itself can be downsized.

  Similarly, since only the maximum voltage of the input video signal amplitude Va is applied to the drain electrode 33D and the source electrode 33S of the pixel transistor 33, it can swing only at the input video signal amplitude Va, and 2 × Va volt is required. Therefore, the breakdown voltage of the pixel transistor 33 can be lowered.

  That is, with the configuration of the pixel cell 30 according to the present embodiment, although the number of elements of the pixel switch increases, the potential applied to the pixel cell can be minimized, and both can be low breakdown voltage elements. As a whole, the pixel cell size can be reduced. Even if the definition is increased and the number of pixels is increased, the chip size is not increased, and the price increase of the semiconductor substrate chip, the liquid crystal display device, and the image display device can be suppressed.

  Furthermore, in the configuration of the pixel cell 30 of the present embodiment, the pixel signal Vsig supplied from the voltage selection circuit (not shown) to the signal line 14 may be shaken with the input video signal amplitude Va, and the voltage selection circuit is also a low withstand voltage circuit. can do. Furthermore, if the voltage selection circuit can be driven at a low voltage, the shift register and other peripheral circuits can be low voltage circuits, and the entire liquid crystal display device can be configured with a low voltage circuit.

  In addition, unlike the driving method described in Patent Document 2, it is not necessary to invert the driving waveform of the pixel signal Vsig corresponding to the input video signal in accordance with the AC driving in order to AC drive the pixel electrode 34a. A general-purpose LCD driver can be used for driving. Further, even when a new LCD driver is developed, a normal LCD driver can be reduced in voltage (downsized), and the cost of the entire liquid crystal display device can be reduced.

  The video signal driver itself can also be reduced in voltage = lower withstand voltage (= lower price) with a simple function, and the cost of the liquid crystal display device and the image display device can be reduced.

  Therefore, in addition to reducing the pixel cell size by lowering the breakdown voltage of the pixel switch transistor used in the pixel cell, the breakdown voltage of the element used in the video signal supply driver can also be reduced. The driving method may be simple, and can have a great effect not only on the liquid crystal display substrate but also on the cost reduction of the entire apparatus.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. Various changes or improvements can be added to the above-described embodiment without departing from the gist of the invention, and embodiments to which such changes or improvements are added are also included in the technical scope of the present invention.

  Further, the above embodiments do not limit the invention according to the claims (claims), and all combinations of features described in the embodiments are not necessarily essential to the solution means of the invention. Absent. The embodiments described above include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. Even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, as long as an effect is obtained, a configuration from which these some constituent requirements are deleted can be extracted as an invention.

  For example, in the above embodiment, the pixel switch is only NMOS, but it may be composed only of PMOS or a combination of NMOS and PMOS, both of which can achieve the same effect as above. .

  In the above-described embodiment, the driving device configured by the vertical driving unit 5 and the horizontal driving unit 6 and other peripheral function units of the pixel array unit 3 is integrally formed on the substrate 2 together with the pixel array unit 3. However, the driving device and the pixel array unit 3 may be configured on different substrates.

It is a figure which shows the outline of the whole structure of one Embodiment of the liquid crystal display device to which the drive device which concerns on this invention is applied. It is a circuit diagram which shows an example of the circuit structure of each pixel cell which comprises a pixel array part. 3 is a timing chart for explaining one method for driving the pixel cell shown in FIG. 2. It is a figure which shows the equivalent circuit of a general pixel cell. 5 is a timing chart for explaining one method for driving the pixel cell shown in FIG. 4. It is a figure which shows the equivalent circuit of the pixel cell made into the structure which carries out alternating current drive of the terminal of the one side of a pixel capacity | capacitance. 7 is a timing chart for explaining one method for driving the pixel cell shown in FIG. 6.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Liquid crystal display device, 2 ... Substrate, 3 ... Pixel array part, 5 ... Vertical drive part, 6 ... Horizontal drive part, 7 ... Level shifter part, 8 ... Terminal part, 12, 12a, 12b ... Scanning line, 14 ... Signal 18 ... Precharge line, 30 ... Pixel cell 30, 32, 33 ... Pixel transistor, 34 ... Liquid crystal cell, 34a ... Pixel electrode, 34b ... Counter electrode, 36 ... Pixel capacitance, 36a, 35b ... Electrode

Claims (11)

A semiconductor device in which a plurality of cells including a switch unit and a storage element are arranged on a substrate, and a signal supplied via a signal line is written to the storage element by on / off control of the switch unit,
A composition related to the display function;
A first storage element, a write capacitor having a write electrode and a counter electrode formed so as to sandwich the composition related to the display function;
A second storage element, wherein one electrode is connected to the write electrode and the other electrode is connected to the output end side of the switch means;
One electrode of the storage capacitor is connected to the write electrode that forms the write capacitor;
The other electrode of the second memory element is connected to the signal line through the switch means. A semiconductor device, wherein: 2. The semiconductor device according to claim 1, further comprising a control unit on the substrate for supplying a control signal for on / off control of the switch unit to the switch unit. By setting the signal to a supply state and turning on the switch means, a signal supplied via the signal line is written to the first storage element via the storage capacitor,
By turning off the switch means while maintaining the signal in the supply state, the signal supplied through the signal line is held in the first storage element,
The switch means is temporarily turned on while maintaining the signal in the supply state, and then the signal is not supplied while the switch means is maintained in the on state. A signal having a polarity opposite to that of the signal supplied to the first memory element,
The first memory element is configured to hold a signal having a polarity opposite to that of the signal supplied via the signal line by turning off the switch unit while maintaining the signal in a non-supply state. The semiconductor device according to claim 2, wherein the control unit performs control. A semiconductor device in which a plurality of cells including a switch unit and a storage element are arranged on a substrate, and a signal supplied via a signal line is written to the storage element by on / off control of the switch unit,
One electrode of the memory element is connected to a voltage supply line for supplying a predetermined voltage via the first switch means,
The other electrode of the memory element is connected to the signal line through the second switch means. A semiconductor device, wherein: A composition related to the display function;
A first storage element, a write capacitor having a write electrode and a counter electrode formed so as to sandwich the composition related to the display function;
And a storage capacitor having one electrode connected to the write electrode and the other electrode connected to the output end of the switch means. The semiconductor device according to claim 4. A first control unit that supplies each control signal to the switch means to control on / off of the first switch means and the second switch means;
A second control unit configured to apply a predetermined voltage corresponding to the signal to the signal line in accordance with an on / off state of the first switch unit and the second switch unit; The semiconductor device according to claim 4. While the signal is not supplied, both the first switch means and the second switch means are turned on,
Next, the signal supplied through the signal line by turning the first switch means off while keeping the second switch means on and setting the signal to the supply state. To the storage element,
Next, the signal supplied via the signal line is changed by turning the second switch means off while keeping the first switch means off while keeping the signal supplied. The semiconductor device according to claim 6, wherein the first control unit and the second control unit perform control in cooperation with each other so as to be held in the storage element. While the signal supplied through the signal line is held in the storage element, the first switch unit and the second switch unit are both turned on while the signal is being supplied.
Next, while maintaining the second switch means in the on state, the signal is not supplied, and the first switch means is turned off to supply the signal via the signal line. A signal having a polarity opposite to that of the signal is written to the memory element;
Next, the signal supplied through the signal line is set by turning off the second switch means while keeping the first switch means off while keeping the signal non-supplied. The semiconductor device according to claim 7, wherein a signal having a polarity opposite to that of the storage element is held in the storage element. 5. The semiconductor device according to claim 4, wherein a predetermined fixed voltage is constantly applied to the voltage supply line when the first switch unit and the second switch unit are on / off controlled. 6. . A plurality of cells including a switch means and a storage element are arranged on the substrate, so as to form a write electrode and a counter electrode formed to form the first storage element, and a second storage element In addition, in a semiconductor device including one electrode connected to the write electrode and the other electrode connected to the output end side of the switch means, on / off control of the switch means, A driving method of a semiconductor device for writing a signal supplied via a signal line to the memory element,
A positive signal writing step of writing a signal supplied via the signal line to the first storage element via the storage capacitor by setting the signal to a supply state and turning on the switch means; ,
A positive signal holding step of holding the signal supplied via the signal line in the first storage element by turning off the switch means while maintaining the signal in the supply state;
The switch means is temporarily turned on while maintaining the signal in the supply state, and then the signal is not supplied while the switch means is maintained in the on state. A negative polarity signal writing step of writing a signal having a polarity opposite to that of the signal supplied to the first storage element;
A negative polarity signal that causes the first memory element to hold a signal having a polarity opposite to that of the signal supplied through the signal line by turning off the switch means while maintaining the signal in a non-supply state. A method for driving a semiconductor device, comprising: a holding step. A plurality of cells including a switch means and a storage element are arranged on the substrate, so as to form a write electrode and a counter electrode formed to form the first storage element, and a second storage element And a driving device for driving a semiconductor device including a storage capacitor having one electrode connected to the write electrode and the other electrode connected to the output end of the switch means,
By setting the signal to a supply state and turning on the switch means, a signal supplied via the signal line is written to the first storage element via the storage capacitor,
By turning off the switch means while maintaining the signal in the supply state, the signal supplied through the signal line is held in the first storage element,
The switch means is temporarily turned on while maintaining the signal in the supply state, and then the signal is not supplied while the switch means is maintained in the on state. A signal having a polarity opposite to that of the signal supplied to the first memory element,
A controller that holds a signal having a polarity opposite to that of the signal supplied via the signal line in the first storage element by turning off the switch unit while maintaining the signal in a non-supply state; A drive device for a semiconductor device, comprising:

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