JPH0824359B2 - Active matrix image display device - Google Patents

Description

The present invention relates to an active matrix type display device having pixels each composed of switching elements arranged in a matrix and display elements such as liquid crystals.

[Conventional technology]

A color television image display device having a screen size of about 6 or more requires a particularly high resolution. Therefore, for example, when an NTSC image signal is input, it is necessary to display about 480 effective horizontal scanning lines. The matrix type television image display device requires about 480 vertical pixels. NTS
For C type image signals are interlaced signal of a frame period 30H _z, 1 in each pixel one frame and using the conventional driving method only the pixels of one row in one horizontal scanning period is not selected
It is selected once and driven by the image signal corresponding to the pixel. Here, for example, when a liquid crystal element is used as a display element, it is necessary to perform AC driving from the viewpoint of the life thereof, and therefore the polarity of the image signal is inverted for each frame for driving. frequency is halved frame frequency 15H _z. When driving the liquid crystal element at an alternating voltage of 15H _z, since it is often the frequency is the flicker due to low occurs, it is necessary to ensure at least 30H _z as alternating frequency of the liquid crystal. Therefore, each pixel is not selected once in one frame but twice, that is, one in one field (one frame is composed of two fields).
It may be selected once, and the polarity of the image signal may be inverted for each field for driving. However, the number of effective horizontal scanning lines in one field is approximately 240, and when driving a liquid crystal panel having approximately 480 vertical pixels, it is necessary to selectively drive pixels in two rows in one horizontal scanning period. Thus once all the pixels selected drive in one field by selectively driving pixel of the second row in one horizontal scanning period, the liquid crystal alternating frequency method and 30H _z, Electronics and Communication Engineers Technical Report 84, Vol 159 Issue (Showa 59
Year) Page 19 to 24.

[Problems to be solved by the invention]

In the above-mentioned conventional technology, an A / D converter, digital memory, D
The / A converter was used to digitally process the so-called double speed conversion of the interlaced TV image signal, and the non-interlaced signal was obtained and input to the horizontal scanning circuit to drive the liquid crystal panel. Therefore, it is necessary to increase the speed of the horizontal scanning circuit as compared with the case where one row of pixels is driven in one horizontal scanning period, and a digital double speed conversion circuit that increases the circuit scale is required.

An object of the present invention is to increase the speed of a horizontal scanning circuit and to use a digital double speed conversion circuit,
An object is to obtain an active matrix type liquid crystal image display device which drives pixels in two rows during one horizontal scanning period to reduce flicker and has a long life.

[Means for solving problems]

The object is to provide a plurality of television image signal sample and hold circuits for one column signal electrode drive circuit, to perform sampling operation of two sample and hold circuits for each drive circuit during a horizontal effective display period of a television image signal, and This is achieved by switching and outputting the signal voltage held by the sample hold circuit 2 times twice in one horizontal period and driving the column signal electrodes of the active matrix type liquid crystal panel.

[Action]

During one horizontal scanning period, two different signal voltages sampled in the previous horizontal scanning period are dividedly output twice to drive the column signal electrodes of the active matrix type liquid crystal panel, so that two rows of pixels are driven. The liquid crystal panel is driven by a so-called non-interlaced double speed image signal. Whereby (if e.g. NTSC television image signal is input, the 30H _z.) LCD alternative frequency is the frame frequency becomes equal and, without the use of digital double speed conversion circuit, flicker less, also a long life Can be obtained.

〔Example〕

 Embodiments of the present invention will be described below with reference to the drawings.

1 is a configuration diagram showing a first embodiment of a double speed line sequential scanning circuit used in an active matrix type display device according to the present invention, and FIG. 2 is an operation waveform diagram of the circuit of FIG. Is a shift register for horizontal scanning, 2 is AND (AN
D) circuit, 3 is a level shifter, 4 is a shift matrix,
5 is a hold capacitor, 6 is a voltage follower, 7 is a buffer amplifier, 8 is a vertical scanning shift register, 9 is a color liquid crystal panel in which three primary color filters are arranged in an oblique mosaic pattern, 10 is a MOS transistor, 11 is a liquid crystal cell, D _r is a column signal electrode, Ga is a row scanning electrode, and _Wij , _Sij (i = A, B, C, D, j = 1,
2, 3, ...) are analog switches composed of, for example, MOS transistors.

In FIG. 1, the horizontal scanning shift register 1 includes
The liquid crystal panel 9 is synchronized with the horizontal synchronizing signal of the television image signal.
Clock pulses φ _H corresponding to the number of horizontal pixels of
A scan start signal D _H obtained by delaying the horizontal synchronization signal is applied. The output of each stage of the shift register 1 is input to the AND circuit 2 together with the signals H ₁ and H ₂ whose logical levels are inverted in each horizontal scanning cycle.
A signal for sequentially selecting once every two horizontal scanning periods is formed, and the level shifter 3 generates an analog switch _Wij (i = A, B, C, D, j).
= 1,2,3, ...) is converted to a driveable voltage level.
The analog switch Wij forms a sample-hold circuit together with the hold capacitor 5, and each sample-hold circuit has a TV image signal X _R , X _G , once every two horizontal scanning periods.
X _B is sequentially sampled, and the hold capacitor 5 holds the signal voltage corresponding to the column signal electrode D _r in charge of driving. This held signal voltage is applied to the selected analog switch S _ij (i = A, B, C, D, j = 1,2,3, ...) Through the high input impedance voltage follower 6.
The held signal voltage is switched by the control signals H _A , H _B , H _C , and H _D every half period of the horizontal scanning period and input to the buffer amplifier 7, and the output drives the column signal electrode _Dr. Is. If the output impedance of the voltage follower 6 and the on resistance of the analog switch S _ij are sufficiently low, the buffer amplifier 7 may be omitted.

Next, a clock pulse φ _V having a frequency twice the horizontal scanning frequency and a vertical scanning start signal D _V obtained by delaying the vertical synchronizing signal are applied to the vertical scanning shift register 8 to horizontally scan the television. Turn on the MOS transistor 10 whose gate is connected to the row scanning electrode Ga corresponding to the line,
An image is displayed by applying a signal voltage applied to the column signal electrode D _r to the liquid crystal cell 11. When the liquid crystal itself and the leakage when the MOS transistor 10 is off cannot be ignored, a signal holding capacitor may be added to the liquid crystal drive electrode of each pixel.

Further, one of the electrodes of all the liquid crystal cells is connected in common, and an almost midpoint potential of the signal voltage is applied to drive the liquid crystal with an alternating current.

The operation described so far is k (= 3j−2; j = 1,2,
The driving circuit for the column signal electrodes D _r -k in the (3, ...) Column will be taken up and the driving signal will be further described in detail with reference to FIG. Column signal electrode D _r of the k + 1, k + 2nd column
Regarding the drive circuits of −k + 1 and D _r −k + 2, (Red, Gre, Blu, R, G, B) will be replaced by (Gre, Bl) in the following description.
u, Red, G, B, R) and (Blu, Red, Gre, B, R, G), the same operation will be performed, and description thereof will be omitted.

Here, a sample hold circuit composed of the analog switches W _Ak , W _Bk , W _Ck , W _Dk and each hold capacitor 5 is respectively
S / H-A, S / H-B, S / H-C, S / H-D will be referred to as the sampling operation period "W", and the selection switches S _Ak , S _Bk , S _Ck ,
S _Dk is selected and sent to the buffer amplifier 7,
The output period for driving the column signal electrodes D _r −k is shown with the symbol “R”. In addition, in () following the sampling period “W”, the three primary color signals Red (Gre), Gre (Green), and Blu (Blue) sampled by each sample and hold circuit are shown.
Indicates the type of. After the output period “R”, the color R (red), G (green), B displayed by the driven pixel is shown in ().
(Blue) and a subscript indicating the number of the row scanning electrode to which the pixel belongs are written.

The shift matrix circuit 4 which receives the three primary color image signals Red, Gre, and Blu in the first horizontal scanning cycle of the first field inputs the signals of Red, Gre, and Blu to the signal lines of X _R , X _G , and X _B , respectively. Output a signal. At this time, S / H-
A and B sample Red and Blu respectively. At this time, the sample-and-hold circuit having a small k number samples near the beginning of the effective display period, and the sample-and-hold circuit having a large k number samples near the end of the effective display period. This also applies to the sampling period described below.

Followed in the first half of the second horizontal scanning period, at the same time when the first row scan electrode Ga-1 is selected, S / H-A from the first row of the signal R ₁ commensurate with pixel column signal electrodes D _r -k Added to. In the latter half of the second horizontal scanning cycle, the second row scanning electrode Ga−
At the same time when 2 is selected, a signal B ₂ corresponding to the pixel on the second row from S / H-B is applied to the column signal electrode D _r -k. In the second horizontal scanning period, the shift matrix circuit 4 outputs Gre, Blu, and Red signals to the X _R , X _G , and X _B signal lines, respectively, and the S / H signal is output during the effective display period. -C and D sample Gre and Red respectively.

In the first half of the third horizontal scanning period, the third row scanning electrodes Ga
At the same time as -3 is selected, a signal G ₃ corresponding to the pixel on the third row from S / H-C is applied to the column signal electrode D _r -k. In the latter half, at the same time when the fourth row scanning electrode Ga-4 is selected, S /
The signal R ₄ corresponding to the pixel on the fourth row from HD is the column signal electrode D
added to _r- k. Further, in the third horizontal scanning period, the shift matrix circuit 4 outputs signals of Blu, Red and Gre to the signal lines of X _R , X _G and X _B , respectively, and S / H is output during the effective display period. -A and B sample Blu, Gre respectively.

Hereinafter, the same operation is repeated, and when the number of pixels in the vertical direction is, for example, 480 pixels, three primary color image signals are sampled during 240 horizontal scanning cycles, and all the pixels are sampled once during the 241st horizontal scanning cycle. They will be selectively driven one by one.

Assuming that an interlaced NTSC image signal is used as a television image signal, one field is composed of 262.5 horizontal scanning periods. Therefore, the display with the image signal of the 263rd horizontal scanning cycle is positioned higher than the display with the image signal of the first horizontal scanning cycle, and the display with the image signal of the 264th horizontal scanning cycle is the image with the first horizontal scanning cycle. It should be below the signal display. In consideration of this relationship, in the second field, only the pixels in the first row are driven by the image signal in the 263rd horizontal scanning cycle, and the pixels in the second row and the third row are driven by the image signal in the 264th horizontal scanning cycle. I am trying. Therefore, during the 263rd horizontal scanning period, the S / H-A is the image signal.
The signal obtained by sampling Gre is not applied to the pixel. This is shown as R (X) in FIG.

In this way, through the 1st and 2nd fields,
All pixels are selectively driven twice within four horizontal scanning cycles. Therefore, the first field giving for example, a positive polarity image signal, by previously giving a negative image signal of the second field, the driving voltage of the liquid crystal cell 11 AC 2 field period or frame period (30H _z) Will be driven.

In FIG. 1, it is considered that about 648 are required for the screen size of the liquid crystal panel 9 having about 6 horizontal pixels. At this time, the frequency _H required for the shift clock φ _H of the horizontal scanning shift register 1 is, for example, , NTSC TV image signal is calculated as follows.

As described above, it is considered that the shift register 1 is required to operate at high speed and consumes a large amount of power. With this in mind, and the frequency of the shift clock 1/3 (4.1MH _z) 3
Third example of configuration of dynamic shift register with reset terminal ( _RS ) using phase clocks φ _H1 , φ _H2 , and φ _H3
FIG. 4 shows an example of its operation waveform. Reference numeral 21 is an analog switch, which has a CMOS configuration here. Reference numeral 22 is a hold capacitor that holds the signal voltage immediately before it is turned off when the analog switch is off, and may be replaced with a parasitic capacitance. 23 is a non-inverting buffer,
For example, two inverters are connected in series. Reference numeral 24 denotes a resetting NMOS transistor, which gives "H" level to the reset terminal R _S to output the shift register output when the three-phase clocks φ _H1 , φ _H2 , and φ _H3 are not given for a long period such as a blanking period. It works to keep stable non-selected state. The horizontal scanning shift register of FIG. 1 has, for example, 64 output stages.
In the case of 8, the circuit scale and power consumption can be reduced by using the circuit of FIG. 3 connected in cascade with 648/3 = 216 circuits. The circuit example shown in FIG. 3 can be applied to the shift register according to another embodiment of the present invention described below.

In addition, as the horizontal scanning shift register of FIG.
When the number of output stages is, for example, 648, a circuit having three normal 1-clock input 216-stage shift registers may be used. In this case, the output waveforms shown in FIG. 4 can be obtained by using three-phase clocks having different phases for the clocks of the three systems of shift registers.

FIG. 5 is an example of a circuit for forming signals to be applied to the control terminals H ₁ , H ₂ , H _A , H _B , H _C , and H _D of FIG. 25 is a quaternary counter and 26 is a 2 to 4 decoder. To the quaternary counter 25,
Given the horizontal scanning of half the period of the periodic clock H / 2 (e.g., may be replaced by a clock phi _V of the vertical scanning shift register.), The upper bits Q ₁ is a signal that is inverted every horizontal scanning period And at the same time its inverted signal Q ₁ is obtained. These signals are exactly the signals required by H ₁ and H ₂ in FIG. The signals O ₀ , O ₁ , O ₂ , O ₃ obtained by adding the output of the quaternary counter 25 to the 2 to 4 decoder 26 are signals which are sequentially selected every half of the horizontal scanning period. , And referring to the operation waveforms in FIG. 2,
It can be seen that the signals are necessary for the terminals H _C , H _D , H _A and H _B in the figure. It is necessary to add a signal R _V synchronized with the vertical synchronizing signal to the reset terminal R of the quaternary counter 25 in order to synchronize with the vertical scanning shift register. When the double speed sequential scanning circuit of FIG. 1 is integrated into an IC, the number of input terminals can be reduced by incorporating the control circuit of FIG.

Another embodiment of the present invention is shown in FIG. 6 and its operation waveform is shown in FIG. A big difference from FIG. 1 is that the number of sample and hold circuits per column signal electrode drive circuit is reduced from four to three, and instead of the buffer amplifier 7, a buffer amplifier with output control 12 capable of putting the output in a high impedance state.
Is used to connect the hold capacitor 13 to the column signal electrode D _r . Incidentally, when the leakage of the column signal electrodes D _r is small, it may be able to use the stray capacitance as the hold capacitor 13.

As can be seen by comparing the operation waveform examples of FIGS. 2 and 7, it can be seen that S / H-A of FIG. 7 also performs the operations of S / H-A and C of FIG. . Therefore, in the embodiment of FIG. 6, the sample hold circuit corresponding to S / H-C can be omitted. However, in FIG. 7, S / H-A
Must always be sampled during the horizontal effective display signal period, so that the output period from the sample hold circuit must be within the horizontal blanking period, and the output period is shorter than that in FIG. Therefore, the output control buffer amplifier 12 is used to drive the column signal electrode D _r by operating the buffer amplifier only for the time corresponding to the horizontal blanking period, and the column signal electrode D _r is connected for the remaining period. The hold capacitor 13 holds the signal voltage. S / H-
Although there is no limitation on the output time for B and C, the same output time as S / H-A is used in consideration of variations in driving voltage.

In the embodiment shown in FIG. 1, the buffer amplifier 7 is described as always operating, but a buffer amplifier with output control as shown in FIG. 6 may be used. If the output impedance of the ball follower 6 and the on resistance of the analog switch S are sufficiently low, the same operation can be achieved even if the output control buffer amplifier 12 is omitted.

As described above, according to the embodiment of FIG. 6, the number of sample hold circuits can be reduced to 3/4 of that of the embodiment of FIG. 1, so that the double speed line sequential scanning circuit scale can be reduced. There is.

FIG. 8 shows another embodiment of the present invention. Similar to the embodiment of FIG. 6, a sample hold circuit 3 for one column signal electrode
3 uses three buffer amplifiers 12 with output control, but a big difference is that the shift matrix 4 used in the embodiments of FIGS. 1 and 6 is omitted. In addition, the AND circuit 2 that determines the sampling period of the sample hold circuits of the three systems is provided for each, and the sample hold circuit and the three primary color image signals Re
The difference is the order of connection with d, Gre, and Blu.
Next, the operation of the embodiment shown in FIG. 8 will be described below with reference to the operation waveform example shown in FIG.

Looking at the operation waveform example in FIG. 9, compared with FIGS. 2 and 7, the three primary color image signals handled by each sample and hold circuit S / H-A, B, C are fixed to Red, Blu, Gre respectively. There is a feature in doing it. For this reason, the shift matrix circuit can be omitted, as described at the beginning in the description of the embodiment of FIG.
Since the other operations are almost the same as those of the embodiment shown in FIG. 6, their explanations are omitted.

FIG. 10, the control terminals H ₁ of FIG. _{6, H 2, H A, H} B, which is a circuit example for forming a signal to be supplied to the H _D. As in the circuit example of FIG. 5, the clock H / 2 of half the horizontal scanning period is set to 4
It is input to the binary counter 25 and forms the control signals H ₁ and H ₂ . On the other hand, regarding the control signals H _A , H _B , and H _D , S / H− in FIG.
A selection pulse corresponding to the "R" portion of the operation waveform of A, B, D is required, but the output of the quaternary counter 25 and the output control signal OE
Is input to the AND circuit 27 to obtain a necessary control signal.

FIG. 11 is an example of a circuit for forming signals to be applied to the control terminals H ₁ , H ₂ , H ₃ , H _A , H _B and H _C of FIG. Fig. 5 and 10
A hexadecimal counter 28 is used instead of the quaternary counter used in the circuit example in the figure. This can be easily inferred from the fact that the operation waveform example of FIG. 9 shows that the same operation is repeated every three horizontal scanning periods (that is, six clocks of clock H / 2). The upper 2 bits of the hexadecimal counter 28 are input to the 2 to 4 decoder 26, the output thereof is inverted by the inverter 29, and the "W" portion of the operation waveforms of S / H-A, B and C in FIG. The respective selection control signals H ₁ , H ₂ , and H ₃ are obtained. Also, the control signal
H _A , H _B , H _C are output of the hexadecimal counter 28 as selection pulses corresponding to the "R" portion of the operation waveforms of S / H-A, B, C in FIG.
It is obtained by inputting the output of the 2 to 4 decoder 26 and the output control signal to the AND-OR circuit 30.

When the double speed line sequential scanning circuit according to the embodiment of the present invention shown in FIGS. 6 and 8 is integrated into an IC, the number of input terminals can be reduced by incorporating the control circuit shown in FIGS. 10 and 11. effective.

The case where the color liquid crystal panel in which the three primary color filters are arranged in a diagonal mosaic pattern is driven has been described above as an example, but the present invention can be applied to other color filter arrangements. For example, set the color filter arrangement on the adjacent row to 1.5.
12th even in the case of triangle arrangement with pixel shift
It can be configured as in the illustrated embodiment of the invention. The operation of the embodiment shown in FIG. 12 is almost the same as the operation of the embodiment shown in FIG.

In the above embodiments, when there is a leak of pixel switching elements arranged in a matrix in the active matrix display device, there is a possibility that uneven brightness in the vertical direction of the display screen may occur. This is because, as shown in the operation waveform in FIG. 24, for example, all pixel display image signals of positive polarity in the even field and negative polarity in the odd field are supplied to the column signal electrodes D _r.
Applied to the gate path Ga-1 of the first row, the pixel connected to the liquid crystal cell capacitance V _LCD-1 almost at the beginning of the even field.
Since the positive polarity signal voltage is written and held in the pixel switching element, the voltage across the pixel switching element (potential difference between D _r and V _{LCD-1 in FIG} . 24) becomes almost 0.
The pixel connected to is written with a positive polarity signal voltage in the liquid crystal cell capacitance V _LCD-480 almost at the end of the even field and held for most of the offset field, so the voltage applied across the pixel switching element (see Fig. 24). At D _r and V _LCD-480 potential difference)
Therefore, if all the pixels are driven by the same image signal voltage, the leak of the signal voltage held in the liquid crystal cell becomes larger toward the lower part on the screen.

Another embodiment of the present invention in consideration of this point is shown in FIG. The embodiment of FIG. 13 is a configuration diagram showing a double speed line sequential scanning circuit for driving an active matrix type liquid crystal panel 91 in which color filters are arranged in a vertical stripe pattern, and in particular,
The polarity of the signal applied to the drain bus can be inverted for each row selection.

In FIG. 13, the horizontal scanning shift register 1 includes
The liquid crystal panel 91 is synchronized with the horizontal synchronizing signal of the television image signal.
A clock panel φ _H corresponding to the number of horizontal pixels of
A scan start signal D _H obtained by delaying the horizontal synchronization signal is applied. The output of each stage of the shift register 1 is input to the logical product (AND) circuit 2 together with the signals H ₁ and H ₂ whose logical levels are inverted with each other, which are switched every horizontal scanning period.
A signal for sequentially selecting once every two horizontal scanning periods is formed and input to the level shifter 3 together with the output of each stage of the shift register 1, and the analog switch W _ij (i = A, B, C, j = 1, 2, 3,
...) drive. The analog switch W _ij forms a sample and hold circuit together with the hold capacitor 5. The sample and hold circuit including the analog switch W _Aj is once in one horizontal scanning period, and the sample and hold circuit including the analog switches W _Bj and W _Cj is 2. During the horizontal scanning period, the TV image signals R +, R-, etc. are sequentially sampled once, and the hold capacity 5
The signal voltage corresponding to the column signal electrode D _r responsible for driving is held. This held signal voltage is applied to the selected analog switch S _ij (i = A, B, C, j = 1,2,3, ...) Through the high input impedance voltage follower 6, and the held signal voltage is adjusted appropriately. Control signal
Buffer amplifier with output control 12 switched by H _A , H _B , H _C
To drive the column signal electrode D _r . If the output impedance of the voltage follower 6 and the on resistance of the analog switch S _ij are sufficiently low,
It does not matter if the buffer amplifier 7 is omitted.

The operation described so far is k (= 3j−2; j = 1,2,3,
…) Taking up the drive circuit of the column signal voltage D _r −k in the column,
A more specific description will be given using the operation waveform diagram of FIG. k
The driving circuit for the column signal electrodes D _r −k + 1 and D _r −k + 2 in the +1 and k + 2th column has the same operation if R is replaced with G and B in the following description, and thus the description thereof is omitted.

In FIG. 14, the three primary color signals R + (red positive polarity), R- (red negative polarity), G + (green positive polarity) sampled by each sample and hold circuit are shown in parentheses () following the sampling period "W". ), G- (green negative polarity), B +
(Blue positive polarity) and B- (blue negative polarity) are shown. In the parentheses following the output period "R", the subscripts indicating the colors R (red), G (green), B (blue) displayed by the driven pixel and the row scan electrode number to which the pixel belongs are entered. are doing.

In the first horizontal scanning period of the first field, S / H-A and B sample R + and R- during the effective display period. At this time, the sample-and-hold circuit having a small k number samples near the beginning of the effective display period, and the sample-and-hold circuit having a large k number samples near the end of the effective display period. This also applies to the sampling period described below.

In the subsequent blanking period of the first horizontal scanning period, the first row scanning electrode Ga-1 is selected, and at the same time, the signal R ₁ (R +) corresponding to the pixel on the first row is output from the S / H-A to the buffer amplifier 12 After being added to the column signal electrode D _r −k through the output of the buffer amplifier 12, the output of the buffer amplifier 12 becomes a high impedance state,
The pixel signal is held until D _r -k is driven next time, and the signal is written in the liquid crystal cell on the first row.

In the effective display period of the second horizontal scanning period, the S / H-A for which the read operation has finished and the waiting S / H-C sample R + and R-, respectively. Also, from an appropriate time during this effective display period (for example, a time that is half the horizontal scanning period before the last time of the effective display period),
The first row scanning electrode Ga-1 becomes non-selected and the second row scanning electrode Ga-1
-2 is selected, and the signal R corresponding to the pixel on the second row from S / H-B that has held the pixel signal until then is selected.
₂ (R−) passes through the buffer amplifier 12 and the column signal electrode D _r −
After a predetermined time (for example, a horizontal retrace time) to k, the output of the buffer amplifier 12 becomes the high impedance state again, and the pixel signal is held until the next driving, and the liquid crystal cell in the second row is held. The navel signal is written.

During the blanking period of the subsequent second horizontal scanning cycle, the second row scanning electrode Ga-2 is deselected, the third row scanning electrode is selected, and the signal R corresponding to the pixel on the third row from S / H-A is selected.
₃ (R +) is read out to the column signal electrodes D _r -k, the liquid crystal cell of the third row are driven.

The same operation is repeated thereafter, and S / H-A and B are set to R + and R- respectively during the effective display period of the odd scan cycle and S / H-A and C are set to the effective display period of the even scan cycle. sampling, during retrace period for driving the column signal electrodes D _r -k read pixel signals are hold S / H-a (red positive polarity). Each predetermined time period S / H-C, and S / H-B sequence reads the pixel signals are held (red negative) signal electrodes D _r of preferred numbers and during the effective display period of the even-number scan period
-Drive k. Therefore, the column signal electrodes D _r -k will be driven by an alternating current waveform of the horizontal scanning period. On the other hand, the row scanning electrodes are sequentially selected in synchronization with the driving of the column signal electrodes every half of the horizontal scanning period, and the pixel signal is written in each of the liquid crystal cells connected to the selected row scanning electrodes.

In the second field, as in the embodiment of FIG.
Only the pixels in the first row are driven by the image signal of the horizontal scanning period,
The pixels of the second row and the third row are driven by the image signal of the 264th horizontal scanning cycle, and all the pixels are selectively driven twice until the 504th horizontal scanning cycle. That is, in the first field, pixels in a few rows are driven in a positive polarity and pixels in an even number row are driven in a negative polarity, and in the second field, pixels in a few rows are negatively driven.
Since the pixels in the even rows are driven with a positive polarity, the voltage applied to each liquid crystal cell polarity is inverted every field, that will be alternating with the frame frequency (30H _z).

Another embodiment of the present invention is shown in FIG. In the embodiment of FIG. 15, the pixels in even rows are shifted by 1.5 pixels to the right from the pixels in the adjacent rows, and an active matrix type liquid crystal panel 92 in which color filters are arranged in a triangular shape is driven by an image signal in which the polarity is inverted for each row. FIG. 3 is a configuration diagram showing a double speed line sequential scanning circuit. First
13 is different from the embodiment of FIG. 13 in that each stage output of the horizontal scanning shift register 1 has a pixel equivalent time (for example, horizontal The number of pixels 648 is 81 ns later than the output of the preceding stage, whereas the number of outputs of the horizontal scanning shift register 21 in FIG. 3 is about twice that of the former, and the output of each stage is equivalent to the above-mentioned pixel equivalent time ( For example, the output of the shift register 11 is delayed by half the time of 81 ns) from the output of the previous stage.
The point is that the one-row signal electrodes are driven using a book.

The operation waveforms are the same as those in FIG. 14, and since they are almost the same as the operation of the embodiment of FIG. 13 except the sampling timing in the sampling mode, detailed description thereof will be omitted. Since the image signal sampling timing of the even-numbered rows is delayed by 1.5 pixels compared to the odd-numbered rows, in the first field, the selection switch S _F controlled by the field discrimination input Fi becomes conductive as shown in FIG. Then, the image signal for a few rows is sampled by S / H-A, and the image signal for an even row is sampled by S / H-B or C. In the second field, select switch
S _F is connected in reverse so that the image signal for several rows is sent to S / H-B or C
Then, the image signal for even rows is sampled by S / H-A.

Still another embodiment of the present invention is shown in FIG. 16 and its operation waveform is shown in FIG. The embodiment of FIG. 16 is a block diagram showing a double speed line sequential scanning circuit for driving an active matrix type liquid crystal panel 9 in which color filters are arranged in a diagonal mosaic pattern with image signals whose polarities are inverted for each row. The difference between the operation waveforms in FIG. 13 and FIG. 17 is mainly only in the sampling order of the sample and hold circuit, and the basic operation is almost the same, so detailed description will be omitted. In FIG. 17, the signals R _A +, R _A −, etc. to be sampled are respectively represented by terminals R _A
Shows the positive (+) and negative (-) polarities of the R (red) primary color applied to the primary color signal applied to the terminal _RA, etc., as shown in FIG. Will be replaced.

At this time, the primary color signal applied to each pixel and its polarity are
As shown in the figure. The + and-signs respectively indicate the polarities of the respective primary color signals, the upper row being the first field and the lower row being the second field.
It shows the polarity in the field. As is apparent from FIG. 19, the primary color signals for driving each pixel are inverted in polarity for each field, and the primary color signals applied to each column signal electrode are inverted in each row.

Another embodiment of the present invention is shown in FIG. 20 and its operation waveform is shown in FIG. The embodiment of FIG. 20 is a block diagram showing a double speed line sequential scanning circuit for driving the oblique mosaic color filter-arranged liquid crystal panel 9 with an image signal whose polarity is inverted row by row, as in the embodiment of FIG. . The difference from the embodiment of FIG. 16 is that the sample and hold circuit is connected to each column signal electrode drive circuit by four.
The system is provided, and the sampling mode sample hold 2 system and the read mode sampler hold 2 system are switched and used for each horizontal scanning cycle, and the buffer amplifier 7 is always in operation, and the drain bus Is not in a high impedance state.

The operation waveform example of FIG. 21 is 6k + 1 (k =
The operation example of the circuit for driving the (0, 1, 2, ...) th column signal electrode D _r −6k + 1 is shown. _{R +} , for signal lines X _{R +} , X _B-
Positive and negative polarity signals of three primary colors such as G + are sequentially given by the shift matrix 4 every horizontal scanning period as shown in FIG. 22, and, for example, S / H-A and B are R + and B- in the first horizontal scanning period, respectively. sampling the primary color signals, the R + signals early in S / H-a of the second horizontal scanning period is held, the S / H-B is held in the second half B- signals drain bus D _r -6k + 1 Output to. In the first half of the second horizontal scanning cycle, the gate bus Ga-1 is, and in the latter half, the gate bus Ga-1.
Since 2 is selected, the R + and B-pixel signals of the second row are written to the pixels of the first row. At the same time, in the second horizontal scanning period, S / H-C and D are sampling the G + and R- signals, respectively.

With S / H-D in the second half of the G + signal S / H-C are held in the first half of the third horizontal scanning period to output the R- signals are held in the drain bus D _r -6k + 1, in the first half Since the gate bus Ga-3 and the gate bus Ga-4 in the latter half are selected, the G + signal is written to the pixels in the third row and the R- signal is written to the pixels in the fourth row. At the same time, in the third horizontal scanning period, S / H-A and B sample the B + and G- signals, respectively.

Thereafter, the same operation is repeated and the first field is scanned. The same sampling operation, reading operation, and pixel writing operation are performed in the second field, and as shown in FIG. 23, each pixel is driven by a signal whose polarity is inverted every field, and each drain bus is also horizontally scanned. It can be driven by a signal whose polarity is inverted every half cycle.

〔The invention's effect〕

As described above, according to the present invention, the pixels in two rows can be easily selected and driven in one horizontal scanning period without using a digital double speed conversion circuit. 480 when a driving a liquid crystal panel, voltage is two fields (one frame) period to be applied to the liquid crystal cell by reversing the polarity of the image signal every field, i.e. becomes an AC signal of 30H _z, flicker is small, also It is possible to provide an active matrix type liquid crystal image display device having a long life.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a configuration diagram showing a first embodiment of a double speed line sequential scanning circuit used in an active matrix type image display device according to the present invention, and FIG. 2 is shown in FIG. FIG. 3 is an operation waveform diagram of the embodiment, FIG. 3 is a circuit diagram showing a concrete configuration example of the shift register in the embodiment shown in FIG. 1, and FIG. 4 is an operation waveform diagram of the circuit example shown in FIG. FIG. 5 is a block diagram showing an example of a control circuit for forming a signal applied to the control terminal of the embodiment shown in FIG. 1, and FIG. 6 is a double speed line sequential scanning used in the active matrix type image display device according to the present invention. FIG. 7 is a configuration diagram showing a second embodiment of the circuit, FIG. 7 is an operation waveform diagram of the embodiment shown in FIG. 6, and FIG. 8 is a double speed line sequential scanning circuit for an active matrix type television image display device according to the present invention. FIG. 9 is a block diagram showing the third embodiment, and FIG. 9 shows the embodiment shown in FIG. 10 is an operation waveform diagram, FIG. 10 is a block diagram showing an example of a control circuit for forming a signal applied to the control terminal of the embodiment shown in FIGS. 6 and 8, and FIG. 12 is an active circuit according to the present invention. FIG. 13 is a configuration diagram showing a fourth embodiment of a double speed line sequential scanning circuit used in a matrix type image display device, and FIG. 13 is a fifth view of a double speed line sequential scanning circuit used in an active matrix type image display device according to the present invention. FIG. 14 is a block diagram showing the embodiment of FIG.
Waveform diagrams showing operation waveforms of FIG. 13, FIG. 15, and FIG. 16 are configuration diagrams showing sixth and seventh embodiments of a double speed line sequential scanning circuit used in an active matrix type image display device according to the present invention, respectively. 17, FIG. 18, FIG. 18 and FIG. 19 are explanatory views for explaining the operation of the embodiment of FIG. 16, and FIG. 20 is a double speed line sequential scanning circuit used in the active matrix type image display device according to the present invention. Configuration diagram showing the eighth embodiment, FIGS. 21 and 22
FIGS. 23 and 23 are explanatory diagrams for explaining the operation of the embodiment of FIG. 20, and FIG. 24 is a diagram for explaining the in-panel operation waveforms by the conventional liquid crystal panel drive circuit. 1,21 ...... Horizontal scan shift register, 2 …… AND circuit, 3 …… Level shifter, 4 …… Shift matrix, 5,
13 ... Hold capacity, 6 ... Voltage follower, 7 ...
... buffer amplifier, 8 ... vertical scanning shift register,
10 …… MOS transistor, 11 …… Liquid crystal cell, 12 …… Buffer amplifier with output control, R +, R−, G +, G−, B +, B−
Positive, negative polarity of the primary color signals of red, green and blue respectively, _Wij , _Sij
(I = A, B, C, D, j = 1,2,3, ...) Analog switch, 91 ... Vertical stripe color filter arrangement Liquid crystal panel, 92
...... Triangle color filter arrangement LCD panel, 9 ……
Diagonal mosaic color filter arrangement Liquid crystal panel, Ga ...... row scanning electrode, D _r ...... column signal electrode.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Satoshi Takashimizu 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Prefecture Home Appliance Research Laboratory, Hitachi, Ltd. (56) Reference JP-A-61-116393 (JP, A) Special features Kai 60-173982 (JP, A)

Claims (1)

[Claims] 1. An active matrix type image display device having switching elements arranged in a matrix and pixels composed of display elements, wherein an image is displayed by turning on and off the switching elements. A unit drive circuit for driving the electrodes includes a plurality of sample and hold circuits, and a control circuit for controlling the plurality of sample and hold circuits in the unit circuit to perform sampling operation of an image signal during one horizontal scanning period; An active matrix type characterized by comprising a double speed line sequential scanning line circuit provided with a circuit for driving the signal electrode by switching the outputs of a plurality of sample hold circuits in the unit circuit a plurality of times during a scanning cycle. Image display device.