JPH0219083A - Sample-and-hold circuit - Google Patents

Abstract

PURPOSE:To ensure the sampling time by providing an overlap between sampling periods of each sample-and-hold elements. CONSTITUTION:Sample-and-hold elements 2A1, 2B1, 2C1,..., 2An, 2Bn, 2Cn are made up of an analog switch 4 sampling video signals VA-VC, a capacitor 5 holding the video signals and a converter 6 converting the signal into a lighting/nonlighting control signal of a liquid crystal element and giving an output. Then 3 columns of n-bit shift registers driven respectively by 3 systems of clocks phiA-phiC, for example, are provided to share the sampling period control for each element group. Thus, lots of sample-and-hold elements 2A1, 2B1... are sampled with a prescribed time deviation while being overlapped mutually. Thus, a sufficiently long sampling time is ensured.

Description

[Detailed Description of the Invention] [Object of the Invention] (Field of Industrial Application) The present invention relates to a sample and hold circuit used in a large-scale integrated circuit for driving a liquid crystal television, and in particular, This invention relates to improvements in shift registers used to control the drive of each sample and hold element.

(Prior art) An LSI for driving an LCD television is equipped with a sample and hold circuit, which samples the video signal obtained by shooting, and uses the sampled value to control the display of the liquid crystal display (LCD).
) Controls lighting/non-lighting of each liquid crystal element. Such a sample-and-hold circuit has a sample-and-hold element for each of the liquid crystal elements arranged in a matrix in the LCD, and the sampling timing of each sample-and-hold element is determined based on the shift in scanning time at the time of photographing. In order to shift the drive timing of each sample-and-hold element according to the timing, the output of each stage of the shift register is used to shift the drive timing of each sample-and-hold element.

FIG. 8 shows a circuit diagram of a shift register used in a conventional sample-and-hold circuit for a color liquid crystal television and its operation timing.

Generally, in the LCD of a color liquid crystal television, the liquid crystal elements that reproduce the three basic color components A, B, and C, respectively, are
They are arranged alternately in the following order: B, C, A, B, C,... Since the arrangement positions of each of these liquid crystal elements are shifted at a constant pitch, each sample and hold element for driving each liquid crystal element is adjusted in accordance with the shift in the scanning time during shooting corresponding to the position shift. It is necessary to shift the sampling period. In order to do this, the conventional sample-and-hold circuit uses a one-phase, one-line shift register driven by a -phase clock Φ, as shown in Figure 8, and from each stage, a time period equivalent to one cycle of the driving clock Φ is used. Output signal QAm with deviation.

QBm, QCm, QAm+1.・= is obtained. Of these, the output signal QAm is used as a sampling control signal for the m-th liquid crystal element of color component A, and the output signal QBm of the next stage is used as a sampling control signal for the m-th liquid crystal element of color component B. Furthermore, the output signal QCm of the next stage is used as a sampling control signal for the m-th liquid crystal element of color component C, so that all three color liquid crystal element sampling timings are controlled by a shift register arranged in one phase. There is.

(Problem to be Solved by the Invention) By the way, a sample hold element that drives a liquid crystal element generally includes an analog switch for sampling a video signal and a capacitor for holding the sampled video signal. The liquid crystal element is turned on and off in accordance with the voltage held in it. In this case, sampling is performed when the analog switch is on, and the length of this sampling time is set by the time width of the output signal applied from each stage of the shift register to each analog switch. Here, the sampling time must be set to a time sufficiently longer than the time constant determined by the on-resistance of the analog switch and the capacitance of the capacitor. This is because if the sampling time is shorter than the time constant, the hold voltage will not rise sufficiently, making it impossible to reliably control the drive of the liquid crystal element.

However, in the above-mentioned conventional technology, the liquid crystal elements of the -scanning line are controlled by a one-phase, one-column shift register, and the time difference between the outputs of each stage corresponds to one period of the drive clock, so the LCD elements The higher the number, the higher the frequency the shift register must be driven.
Since the output time of each stage of the shift register is shorter,
It becomes difficult to secure sufficient sampling time.

For example, the time per scanning line of a television image is 63
It is defined as 65 μsec. Therefore, when using an LCD with 480 horizontal elements, the retrace period is set to 10
If μSee, the sampling frequency of the video signal is 8
．． 97MHz [-480/(63.5μm10μ)]
becomes. That is, the sampling time of the video signal is 1lln
Since the time is as short as see[-1/8.97 MHz, the hold voltage cannot be expected to rise completely within the sampling time, making it difficult to reproduce a faithful image.

Therefore, an object of the present invention is to ensure that each sampling time is sufficiently long even when the difference in sampling timing of each sample-and-hold element is shortened, thereby ensuring reliable sampling operation. The object of the present invention is to provide a sample-and-hold circuit that can perform

[Structure of the invention]

(Means for Solving the Problems) In order to achieve the above object, the present invention provides a multi-stage shift register with a large number of sample-and-hold elements, and a plurality of columns in which these sample-and-hold elements are divided and sequentially driven by the output of each stage. The multi-stage shift registers in the plurality of columns are each driven by shift clocks of different systems, and the shift clocks of the different systems provide a sample-and-hold circuit whose phases are shifted from each other by a plurality of cycles.

Further, the present invention includes a large number of sample water holding elements and a single column multi-stage shift register that sequentially drives these sample holding elements by the output of each stage, and this single column stage shift register is used for multiple systems. The sample and hold circuit is driven by a shift clock so that shift clocks of the same system are cyclically applied to each of a plurality of stages, and the shift clocks of the plurality of systems have phases shifted from each other by a plurality of cycles. .

Furthermore, the present invention includes a large number of sample-and-hold elements and a single-column multi-stage shift register that sequentially drives these sample-and-hold elements by the output of each stage, and this single-column stage shift register is driven by one system of shift clocks. A sample and hold circuit is provided which is driven and is supplied with an input signal having a pulse width equivalent to a plurality of cycles of this shift clock.

(Function) According to the above configuration, a large number of sample and hold elements perform sampling with a predetermined time lag while the sampling times overlap with each other. Since the sampling times of each sample-and-hold element are overlapped in this way, even if the deviation of each sample-and-hold element is shortened, a sufficiently longer sampling time can be secured compared to the conventional technique.

(Example) Hereinafter, the present invention will be specifically explained with reference to Examples.

FIG. 1 shows a block configuration of an embodiment of a sample and hold circuit for driving a color liquid crystal television according to the present invention, and FIG. 2(a) shows shift registers 7A and 7B of this embodiment.
, 7C is shown.

As already explained, in an LCD for a color liquid crystal television, liquid crystal elements IA1. ...,I
An, a liquid crystal element IB1 for reproducing color component B; ...,l
Liquid crystal elements IC1, . . . for reproducing Bn and color component C;
ICn are arranged alternately as shown. These liquid crystal elements IA1゜IBI, ICL・'', IAn, IB
n, ICn, a sample hold element 2A1.2B1.2CI, . . . for driving each of ICn.
2An, 2Bn, and 2Cn are provided. These sample and hold elements correspond to the colors A, B, and C of the liquid crystal element to be driven.
It is divided into groups according to the element group IA1. ..., IAn
is connected to the signal line 3A of the video signal VA of color component A to the element group IB.
1. ..., lBn are connected to the signal line 3B of the video signal VB of color component B, and the element groups IC1, ..., ICn are connected to the signal line 3B of the video signal VB of color component B.
are respectively connected to the signal line 3C of the video signal VC. Each sample and hold element receives video signals VA, VB.
.

an analog switch 4 for sampling VC;
It consists of a capacitor 5 for holding the sampled video signal, and a converter 6 for converting the held video signal into a lighting/non-lighting control signal for the liquid crystal element and outputting it. It should be noted that each converter 6 performs an output operation for each -scanning line at the same time in response to an output enable signal OE.

Each liquid crystal element IA1. IBI, ICI, ...IAn, I
Since the positions of Bn and ICn are shifted at a constant pitch as shown in the figure, each sample hold element 2A1, 2 is
It is necessary to shift the timing of sampling B1, 2C1, . . . 2An, 2Bn, 2Cn. To do this,
In this embodiment, three rows of one-phase n-bit shift registers 7A, 7B, and 7C each driven by three systems of clocks ΦA, ΦB, and ΦC are provided, and control of sampling timing is shared for each of the above-mentioned element groups.

These shift registers 7A, 7B, and 7C are configured to receive input signals QA, QB, and QC having pulse widths equivalent to one cycle of clocks ΦA, ΦB, and ΦC, respectively. Of these, the output of each stage of the shift register 7A is connected to the control terminal of each analog switch 4 of the sample and hold element group IAI, . . . , IAn.
The output of each stage is from the element group IB1. ..., to the control terminal of each analog switch 4 of IBn, and also to the shift register 7.
The output of each stage of C is connected to the control terminal of each analog switch 4 of the element group IC1, . . . , lcn via a level shifter 8. And clock ΦA.

By adjusting the timing of ΦB and ΦC, the input signal QA to each stage of those three columns of shift registers 7A, 7B, and 7C is
The shift points of QB and QC are shifted by a fixed amount of time, thereby shifting the sampling timing of each sample-and-hold element.

As shown in FIG. 2(a), each shift register 7A, 7
B, 7C, each stage is a signal Q shifted from the previous stage.
Input gate 11 consisting of a clocked inverter for taking in A, QB, QC and the taken signals QA, QB, Q
It has an output gate 12 consisting of a clocked inverter for shifting C to a subsequent stage, and an external output line 13 for outputting signals QA, QB, and QC shifted from the output gate 12 to the subsequent stage to the control terminals of the corresponding analog switches. It is configured as follows. The output gates 12 of each stage are turned on when the clocks ΦA, ΦB, and ΦC rise, and are held in the output state when they fall, and the input gates 12 are turned on when they rise, and are held in the output state when they rise. Therefore, each stage output QAm, QBm, QCm, QAm+
1. -... are determined at the rising edge of clocks ΦA, ΦB, and ΦC.

FIG. 2(b) shows shift registers 7A and 7B.

7C operation timing is shown. These shift registers 7A, 7B, and 7C all have a duty ratio of 1.
A clock ΦA whose phase is shifted by 1/3 period by /3,
Driven by ΦB and ΦC.

Therefore, the output QAm of the shift register 7A is at a high level during one period from the rise to the rise of the clock ΦA, and the output QBm of the shift register 7B is at a high level during one period from the rise to the rise of the clock ΦB, which is shifted by 1/3 period. Next 1. Clock Φ further shifted by 1/3 period
The output QAm, QBm, QCm of each shift register is such that the output QCm of the shift register 7C becomes high level in one cycle from the rise of C to the rise of C.

QAm+1. ... rises at intervals of 1/3 period and maintains a high level state for one period. Therefore, each analog switch driven by these outputs also has l/
It turns on at three-cycle intervals and continues sampling for one cycle.

In this case, sampling of video signals having different color components is performed in an overlapping manner, but since the signals are of different systems, mutual interference does not occur. In addition, regarding sampling of video signals of the same color component using different analog switches, at the rising edge of the clock, the previous output of the shift register (for example, QAm) falls and the output of the latter stage (for example, QAm) falls.
Am+1) rises, so there is no overlap.

Comparing the above operation with the conventional example shown in FIG. 8, it can be seen that although the deviation in the start time of each sampling is the same, the sampling time is three times longer. Furthermore, when the pulse widths of the clocks ΦA, ΦB, and ΦC are compared with those of the conventional example, it is found that they are twice as long. Thus, according to this embodiment, the operating frequency can be improved by three times in the sampling time and twice in the clock width.

FIG. 3 shows the operation timing of the second embodiment of the present invention. This embodiment uses the same shift register as in FIG. 2(a). The difference is that clock ΦB is used as clock ΦC.
The point is that the inverted signal of . In this case, each clock ΦA, ΦB.

Since the time lag in the rise of ΦC is the same as in FIG. 2(b), the outputs of each stage QAm, QBm, QCm.

QAm+l, . . . are also the same as in FIG. 2(a), and the same sampling operation can be obtained.

The advantage of this embodiment is that the clock generation circuit can be simplified. In other words, to generate the three systems of clocks ΦA, ΦB, and ΦC shown in FIG. 2(b), separate generation circuits are required, but the clocks of FIG.
C is clock ΦA.

It is only necessary to have each generation circuit of ΦB and an inverter, resulting in a simpler configuration, so that the pattern area can be reduced when configured as an integrated circuit.

FIG. 4 shows the operation timing of the third embodiment of the present invention. This embodiment also uses the shift register shown in FIG. 2(a). A feature of this embodiment is that the duty ratio of the clocks ΦA, ΦB, and ΦC is 1/2. Each clock ΦA, Φ
The phase shift of B and ΦC is the same as in the case of FIG. 2(b). Therefore, the sampling operation is the same as the embodiment of FIG.

The advantage of this embodiment is that the clocks ΦA, ΦB.

The operating frequency is improved by reducing the duty ratio of ΦC to 1/2. In other words, in the case of FIG. 2(a), the clock width is twice as long as compared to the conventional example shown in FIG. 8, but in the case of this embodiment, the clock width is three times longer, The operating frequency of the generator circuit is further improved.

FIG. 5 shows a block configuration of a fourth embodiment of the present invention,
FIG. 6(a) shows a circuit diagram of the shift register 7 of this embodiment.

As shown in FIG. 5, in this embodiment, the sampling timing of each sample-and-hold circuit is controlled using a three-phase, single-column nX3-bit shift register 7 driven by three systems of clocks ΦA, ΦB, and ΦC.

As shown in FIG. 6(a), each stage of the shift register 7 includes an input gate 11 consisting of a clocked inverter for receiving the signal Q shifted from the previous stage, and an input gate 11 for receiving the signal Q shifted from the previous stage. It is configured to include an output gate 14 consisting of an always-on inverter that is shifted to the subsequent stage, and an external output line 13 that outputs the signal Q output from the output gate 14 to the subsequent stage to a corresponding analog switch. Each of the clocks ΦA, ΦB, and ΦC is cyclically applied to the manual gate 11 at every third stage, shifted by one stage from each other. Then, the output QA of the stage driven by the clock ΦA
m, QAm+1. . . . is the output Q of the stage driven by the clock ΦB as the sampling control signal of the video signal VA.
Bm, . . . are the sampling control signals of the video signal VB, and the output QCm of the stage driven by the clock ΦC,
. . . are respectively used as sampling control signals for the video signal VC.

FIG. 6(b) shows the operation timing of this shift register. This shift register operates substantially in the same way as the shift register in FIG. 2(a), and in this embodiment is driven by the same clocks ΦA, ΦB, and ΦC as in FIG. 2(b). Therefore, the same operation as in the case of FIG. 2(b) can be obtained, and the same improvement in operating frequency can be obtained.

The advantage of using such a three-phase, single-column shift register is that the structure of the shift register is simplified. In other words, Fig. 2 (a
) and FIG. 6(a), it is clear that compared to the case where a three-column shift register is used, in this embodiment, the number of wires of the shift register, etc. is greatly simplified.
This can greatly contribute to reducing the pattern area when configured as an integrated circuit.

As mentioned above, the shift register in FIG. 6(a) is changed to the shift register in FIG.
Since it operates essentially the same as the shift register in a), it is used as the clock ΦA shown in FIGS. 3 and 4.
An embodiment in which driving is performed by ΦB and ΦC is also possible. Of course, these embodiments also provide the same effects as the embodiments shown in FIGS. 3 and 4.

FIG. 7 shows the structure and operation timing of a shift register according to a fifth embodiment of the present invention. This embodiment uses a 1-phase, 1-column, n.times.3 bit shift register, which is the same as the conventional example shown in FIG. 8, and is driven by a clock Φ having the same frequency as the conventional example.

The difference is the pulse width of the input signal Q of the shift register. That is, in the conventional example shown in FIG. 8, an input signal Q having a pulse width equivalent to one cycle of the clock Φ is used, but in this embodiment, an input signal Q having a pulse width equivalent to three cycles of the clock Φ is used. As a result, each stage output of the shift register QAm, QBm, QCm, QAm+1. -... have a pulse width equivalent to three periods of the clock Φ, and rise sequentially with a time lag equivalent to one period of the clock Φ while overlapping each other.

The operation of this shift register is substantially the same as that of the first to fourth embodiments described above, and therefore a similar sampling operation is obtained. The advantage of this embodiment is that the shift register can be driven by l systems of clocks Φ.

Although some preferred embodiments have been described above, the present invention is not limited to these embodiments. As long as the outputs of each stage of the shift register rise and fall with a specified time lag, various other variations can be considered regarding the configuration of the shift register, the overlap width of the outputs of each stage, etc. obtain. Furthermore, although the above embodiment has been described with reference to a sample and hold circuit for driving a commercially available television, the present invention is not limited thereto. If it is applicable in the field,
It can be applied to various fields such as facsimiles, copying machines, and image printers.

〔Effect of the invention〕

As explained above, according to the present invention, since there is an overlap between the sampling times of each sample and hold element, it is necessary to shorten the deviation in the drive timing of each sample and hold element. However, sufficient sampling time can be secured, and reliable sampling operation can be guaranteed. Furthermore, if the sampling time is kept the same as in the past, more sample and hold elements can be driven at higher speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a first embodiment of the sample and hold circuit according to the present invention, FIG. 2 is a circuit diagram of the shift register of the embodiment of FIG. 1 and a timing chart showing its operation, and FIG. A timing chart showing the operation of the second embodiment of the invention, FIG. 4 a timing chart showing the operation of the third embodiment of the invention, and FIG. 5 a block diagram of the fourth embodiment of the invention. , FIG. 6 is a circuit diagram of the shift register of the embodiment of FIG. 5 and a timing chart showing its operation, and FIG. 7 is a circuit diagram of the shift register of the fifth embodiment of the present invention and a timing chart showing its operation. , 8th
The figure is a circuit diagram of a shift register of a conventional sample and hold circuit and a timing chart showing its operation. 2... Sample and hold element, 4... Analog switch, 5... Capacitor, 7... 3-phase 1-row QX 3-bit shift register, 7A, 7B, 7C... --phase 3-row n-bit shift register , 11... input gate, 12
．． 14...Output gate, 13...External output line. QArn++ Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7

Claims (1)

[Scope of Claims] 1. A multi-stage shift register with a plurality of columns, which includes a large number of sample-and-hold elements and a plurality of columns of multi-stage shift registers that share these sample-and-hold elements and sequentially drive the outputs of each stage, and these multi-column multi-stage shift registers. are respectively driven by shift clocks of different systems, and the phases of the shift clocks of the different systems are shifted from each other by one period of a plurality of sample and hold circuits. 2. Equipped with a large number of sample-hold elements and a single-column multi-stage shift register that sequentially drives these sample-hold elements with outputs from each stage, and this single-column multi-stage shift register uses shift clocks of the same system using multiple systems of shift clocks. The sample and hold circuit is driven such that the shift clocks of the plurality of systems are cyclically added to each of a plurality of stages, and the phases of the shift clocks of the plurality of systems are shifted from each other by one period of a plurality of cycles. 3. The sample hold circuit according to claim 1, wherein at least one of the shift clocks is an inverted signal of another shift clock. 4. The sample hold circuit according to claim 1 or 2, wherein the shift clock has a duty ratio of 1/2. 5. It is equipped with a large number of sample and hold elements and a single column multistage shift register that sequentially drives these sample and hold elements by the output of each stage, and this single column multistage shift register is driven by one system of shift clocks, and this A sample and hold circuit that receives an input signal with a pulse width equivalent to multiple cycles of the shift clock.