JP2003140622A - Active matrix type liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an active matrix type liquid crystal display device of which the picture is deteriorated little in quality due to inter-phase crosstalk even when video signals are supplied in parallel and multiple phases. SOLUTION: In the active matrix type liquid crystal display device which is provided with a substrate having column signal electrodes D1-Dn, row scanning electrodes G1-Gm, display pixels PIX including transistors Tr and pixel electrodes, a column signal electrode driving circuit 4, a row scanning electrode driving circuit 8, and video signal input lines S1-SN to be connected in common with the corresponding electrodes in the column signal electrodes grouped for each N pieces of electrodes, and an external driving circuit 10 for converting the video signals into N-series simultaneous parallel signals and sending them to a multi-video signal output line, and which sequentially samples the inputted video signals in parallel to the adjacent N pieces of column signal electrodes, the video signals are arranged so as to be supplied with the polarity inverted at every other connection line arrangement in the output side connection lines of the external driving circuit 10, and to be supplied with the same polarity in all the phases in the input side of the video signal input lines on the substrate 2.

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type liquid crystal display device suitable for a projection type liquid crystal display and the like. 2. Description of the Related Art In general, as a display device replacing a CRT, for example, Japanese Patent Application Laid-Open No. 5-108028 and Japanese Patent Application Laid-Open No. 11-25, because of their small size and very low power consumption.
A display device using a liquid crystal as disclosed in, for example, Japanese Patent Publication No. 9053 or the like has attracted attention and has been widely used. Here, an example of a conventional liquid crystal display device will be described. FIG. 4 is a configuration diagram showing a conventional active matrix type liquid crystal display device. In the figure, an active matrix substrate 2 has a plurality of column signal electrodes D
1, D2,... Dn and row scan electrodes G1, G2,.
Are formed in directions orthogonal to each other, and each of the electrodes D1 to Dn,
A display pixel PIX is formed at each intersection of G1 to Gm. This display pixel PIX is, as shown in FIG.
It comprises a switching transistor Tr, an auxiliary capacitor Cs, a display pixel electrode (not shown) and a liquid crystal display LCM. In FIG. 5, a column signal electrode is represented by D, and a row scanning electrode is represented by G. The column electrode driving circuit 4 includes a shift register circuit 6
And N (in the illustrated example, N = 4) video signal input lines S1, S2, S3, S4 are horizontally adjacent to the input sides of the switch circuit groups SW1 to SWn. At every four pixel pitches (every four signal electrodes). 4 adjacent switch circuits
As a group, the output lines B1, B2,... Bn / 4 of each stage of the shift register circuit 6 are sequentially connected to each switch control terminal in a group unit. The row scanning electrode driving circuit 8 is formed of a shift register circuit, and the output lines of each stage are connected to the row scanning electrodes G1, G2,... Gm, respectively, and the row scanning electrodes G1, G2,. It is connected to the gate terminal of the switching transistor Tr of the located display pixel PIX. An external drive circuit 10 is connected to the active matrix substrate 2 as shown in the figure. The external drive circuit 10 includes a timing generation circuit 12, a drive pulse generation circuit 14, a phase expansion circuit 16, a polarity inversion circuit 18, and a video signal buffer circuit Buf. The timing generation circuit 12 outputs the horizontal synchronization signal H and the vertical synchronization signal V from the previous stage.
Then, a timing signal such as horizontal, vertical and clock synchronized with these signals and a timing signal necessary for developing a video signal in parallel are generated. The drive pulse generation circuit 14 receives horizontal, vertical, and clock signals from the timing generation circuit 12, and receives drive signals HST (horizontal start signal) and HCK (horizontal shift clock signal) used in the column signal electrode drive circuit 4 of the active matrix substrate 2. 1, HCK (horizontal shift clock signal) 2 and drive signals VST (vertical start signal), VCK (vertical shift clock signal) 1 and VCK (vertical shift clock signal) 2 used in the row scanning electrode drive circuit 8 are generated. A video signal Video input from the outside is converted by a phase expansion circuit 16 into N series (N = 4 in the illustrated example) simultaneous parallel signals corresponding to N display pixels adjacent to each other in advance. FIG. 6 shows an outline of this phase deployment operation. That is, the video signal Video is sampled at a predetermined time interval, and each sampled value is stored in the video signal input line S1.
ＳS4 are distributed in such a manner as to be sequentially input in a cyclic manner. The phase-developed video signal is converted by a polarity inversion circuit 18 into an AC signal whose polarity is inverted every vertical scanning cycle. This is intended to prevent material deterioration and image sticking by driving a liquid crystal as a display body with an AC voltage. The video signal (parallel signal) of each phase converted into an alternating current by the polarity inversion circuit 18 is supplied to a buffer circuit Buf.
Video signal input line of the active matrix substrate 2 through
Simultaneous and parallel inputs are made to S1, S2, S3, and S4 in the form shown in FIG. The drive signal of HST, HCK1, and HCK2 is supplied from the external drive circuit 10 to the shift register circuit 6 of the column signal electrode drive circuit 4 of the active matrix substrate 2, thereby forming the column signal electrode drive circuit 4. The shift register 6, which is an element, is driven, and pulses are sequentially output to the output stages B1 to Bn / 4. The switch groups SW1 to SWn of the column signal electrode drive circuit 4 are
Are sequentially turned on by the output of the video signal input lines S1,
The video signals input in parallel to S2, S3, and S4 are converted into adjacent four sets (groups) of column signal electrodes (D1, D2, D3, D4), (D
5, D6, D7, D8), ... are sampled in parallel sequentially. As described above, by processing the video signal (display signal) as an N-phase parallel signal, the drive clock rate of the shift register and the display signal rate can be reduced to 1 / N, and the number of pixels can be increased. It is possible to correspond to the display device. On the other hand, by supplying VST, VCK1, VCK2 drive pulses from the external drive circuit 10 to the row scan electrode drive circuit 8, selection pulses are sequentially sent to the row scan electrodes G1, G2,... Gm. Each row of the switching transistors Tr of the display pixels PIX provided at each intersection of the column signal electrodes D1 to Dn and the row scanning electrodes G1 to Gm is sequentially turned on. As a result, the display signal sampled on the column signal electrode D is supplied to the liquid crystal display LCM via the switching transistor Tr. The auxiliary capacitance Cs is provided for the purpose of holding the liquid crystal driving voltage during the period in which the switching transistor Tr is off and realizing high duty driving. In the above-described liquid crystal display device according to the prior art, as shown in FIG. 4, a video signal and a driving pulse which are made into a parallel polyphase are externally driven with respect to the active matrix substrate 2. Since the configuration is supplied from the circuit 10, in particular, in order to realize a high-definition, high-pixel-number liquid crystal display device, the video signal is subjected to parallel multi-phase processing to reduce the driving frequency and is simultaneously sampled. Reducing the substantial operating frequency is an effective measure. On the other hand, the following problems have arisen. FIG. 7 is a waveform diagram showing a multi-phase video signal of a conventional liquid crystal display device. Here, the video signals are S1, S2, S3, S4
4 shows a case in which four-phase expansion is performed corresponding to the four input lines, and the video signal corresponding to the input lines S1 and S2 includes a video signal (a video having a vertical Signal), and a constant-level signal that does not change with time is input to the input lines S3 and S4. In the liquid crystal display device described in the related art, the characteristics in the external drive circuit 10, the signal transmission path from the external drive circuit 10 to the active matrix substrate 2, the wiring in the circuit of the active matrix substrate 2, etc. There is a problem that inter-phase crosstalk occurs between multi-phase parallel video signals due to the influence of capacitive coupling and the like, and block-like noise occurs due to a sampling error. In FIG. 7, the signal waveform components of the signals of the input lines S1 and S2 crosstalk with the video signals corresponding to the signals of the input lines S3 and S4, which do not change with time.
This effect appears as block-like noise and greatly degrades image quality. In particular, for signal transmission from the external drive circuit 10 to the active matrix substrate 2, it is difficult to completely match the transmission line characteristics of the wires serving as connection lines with the load impedance of the input portion of the active matrix substrate 2, Under such conditions of impedance mismatch, crosstalk occurs more remarkably. In order to realize a liquid crystal display device having a large number of pixels, it is necessary to increase the number of phase expansions (N) of a video signal.
The problem of crosstalk between video signals becomes even more serious. The present invention focuses on the above problems, and has been conceived in order to effectively solve the problems. The purpose of the present invention is to reduce the deterioration of image quality due to inter-phase crosstalk even when video signals are supplied in parallel and multi-phase. An object of the present invention is to provide a small active matrix liquid crystal display device. According to the present invention, a plurality of column signal electrodes, a plurality of row scanning electrodes, and a crossing portion between the column signal electrodes and the row scanning electrodes are provided. A display pixel including a switching transistor and a pixel electrode arranged in a matrix; a column signal electrode driving circuit including a shift register circuit and a switching circuit group for sequentially sampling display signals on the plurality of column signal electrodes; A row scan electrode drive circuit including a shift register circuit for supplying a row selection pulse to the row scan electrodes; and the column signal electrodes are grouped into adjacent N (≧ 2 natural number) column signal electrodes. An active element having N video signal input lines commonly connected to the corresponding column signal electrodes of the N column signal electrodes of the group via the switch circuit group; An external drive circuit that converts a video signal into an N-series simultaneous parallel signal and sends each signal to a polyphase video signal output line connected to the video signal input line. In the active matrix type display device which sequentially samples the video signal in parallel to the adjacent N column signal electrodes, the connection lines on the output side of the external drive circuit for simultaneous parallel signals have respective connection line arrangements. A first polarity inversion circuit group for inverting the polarity of the video signal every other line, and all the phase video signals are supplied to the column signal electrode drive circuit on the input side of the video signal input line of the active matrix substrate. An active matrix liquid crystal display device comprising a second polarity inversion circuit group for inverting the polarity of the video signal so as to be supplied with the same polarity. An embodiment of an active matrix type liquid crystal display device according to the present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 is a block diagram showing a first embodiment of the active matrix type liquid crystal display device of the present invention.
FIG. 2 is a waveform diagram showing signals of respective parts in FIG. In addition, FIG.
The same components as those shown in FIG. 7 are described with the same reference numerals. As shown in the figure, in the first embodiment of the active matrix type liquid crystal display device, the active matrix substrate 2 is provided in the same manner as described above with reference to FIG.
, Dn and row scanning electrodes G1, G2,... Gm are formed in directions orthogonal to each other, and a display pixel PIX is provided at each intersection of the electrodes D1 to Dn, G1 to Gm. Is formed. This display pixel PIX
Is the switching transistor T as shown in FIG.
r, an auxiliary capacitor Cs, a display pixel electrode (not shown), and a liquid crystal display LCM. The column electrode driving circuit 4 includes a shift register circuit 6
And N (in the illustrated example, N = 4) video signal input lines S1, S2, S3, S4 are horizontally adjacent to the input sides of the switch circuit groups SW1 to SWn. At every four pixel pitches (every four signal electrodes). 4 adjacent switch circuits
As a group, the output lines B1, B2,... Bn / 4 of each stage of the shift register circuit 6 are sequentially connected to each switch control terminal in a group unit. The row scanning electrode drive circuit 8 is formed of a shift register circuit, and output lines of each stage are connected to row scanning electrodes G1, G2,... Gm, respectively, and the row scanning electrodes G1, G2,. It is connected to the gate terminal of the switching transistor Tr of the located display pixel PIX. An external drive circuit 10 is connected to the active matrix substrate 2 as shown. The external drive circuit 10 includes a timing generation circuit 12, a drive pulse generation circuit 14, a phase expansion circuit 16, a polarity inversion circuit 18, and a video signal buffer circuit Buf. The timing generation circuit 12 outputs the horizontal synchronization signal H and the vertical synchronization signal V from the previous stage.
Then, a timing signal such as horizontal, vertical and clock synchronized with these signals and a timing signal necessary for developing a video signal in parallel are generated. The drive pulse generation circuit 14 receives horizontal, vertical, and clock signals from the timing generation circuit 12, and receives drive signals HST (horizontal start signal) and HCK (horizontal shift clock signal) used in the column signal electrode drive circuit 4 of the active matrix substrate 2. 1, HCK (horizontal shift clock signal) 2 and drive signals VST (vertical start signal), VCK (vertical shift clock signal) 1 and VCK (vertical shift clock signal) 2 used in the row scanning electrode drive circuit 8 are generated. A video signal Video input from the outside is converted by a phase expansion circuit 16 into N series (N = 4 in the illustrated example) simultaneous parallel signals corresponding to N adjacent display pixels in advance. FIG. 6 shows an outline of this phase deployment operation. That is, the video signal Video is sampled at a predetermined time interval, and each sampled value is stored in the video signal input line S1.
ＳS4 are distributed in such a manner as to be sequentially input in a cyclic manner. The phase-developed video signal is converted by a polarity inversion circuit 18 into an AC signal whose polarity is inverted every vertical scanning cycle. This is intended to prevent material deterioration and image sticking by driving a liquid crystal as a display body with an AC voltage. The video signal (parallel signal) of each phase converted into an alternating current by the polarity inversion circuit 18 is supplied to a buffer circuit Buf.
Video signal input line of the active matrix substrate 2 through
Simultaneous and parallel inputs are made to S1, S2, S3, and S4 in the form shown in FIG. In this embodiment, the output side of the polarity inversion circuit 18, ie, a part of the connection lines X1 to X4 connecting the polarity inversion circuit 18 and the buffer circuit Buf,
A first polarity inversion circuit group 20 for inverting the polarity of the video signal is provided for every other line arrangement. Specifically, the above 4
To two connecting lines X1 and X3 of the connecting lines X1 to X4,
For example, polarity inverting circuits INV1 and INV formed by inverters
V2 is interposed. As described above, by arranging the polarity inverting circuits INV1 and INV2 every other phase of the adjacent video signal, the set of the outputs (P1, P3) and the set of the outputs (P2, P4) have opposite polarities. Become. Note that P1 to P4 indicating output lines also represent signals flowing through them. Correspondingly, the four-phase video signals of all four phases are supplied to the column signal electrode drive circuit 4 with the same polarity to the input sides of the video signal input lines S1 to S4 of the active matrix substrate 2. Thus, the second polarity circuit inversion group 22 for inverting the polarity of the video signal is provided. Specifically, the four video signal input lines S1 to S4
The phase inverting circuits INV3 and INV4 made up of, for example, inverters are respectively interposed between the two input lines S2 and S4. As described above, the polarity inversion circuits INV3 and INV4 for inverting the polarities of the signals (P2 and P4) input without passing through the polarity inversion circuits INV1 and INV2 are arranged at the input portion of the video signal in the active matrix substrate 2. Is done. A description will now be given of the waveform of the video signal in the display device configured as described above. FIG. 2 shows the external drive circuit 1
An example of signal waveforms of the polyphase video signal output lines P1, P2, P3, P4 from 0 and the video signal input lines S1, S2, S3, S4 of the column signal electrode drive circuit 4 of the active matrix substrate 2 is shown. . As an example, here, a signal (a display pattern such as a vertical line) with a temporal change is input to each of the first phase and the second phase, and a constant level signal is input to each of the third phase and the fourth phase. It is assumed that there is. The signals P1 and P2 are video signals having a rising edge and a falling edge corresponding to the display pattern. In the present invention, the polarity inverting circuit IN of the external driving circuit 10 is used.
Due to the presence of V1 and INV2, only the signal P1 is inverted,
The changes corresponding to the display patterns of the signals P1 and P2 have opposite phases. As a result, even when the video signal waveforms of the first phase and the second phase crosstalk with another phase, that is, the third phase and the fourth phase, the crosstalk component becomes the opposite phase and the influence is canceled. . Since the polarity inversion circuits INV3 and INV4 for the signals P2 and P4 which are not inverted by the external drive circuit 10 are provided on the active matrix substrate 2, the video signal input lines of the column signal electrode drive circuit 4 are provided. S1, S2, S
The polarities of the video signals of the respective phases S3 and S4 are all in the same state, so that all the pixels can be driven by the signal voltages of the same polarity. As described above, according to the present invention, the parallel multi-phase video signals are output in opposite polarities for each adjacent phase, and the polarities of the input side of the active matrix substrate 2 are inverted so that the active matrix substrate 2 is driven again with the same polarity. Therefore, it is possible to cancel the crosstalk component in the output stage of the external drive circuit 10 and the signal transmission portion to the active matrix substrate 2 in particular. Shape noise) can be improved. Next, a second embodiment of the present invention will be described. FIG. 3 is a block diagram showing a second embodiment of the liquid crystal display device according to the present invention. The same components as those shown in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted. In this embodiment, the polarity inverting circuits INV3, INV4, INV5, IN are provided on the video signal input side of the active matrix substrate 10.
V6, INV7, and INV8 are arranged. That is, here, the polarity inversion circuits INV1 and INV1 of the first polarity inversion circuit group 20 are used.
2 are provided on the input sides of the same input lines S1 and S3 as the connection lines X1 and X3 with the polarity inverting circuits INV3 and INV4 interposed therebetween, and the input and output sides of the polarity inverting circuits INV3 and INV4 are provided immediately. , A pair of polarity inversion circuits INV5, INV7 and INV6, INV8 are connected to the other input lines S2, S4, respectively.
Are interposed. As a result, the output signals to the output lines P1 and P3 subjected to the polarity inversion processing by the first polarity inversion circuit group 20 on the output side of the external drive circuit 10 are output to the second polarity inversion circuit group 2 respectively.
The polarity is inverted again on the input side of the active matrix substrate 2 by the 2 polarity inversion circuits INV3 and INV4. The output signals of the output lines P2 and P4, whose polarity is not inverted at the output side of the external drive circuit 10, are 2 at the input side of the active matrix substrate 2 respectively.
Polarity inverting circuits INV5, INV7 and INV connected in series
6, the polarity is maintained without being inverted as a result of the processing at INV 8. With the above configuration, the circuit outputs and transmissions of the adjacent phases are made to have the opposite polarities as in the first embodiment, and the polarities of the inputs to the column signal electrodes D1 to Dn and the polarity of the write voltage to each display pixel are all changed. The same polarity can be maintained. Further, on the input side of the active matrix substrate 2, signals are supplied to the column signal electrodes D1 to Dn for all phases via the same polarity inversion circuit. It is possible to realize a uniform sampling operation. As described above, according to the active matrix type liquid crystal display device of the present invention, the video signals that have been converted into parallel and multi-phase signals are inverted by the first polarity inversion circuit group for each adjacent phase. The polarity is output and the polarity is re-aligned by the polarity inversion in the second polarity inverting circuit group on the input side of the active matrix substrate. Can cancel the crosstalk component in the signal transmission part of
Degradation of display image quality (block noise) due to inter-phase crosstalk can be improved.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a first embodiment of an active matrix type liquid crystal display device of the present invention. FIG. 2 is a waveform chart showing signals of respective units in FIG. FIG. 3 shows a block diagram of a second embodiment of the liquid crystal display device according to the present invention. FIG. 4 is a configuration diagram showing a conventional active matrix type liquid crystal display device. FIG. 5 is a configuration diagram showing a display pixel. FIG. 6 is a diagram illustrating a phase expansion operation of a video signal. FIG. 7 is a waveform diagram showing a multi-phase video signal of a conventional liquid crystal display device. [Description of Signs] 2 ... Active matrix substrate, 4 ... Column signal electrode drive circuit, 8 ... Row scan electrode drive circuit, 10 ... External drive circuit, 1
2 ... timing generation circuit, 14 ... drive pulse generation circuit,
16 phase expansion circuit, 18 polarity inversion circuit, 20 first polarity inversion circuit group, 22 second polarity inversion circuit group, D1
Dn: column signal electrodes, G1 to Gm: row scanning electrodes, INV1
ＩＮINV8: polarity inversion circuit, P1 to P4: polyphase video signal output line, S1 to S4: video signal input line, PIX: display pixel, X1 to X4: connection line.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H04N 5/66 102 H04N 5/66 102B F term (Reference) 2H093 NA16 NA31 NC22 NC34 ND15 5C006 AC21 AC26 AF43 BB14 BB16 BC13 BC23 BF03 BF25 FA15 FA36 5C058 AA06 BA01 BA10 BA33 BB09 5C080 AA10 BB06 DD10 FF11 JJ02 JJ04

Claims (1)

Claims 1. A plurality of column signal electrodes, a plurality of row scan electrodes, and switching transistors and pixel electrodes arranged in a matrix at each intersection of the column signal electrodes and the row scan electrodes. A column signal electrode driving circuit including a shift register circuit and a switching circuit group for sequentially sampling display signals to the plurality of column signal electrodes; and supplying a row selection pulse to the plurality of row scanning electrodes. A row scan electrode driving circuit including a shift register circuit; and the column signal electrodes are grouped for each of N adjacent (a natural number of ≧ 2) column signal electrodes.
An active matrix substrate having N video signal input lines commonly connected to the corresponding column signal electrodes of the column signal electrodes via the switch circuit group; and Convert each signal into a parallel signal,
An external drive circuit for sending out to a multi-phase video signal output line connected to the video signal input line, and sequentially sampling the input video signal in parallel to the adjacent N column signal electrodes. In the active matrix display device, the connection line on the output side of the simultaneous parallel signal of the external drive circuit includes a first polarity inversion circuit group for inverting the polarity of the video signal in every other connection line array, A second polarity inversion circuit group for inverting the polarity of the video signal so that the video signal of all phases is supplied to the column signal electrode drive circuit with the same polarity on the input side of the video signal input line of the active matrix substrate; An active matrix type liquid crystal display device comprising: