KR100353555B1 - LCD source driver - Google Patents

Abstract

The present invention relates to an LCD source driver, which has an internal clock generator to generate a clock only while actually driving a pixel, and to generate a signal for driving one pixel even while driving a pixel, thereby suppressing large power consumption. The purpose is to make it effective. The LCD source driver according to the present invention for this purpose comprises an internal clock generator, a shift register, a data register, a sampling register, a hold register, a level shifter, a digital-to-analog converter, and an output buffer. The internal clock generator receives a chip enable signal, an external clock signal, and an N-th pixel output signal, and generates an internal clock signal only between an activation time of the chip enable signal and an inactivation time of the N-th pixel output signal. The shift register is operated by a chip enable signal and an internal clock signal to generate an Nth pixel output signal and a plurality of sequential data clock signals. The data register stores a digital video signal input in synchronization with an internal clock signal. The sampling register samples the digital video signal stored in the data register when it is sequentially input in synchronization with the data clock signal. The hold register stores the value sampled from the sampling register. The level shifter converts the digital video signal output from the hold register into a high voltage signal. The digital-to-analog converter converts the digital video signal output from the level shifter into an analog video signal. The output buffer delivers an analog video signal to each pixel of the LCD panel.

Description

LCD source driver

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor integrated circuits, and more particularly to an LCD source driver for driving the source side of a liquid crystal display (LCD).

When supplying a video signal to the liquid crystal display device, the video signal having the same polarity is not supplied continuously to one pixel Pixel and is alternately supplied. When a video signal of the same polarity is continuously supplied to one pixel, the liquid crystal of the pixel has a certain direction according to the polarity of the video signal, which shortens the life of the liquid crystal.

The LCD source driver converts the digital video signal into a negative digital video signal and a positive digital video signal, and then converts each of them into an analog video signal and supplies the same to each pixel. The negative digital video signal has a voltage level lower than the common voltage V _COM , and the positive digital video signal has a voltage level higher than the common voltage V _COM . In general, the common voltage V _COM is set to 5V, the positive video signal is set to 5 to 10V, and the negative video signal is set to 0 to 5V.

A method of driving an LCD panel using an LCD source driver includes a line inversion method, a column inversion method, and a dot inversion method. The line inversion method alternately inverts an LCD panel of a matrix structure in rows, and inverts polarities of video signals supplied to odd and even columns of the LCD panel. The column inversion method inverts an LCD panel in column units, and alternately inverts polarities of video signals supplied to odd and even columns of the liquid crystal display.

However, in the line inversion method and the column inversion method, flicker occurs as two adjacent columns or rows are alternately inverted. In order to solve this problem, a dot inversion method in which a line inversion method and a column inversion method are mixed is used. The dot inversion method staggers the polarities of the digital video signals supplied to neighboring cells of the LCD panel, thereby greatly reducing the degree of flicker. Since the application field of LCD panels is expanding to TV receivers and computer monitors in which the quality of output image is very important, the dot inversion method is mainly used to realize high quality images.

1 is a diagram illustrating a conventional LCD source driver.

As shown in FIG. 1, a conventional LCD source driver includes a shift register 104 and a data register 108, a sampling register 106, a hold register 110, a level shifter 112, and a digital-to-analog converter 114. And an output buffer 116.

The shift register 104 is operated by the chip enable signal CEIO and the external clock signal EXT_CLK to generate a data clock signal. The data clock signal output from the shift register 104 is output to the sampling register 106, and not all data clock signals are output simultaneously but sequentially. Each of the data clock signals sequentially output as described above controls the timing at which the digital video data RGB stored in the data register 108 is input to the sampling register 106. Each time one data clock signal dataclk is output, a digital video signal block for driving one pixel is input from the data register 108 to the sampling register 106.

The digital video signal RGB is input and stored in the data register 108.

The digital video signal RGB stored in the data register 108 is sequentially input to the sampling register 106, at which time the data clock signal output from the shift register 104 is used.

The hold register 110 converts and outputs the analog voltage of the digital video signal RGB stored in the sampling register 106 when the load signal LOAD is activated. But it still has a logic value as a digital video signal.

The level shifter 112 raises the level of the digital video signal output from the hold register 110 and converts the level into a high voltage signal.

The digital-to-analog converter 114 converts the digital video signal RGB into an analog video signal and outputs the analog video signal.

The analog video signal output from the digital-to-analog converter 114 drives unit pixels of the LCD panel.

In order to perform this series of steps correctly and accurately for each pixel, it is necessary to accurately synchronize the operation of each of the above-described elements constituting the LCD source driver to the clock signal. Therefore, the clock signal occupies a very large portion.

However, the conventional LCD source driver is configured to operate by the external clock signal EXT_CLK. The external clock signal EXT_CLK is continuously input even when the pixel is not actually driven. Because of this, even though the components involved do not actually drive the pixels, they continue to take preliminary operations, resulting in very high power consumption.

The LCD source driver according to the present invention has an internal clock generator to generate a clock only while driving a pixel, and to generate a signal for driving one pixel only while driving a pixel, thereby greatly reducing power consumption. Its purpose is to get it.

The LCD source driver according to the present invention for this purpose comprises an internal clock generator, a shift register, a data register, a sampling register, a hold register, a level shifter, a digital-to-analog converter, and an output buffer.

The internal clock generator receives a chip enable signal, an external clock signal, and an N-th pixel output signal, and generates an internal clock signal only between an activation time of the chip enable signal and an inactivation time of the N-th pixel output signal. The shift register is operated by a chip enable signal and an internal clock signal to generate an Nth pixel output signal and a plurality of sequential data clock signals. The data register stores a digital video signal input in synchronization with an internal clock signal. The sampling register samples the digital video signal stored in the data register when it is sequentially input in synchronization with the data clock signal. The hold register stores the value sampled from the sampling register. The level shifter converts the digital video signal output from the hold register into a high voltage signal. The digital-to-analog converter converts the digital video signal output from the level shifter into an analog video signal. The output buffer delivers an analog video signal to each pixel of the LCD panel.

1 is a diagram showing a conventional LCD source driver.

2 illustrates an LCD source driver according to the present invention.

3 is a logic circuit diagram illustrating a configuration of an internal clock generator of an LCD source driver according to the present invention.

4 is a timing diagram showing an operating characteristic of an internal clock generator of an LCD source driver according to the present invention;

5 is a logic circuit diagram showing a configuration of a shift register of an LCD source driver according to the present invention;

6 is a timing diagram showing an operating characteristic of a shift register of an LCD source driver according to the present invention;

Explanation of symbols on the main parts of the drawings

104, 204: shift register 106, 206: sampling register

108, 208: data register 110, 210: hold register

112, 212: level shifter 114, 214: digital-to-analog converter

116, 216: output buffer 202: internal clock generator

CEIO: Chip Enable Signal EXT_CLK: External Clock Signal

I_CLK: Internal Clock Signal Pixelout: Pixel Output Signal

dataclk: Data clock signal Pixel_live: Pixel enable signal

Live_clk: enable clock signal Chip_live: chip enable signal

An LCD source driver according to the present invention will be described with reference to FIGS. 2 to 6 as follows. 2 illustrates an LCD source driver according to the present invention.

As shown in FIG. 2, the LCD source driver according to the present invention includes an internal clock generator 202, a shift register 204, a data register 208, a sampling register 206, a hold register 210, and a level shifter 212. ), Digital-to-analog converter 214, and output buffer 216.

The internal clock generator 202 receives the chip enable signal CEIO, the external clock signal EXT_CLK, and the N-th pixel output signal PixelNout to operate to generate the internal clock signal I_CLK. The N th pixel output signal PixelNout is a signal output from the shift register 204.

The shift register 204 is operated by the chip enable signal CEIO and the internal clock signal I_CLK to generate a data clock signal. The data clock signal output from the shift register 104 is output to the sampling register 106, and not all data clock signals are output simultaneously but sequentially. Each of the data clock signals sequentially output as described above controls the timing at which the digital video data RGB stored in the data register 108 is input to the sampling register 106. Each time one data clock signal dataclk is output, a digital video signal block for driving one pixel is input from the data register 108 to the sampling register 106. The shift register 204 also generates a pixel output signal PixelNout, which is one of the input signals of the internal clock generator 202 described above.

The digital video signal RGB is input to and stored in the data register 208. The digital video signal RGB is input in synchronization with the internal clock signal I_CLK.

The digital video signal RGB stored in the data register 208 is sequentially input to the sampling register 206 in a pixel unit. At this time, the data clock signal dataclk output from the shift register 204 is used.

The hold register 210 outputs the analog voltage of the digital video signal RGB stored in the sampling register 206 when the load signal LOAD is activated. But it still has a logic value as a digital video signal.

The level shifter 212 raises the level of the digital video signal output from the hold register 210 and converts the level into the high voltage signal.

The digital-analog converter 214 converts the digital video signal RGB into an analog video signal and outputs the analog video signal.

The analog video signal output from the digital-to-analog converter 214 is transmitted to each pixel of the LCD panel through the output buffer 216.

The configuration and operation of the internal clock signal I_CLK of the LCD source driver according to the present invention will be described with reference to FIGS. 3 and 4 as follows. 3 is a logic circuit diagram illustrating an internal clock generator of an LCD source driver according to the present invention, and FIG. 4 is a timing diagram illustrating an operation characteristic of an internal clock generator of an LCD source driver according to the present invention.

First, as shown in FIG. 3, the internal clock generator 202 of the LCD source driver according to the present invention inputs the chip enable signal CEIO, the last pixel output signal PixelNout, and the external clock signal EXT_CLK. It receives and operates to generate the internal clock signal I_CLK.

The de flip-flop 304 operates at a rising edge of the clock signal, and the data input terminal D is connected to the power supply voltage VDD so that a data signal of a high level (logic 1) is always input. The chip enable signal CEIO is input to the clock input terminal. The chip enable signal CEIO outputs an output data signal Q301 having a high level (logic 1) at each rising edge of the chip enable signal CEIO.

The de flip-flop 306 operates at the falling edge of the clock signal. Since the data input terminal D is connected to the power supply voltage VDD, the data signal of a high level (logic 1) is always input. The last pixel output signal PixelNout is input to the clock input terminal. The output data signal Q302 of a high level (logic 1) is output at every falling edge of the pixel output signal PixelNout. The de flip-flop 306 also has a high level reset terminal R, which is reset when the chip enable signal CEIO is at a high level.

An output data signal Q301 of the de-flip flop 304 and an output data signal Q302 of the de-flip flop 306 are input to the AND gate 310, and an output data signal Q302 of the de flip-flop 306. Is inverted by the inverter 308 and input. The output signal of the AND gate 310 is a chip activation signal Chip_live.

The chip activation signal Chip_live and the external clock signal EXT_CLK are input to the AND gate 312. The output signal of this AND gate 312 is an internal clock signal I_CLK.

The de flip-flop 304 generates a high level output data signal Q301 at the rising edge of the chip enable signal CEIO, so that one of the inputs of the AND gate 310 becomes a high level, that is, a logic one. At this time, another de flip-flop 306 is reset by the chip enable signal CEIO to generate an output data signal Q302 having a low level, that is, a logic zero. The output data signal Q302 of logic 0 is inverted to logic 1 by the inverter 308 and input to the AND gate 310. Therefore, both inputs of the AND gate 310 become logic 1, and the chip activation signal Chip_live becomes logic 1.

While the chip activation signal Chip_live maintains the logic 1 state, the logic value of the internal clock signal I_CLK output from the AND gate 312 is determined by the external clock signal EXT_CLK. That is, while the chip enable signal Chip_live is logic 1, the internal clock signal I_CLK and the external clock signal EXT_CLK are the same.

According to the internal clock signal I_CLK, the pixel output signal Pixelout of the shift register 204 is sequentially generated, and when the falling edge of the last pixel output signal PixelNout is reached, the second de-flip flop 306 is generated. The output data signal Q302 of logic 1 is outputted to make the chip activation signal Chip_live output from the AND gate 310 as logic 0. For this reason, the internal clock signal I_CLK output from the AND gate 312 is also fixed to logic zero.

As described above, the internal clock signal I_CLK has the same frequency and phase as the external clock signal EXT_CLK from the time when the chip enable signal CEIO is activated to the falling edge of the last pixel output signal PixelNout. After the falling edge of the last pixel output signal (PixelNout) until the next chip enable signal (CEIO) generation time is fixed to a logic value of zero.

The configuration and operation of the shift register of the LCD source driver according to the present invention will be described with reference to FIGS. 5 and 6 as follows. 5 is a logic circuit diagram illustrating a shift register of an LCD source driver according to the present invention, and FIG. 6 is a timing diagram illustrating an operation characteristic of a shift register of an LCD source driver according to the present invention.

As shown in Fig. 5, the shift registers of the LCD source driver according to the present invention are all composed of N data clock generators 502. All data clock generators 502 are connected in series with each other, and one data clock signal dataclk is generated in each data clock generator 502. The data clock generator 502 is configured to receive and operate the pixel output signal Pixelout generated by the preceding data clock generator.

The configuration of the first data clock generator 502a is as follows.

The chip enable signal CEIO is input to the three-input OR gate 504a, and the pixel activation signal Pixel1_live output from the OR gate 504a is input to the AND gate 506a together with the internal clock signal I_CLK. . The activation clock signal Live_clk1 output from the AND gate 506a is input as a clock signal of the de-flop flop 508a. The de flip-flop 508a generates an output at the falling edge of the activation clock signal Live_clk1. The chip enable signal CEIO is input to the data input terminal D of the de flip-flop 508a. The output data signal Q of the de-flop flop 508a is input to the or gate 504a and the data input terminal D of the de-flop flop 510a. The activation clock signal Live_clk1 is input to the clock input terminal of the de flip-flop 510a. The de flip-flop 510a generates an output at the rising edge of the activation clock signal Live_clk1. The output data signal Q of the de flip-flop 510a is a pixel output signal Pixel1out, which is input to the or gate 504b and the de-flop-flop 508b of the next data clock generator 502b. Each output data signal Q output from the two de-flip flops 508a and 510a is input to the AND gate 512a, and the first data clock signal dataclk1 is output from the AND gate 512a. do

The operation of the data clock generator 502 of the shift register 204 configured as described above will be described with reference to FIGS. 5 and 6. When the chip enable signal CEIO becomes logic 1 (high level), the pixel activation signal Pixel1_live output from the OR gate 504a is also logic 1. Therefore, the activation clock signal Live_clk1 output from the AND gate 506a is equal to the internal clock signal I_CLK. At the falling edge of the activation clock signal Live_clk1, the output data signal Q1 of logic 1 is output from the first de-flip flop 508a and input to the or gate 504a and the second de-flip flop 510a. Subsequently, at the rising edge of the activation clock signal Live_clk1, the output data signal of logic 1, that is, the pixel output signal Pixel1out, is output from the second flip-flop 510a. The output data signal Q1 of the first de flip-flop 508a and the pixel output signal Pixel1out of the second de flip-flop 510a are input to the AND gate 512a, and the data clock at this AND gate 512a. The signal dataclk1 is output.

In FIG. 6, when the chip enable signal CEIO is activated, the internal clock signal I_CLK is generated. On the first falling edge of the internal clock signal I_CLK, the output data signal Q1 is output at the de-flip flop 508a of FIG. 5, and at the next rising edge, the pixel output signal Pixel1out at the second de-flip flop 510a. ) Is output. The pixel enable signal Pixel1_live has a pulse width from the point at which the chip enable signal CEIO is activated to the falling edge of the pixel output signal Pixelout. The data clock generator 502a operates only during this time. It doesn't work.

The configuration and operation of the second data clock generator 502b is the same as the first data clock generator 502a described above. However, the second data clock signal dataclk2 and the pixel output signal Pixel2out are generated by operating by the pixel output signal Pixel1out output from the front end instead of the chip enable signal CEIO.

As a result, the pixel output signal Pixel1out and the data clock signal dataclk1, which are outputs of the first data clock generator 502a, are generated and the second data clock generator 502b is operated to operate with the pixel output signal Pixel2out. The data clock signal dataclk2 is generated, and at the same time, the third data clock generator 502c operates to generate the pixel output signal Pixel3out and the data clock signal dataclk3. This series of operations is performed sequentially with the rest of the data clock generator.

When the operation of the last data clock generator 502N is completed to generate the last data clock signal dataclkN and the pixel output signal PixelNout, as described in the description of FIG. 3, at the falling edge of the pixel output signal PixelNout. The internal clock signal I_CLK is not generated until the internal clock generator 202 is initialized and the next chip enable signal CEIO is activated.

The LCD source driver according to the present invention has an internal clock generator to generate a clock only while driving a pixel, and to generate a signal for driving one pixel only while driving a pixel, thereby greatly reducing power consumption. Its purpose is to get it.

Claims (6)

An internal clock generator configured to receive a chip enable signal, an external clock signal, and an N-th pixel output signal, and generate an internal clock signal only between an activation time of the chip enable signal and an inactivation time of the N-th pixel output signal; A shift register operated by the chip enable signal and the internal clock signal to generate the Nth pixel output signal and a plurality of sequential data clock signals; A data register for storing a digital video signal input in synchronization with the internal clock signal; A sampling register for sampling the digital video signal stored in the data register when it is sequentially input in synchronization with the data clock signal; A hold register for storing a value sampled from the sampling register; A level shifter for converting the digital video signal output from the hold register into a high voltage signal; A digital-to-analog converter for converting the digital video signal output from the level shifter into an analog video signal; And an output buffer for transmitting the analog video signal to each pixel of the LCD panel. The method according to claim 1, wherein the internal clock generator, A first de flip-flop in which a data signal of logic 1 is always input, the chip enable signal is input as a clock signal, and an input / output of the data signal is performed at a rising edge of the chip enable signal; A data signal of logic 1 is always input, the N-th pixel output signal is input as a clock signal, an input / output of the data signal is performed at the falling edge of the N-th pixel output signal, and the chip enable signal is at a high level. A second de flip-flop that is reset when; A first logic gate for generating a chip activation signal by performing an AND operation on the inverted signal of the output data signal of the first di flip-flop and the output data signal of the second di flip-flop; And a second logic gate configured to receive the chip activation signal of the first logic gate and the external clock signal and to perform an AND operation to generate the internal clock signal. The method of claim 1, wherein the shift register, A sequential circuit including at least one memory device, comprising: a first data clock generator configured to receive and operate the chip enable signal and the internal clock signal to generate a first pixel output signal and a first data clock signal; A sequential circuit including at least one memory device, the at least one second data configured to receive and operate the first pixel output signal and the internal clock signal to generate a second pixel output signal and a second data clock signal. A clock generator; A sequential circuit including at least one memory device, the N-1 pixel output signal and the internal clock signal output from an N-1 data clock generator connected to a front end thereof are operated to receive the Nth pixel output signal, and And an Nth data clock generator configured to generate an Nth data clock signal. The method of claim 3, wherein the first data clock generator, A first or gate having at least two inputs including the chip enable signal and outputting a first pixel activation signal; A third AND gate receiving the first pixel activation signal and the internal clock signal and outputting a first activation clock signal; The chip enable signal is input as a data signal, the first activation clock signal is input as a clock signal to operate at a falling edge of the first activation clock signal to generate a first output data signal, and the first output data. A third de flip-flop configured to input a signal to the first or gate; The first output data signal is input as a data signal, the first activation clock signal is input as a clock signal to generate the first pixel output signal, and the first pixel output signal is input to the first or gate. A fourth di flip-flop; And a fourth AND gate configured to receive the first output data signal and the first pixel output signal to generate the first data clock signal. The method of claim 3, wherein the second data clock generator, A second or gate for receiving the first pixel output signal and generating a second pixel activation signal; A fifth AND gate receiving the second pixel activation signal and the internal clock signal to generate a second activation clock signal; The chip enable signal is input as a data signal, and the second activation clock signal is input as a clock signal to operate at a falling edge of the second activation clock signal to generate a second output data signal, and the second output data. A fifth de flip-flop configured to input a signal to the second or gate; The second output data signal is input as a data signal, the second activation clock signal is input as a clock signal to generate the second pixel output signal, and the second pixel output signal is input to the second or gate. A sixth di flip-flop; And a sixth AND gate configured to receive the second output data signal and the second pixel output signal and generate the second data clock signal. The method of claim 3, wherein the N-th data clock generator, A third or gate configured to receive an N-1th pixel output signal output from an N-1th data clock generator connected to the front end and generate an Nth pixel activation signal; A seventh AND gate configured to receive the Nth pixel activation signal and the internal clock signal and generate an Nth activation clock signal; The chip enable signal is input as a data signal, and the Nth activation clock signal is input as a clock signal to operate at a falling edge of the Nth activation clock signal to generate an Nth output data signal, and the Nth output data. A seventh de flip-flop configured to receive a signal into the third or gate; The Nth output data signal is input as a data signal, the Nth activation clock signal is input as a clock signal to generate the Nth pixel output signal, and the Nth pixel output signal is input to the third or gate. An eighth di flip-flop; And an eighth AND gate configured to receive the Nth output data signal and the Nth pixel output signal and generate the Nth data clock signal.