JPH08305322A - Display device - Google Patents

Abstract

PURPOSE: To reduce deformation or noises in data signal and to realize a high resolution display by supplying a same data signal in multiple data signal lines and also connecting each line with different sampling circuits through different buffer circuits. CONSTITUTION: Data signal from a data signal line 12 is supplied to a sample holding circuits 11 from the data signal lines 16-18 connected through buffer circuits 13-15, and the data signal is sampled in accordance with the sampling pulses from a source shift register 10. Namely, a same data signal is branched into three, which are individually sampled. Sampling switches 19-23 are provided so that sampling switches connected with a same data signal line, for example, the sampling switches 19 and 22 connected with the data signal line 16, are not simultaneously turned ON. This means that the individual sampling switches 19-23 are loose in electric coupling with each other.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device such as a liquid crystal display device.

[0002]

2. Description of the Related Art Conventionally, as a display device, for example, a liquid crystal display device (hereinafter referred to as LCD), as shown in FIG. 12, a display portion 101 having a plurality of picture element portions 104 ...
It is configured by a source driver 102 and a gate driver 103 as a drive circuit for driving each picture element portion 104.

Each of the picture element portions 104 is arranged at a portion orthogonal to a plurality of source bus lines 105 connected to the source driver 102 and a plurality of gate bus lines 106 connected to the gate driver 103. ing. Therefore, the arrangement of the picture element units 104 ...
It becomes a matrix above.

Further, the picture element portion 104 is a TFT (Thin film).
a pixel transistor 107 composed of a transistor), a pixel capacitor 108, and an additional capacitor 109, and the gate terminal of the pixel transistor 107 is a gate bus line 106.
The source terminal is connected to the source bus line 105, and the drain terminal is connected to the pixel capacitor 108 and the additional capacitor 109.

The source driver 102 is composed of a shift register 110, a sampling switch 111 composed of a transistor, a sampling capacitor 112, a data signal line 113 and the like.
1, sampling capacitor 112, data signal line 11
3 and the source bus line 105 form a sample hold circuit 114.

A start pulse (SP) and a drive clock (CK, / CK) are input to the shift register 110, and the input SP is sequentially shifted according to CK, / CK and is applied to the sample hold circuit 114. Is output.

The gate driver 103 has a shift register 115 and sequentially outputs a scanning signal to each gate bus line 106 ...

The display unit 101 and the source driver 1
02 and the gate driver 103 may be monolithically formed on the same substrate, or only the display unit 101 may be formed on an insulating substrate.

The operation of the display device having the above structure will be described below. First, the SP input to the shift register 110 of the source driver 102 is sequentially shifted by CK and / CK, output to the sample hold circuit 114, and becomes a sampling pulse in the sample hold circuit 114. Then, the sampling switch 111 is turned on by the input sampling pulse,
The data signal on the data signal line 113 at the time when this sampling pulse is input is sampled.

The data signal sampled by the sampling pulse is sent to the sampling capacitor 1
It is held at 12 and is output to the source bus line 105 as a source bus line signal.

On the other hand, the output of each digit in the shift register 115 of the gate driver 103 is sequentially output to the gate bus lines 106 ... As a scanning signal (gate bus line signal) and connected to the selected gate bus line 106. 107 is turned on, and the source bus line signal at that time is sequentially written as image data in the picture element capacitor 108 and the additional capacitor 109.

Then, a desired display is performed by driving the liquid crystal corresponding to each picture element portion 104.

Therefore, in the LCD having the above structure, as described above, the source driver 102 is of the panel sample hold type in which the display unit 101 holds the image data. In an LCD having such a source driver 102, when the number of picture element portions 104 in the horizontal scanning direction increases, the picture element portion 104 connected to the lowest digit and the picture element portion 104 connected to the highest digit of the shift register 110 are The writing time of image data is different. Therefore, the writing time of the image data can be lengthened in the picture element unit 104 connected to the upper digit of the shift register 110, but the writing time of the image data cannot be sufficiently taken in the picture element unit 104 connected to the lower digit. The problem arises.

Therefore, in order to solve the above problem, an LCD using a source driver of a driver sample hold type for holding image data on the source driver side has been proposed.

An LCD using the source driver of the driver sample hold method will be described below. In this LCD, except for the source driver, FIG.
It is assumed that the display unit 101 and the gate driver 103 are the same as those of the LCD shown in FIG. 3, and the description here will be made only for the source driver of the driver sample hold method.

The source driver of the above-mentioned driver sample-hold system is provided on the output side of the sample-hold circuit 114 of the source driver 102 shown in FIG. 12, as shown in FIG. 13, with a transfer switch 116, a hold capacitor 117, a buffer circuit 118 and a transfer circuit. The transfer circuit 120 including the signal line 119 is connected.

That is, the sample and hold circuit 114 outputs 1
When the data for the scanning line is sampled, the transfer signal is output from the transfer signal line 119 in the transfer circuit 120, the transfer switch 116 is turned on, and the sample hold circuit 1 is turned on.
After the data held in the 14 sampling capacitors 112 are transferred to the hold capacitors 117 all at once,
Sampling for the next scanning period is performed.

That is, while the data for the next one scanning line is being sampled, the previous sampling data for one scanning line held in the hold capacitor 117 is sourced via the buffer circuit 118 as a source bus line signal. It continues to be applied to the bus line 105 (FIG. 12).

As described above, by using the driver sample-hold type source driver, even if the number of picture element portions 104 in the horizontal scanning direction increases, each picture element portion 1
Sufficient time for writing the image data to 04. As a result, the writing time of the image data can be made substantially the same between the picture element portion 104 connected to the lowest digit and the picture element portion 104 connected to the highest digit of the shift register 110.

Further, when the LCD is formed on an insulating substrate in a driver monolithic manner, p-SiTFT is used.
The speed at which the shift register formed by using the above is stably operated at about several MHz, and the operation speed of the shift register in the shift register in the source driver of the LCD, which requires a high-speed operation and has a large number of horizontal picture elements. There is a problem such as shortage.

Therefore, in order to reduce the operating speed of the shift register, for example, as shown in FIG. 14, a plurality of systems, in this case, four systems of shift registers 131 to 134 are provided, and each of the shift registers 131 to 134 is provided. , CK1 to CK4 and / CK1 to / CK4 having different phases are proposed to operate the source shifters 131 to 134 at low speeds while keeping the entire shift speed.

The above-mentioned four systems of shift registers 131 to 13
In the source driver having 4 as shown in FIG.
Start pulse SP is CK1 to CK4, / CK1 to / C
Sampling pulse SMP by sequentially shifting by K4
1 to SMP8 are output. The SMP1 output from the four shift registers 131 to 134
The width of each of the SMP8 to SMP8 is four times as large as that of one shift register, but the phase shift of each SMP1 to SMP8 is the same as that of one shift register.

[0023]

However, in the source driver having the above-mentioned four systems of shift registers 131 to 134, as shown in FIG.
MP1 to SMP8 overlap each other. Therefore, at a certain moment, the eight sampling transistors 111 ... Are always on. That is, for the data signal line 113 or the data signal output circuit, the capacity of the eight sampling capacitors 112 ... Is a load via the sampling transistors 111. Further, since the data signal line 113 has wiring resistance and the sampling transistor 111 has ON resistance, the response of the data signal in each sampling capacitor 112 deteriorates due to the action of the time constant of the RC integrating circuit. The waveform is more blunt than the data signal of.

In the sampling of the data signal based on the waveform thus formed, the band information originally possessed by the data signal is lost, so that the display has a low horizontal resolution. Further, in the scanning signal (not shown),
Depending on the configuration, two adjacent outputs of the gate shift register overlap each other, and the same problem occurs in the picture element portion as in the sampling portion of the source driver described above.

In order to prevent such a problem, a display device has been proposed in which a video signal line is provided for each shift register 131-134. In this case, for example, the Nth (SMP1) falling edge of the sampling pulse and the N + 8th (SMP9) rising edge of the sampling pulse shown in FIG. 15 have the same timing, but in reality, due to rounding or delay of the signal waveform. , Nth sampling transistor 1
A phenomenon occurs in which the N + 8th sampling transistor 111 is simultaneously turned on before 11 is completely turned off.

When such a phenomenon occurs, as described above, even if the video signal line is divided into a plurality of pieces, the sampling data of the Nth sample hold circuit 114 of the source driver is not only the N + 4 sampling signal but also the N + 4 sampling signal.
It is also affected by the eighth sampling data, which adversely affects the display as a ghost phenomenon or noise.

Further, the above-mentioned phenomenon can similarly occur in the display section. Therefore, for example, the applicant of the present application has proposed, in Japanese Patent Application No. 5-300537, a display device in which the same video signal line is branched into a plurality outside the drive circuit.
In this way, by dividing the same video signal line into a plurality of parts outside the drive circuit, a plurality of sampling circuits connected to one video signal line do not turn on at the same time. The rounding of the signal in the signal line is reduced to improve the resolution of the display device.

By the way, even if the same video signal line is simply divided into a plurality of parts, if they are divided into a plurality of parts on the same substrate as the panel, the contact resistance with the flexible substrate, the wiring resistance, and further the video signal. The output impedance of the source can increase the time constant, but cannot completely suppress the occurrence of ghosts. Even if the same video signal line is simply divided into a plurality of parts outside the panel, the time constant can be increased due to the contact resistance with the flexible substrate and the like, the wiring resistance, and the output impedance of the video signal supply source. , It is not possible to completely suppress the occurrence of ghosts.

Looking at the sampling circuit connected to the same data signal line that constitutes the source driver, although the OFF resistance exists in the sampling transistor, if the OFF resistance of the sampling transistor is not sufficiently large, the sampling capacitor becomes The written sampling data is the OFF resistance of the transistor,
This causes a problem of mutual crosstalk through the data signal lines.

The present invention has been made in view of the above problems, and an object thereof is to reduce the distortion of a data signal and the noise of a data signal due to simultaneous turn-on of adjacent transistors. O of transistor
To provide a display device capable of reducing crosstalk due to lack and deterioration of FF characteristics, preventing a ghost phenomenon, and realizing high resolution display while suppressing deterioration of display resolution due to deterioration of horizontal resolution and crosstalk. is there.

[0031]

A display device according to claim 1 is
A plurality of data signal lines to which data signals are respectively supplied, a plurality of sampling circuits for sampling the data signals supplied from the plurality of data signal lines, and a plurality of data buses connected to the plurality of sampling circuits, respectively. Line, a plurality of picture element portions connected to the plurality of data bus lines and arranged in a matrix, and a drive circuit including the sampling circuit and driving the data bus line. At least two of the data signal lines are supplied with the same data signal and are connected to different sampling circuits via different buffer circuits.

According to a second aspect of the present invention, in the display device according to the first aspect, among the plurality of sampling circuits, the sampling circuit whose sampling timing is synchronized is
It is characterized in that they are connected to different data signal lines and the ON periods of the respective sampling circuits do not overlap with each other in terms of time.

The display device according to claim 3 is the display device according to claim 1 or 2.
In the display device described above, the buffer circuit is formed on the same substrate as the sampling circuit.

According to another aspect of the display device of the present invention, a plurality of data signal lines to which data signals are respectively supplied, a plurality of sampling circuits for sampling the data signals supplied from the plurality of data signal lines, and a plurality of the plurality of sampling circuits. A plurality of data bus lines respectively connected to the sampling circuit, a plurality of picture element portions connected to the plurality of data bus lines and arranged in a matrix, and the sampling circuit, A driving circuit for driving the data signal line, and the data signal line is divided into a plurality of lines in the horizontal direction of the display, and each divided signal line is connected to a sampling circuit through a different buffer circuit. Is characterized by.

According to another aspect of the display device of the present invention, a plurality of data signal lines to which data signals are respectively supplied, a plurality of sampling circuits for sampling the data signals supplied from the plurality of data signal lines, and a plurality of the plurality of sampling circuits. A plurality of data bus lines respectively connected to the sampling circuit, a plurality of picture element portions connected to the plurality of data bus lines and arranged in a matrix, and the sampling circuit, A plurality of picture element portions that are adjacent to each other in the column direction among the plurality of picture element portions, and different data bus lines are connected to the picture element portions; It is characterized in that the same sampling circuit is connected via.

A display device according to claim 6 is the display device according to claim 1,
In the display device according to 3, 4, or 5, a drive circuit,
It is characterized in that the image display portion including a plurality of picture element portions is monolithically formed on the same substrate.

[0037]

According to the structure of claim 1, at least two of the plurality of data signal lines are supplied with the same data signal and are connected to different sampling circuits via different buffer circuits. The electrical connection between the adjacent sampling circuits to which the same data signal is supplied can be reduced.

As a result, even if the adjacent sampling circuits to which the same data signal is supplied are simultaneously turned on, the noise generated at this time affects other adjacent sampling circuits to which the same data signal is supplied. Will not give. That is, the noise prevents the erroneous data signal from being sampled.

Further, since the adjacent sampling circuits are not connected to the same data signal line, the load on one data signal line can be reduced, so that the rounding of the data signal can be reduced.

Therefore, in the adjacent sampling circuits, there is no erroneous sampling due to rounding of the data signal,
Moreover, it is possible to always sample an accurate data signal and supply the sampled data signal to the data bus line without being affected by the ON / OFF state of each other. Crosstalk due to defects can be reduced. Therefore,
It enables high-resolution display that suppresses the deterioration of display quality due to crosstalk.

According to the structure of claim 2, the sampling circuits whose sampling timings are synchronized are connected to different data signal lines, and the ON periods of the respective sampling circuits do not overlap each other, so that one sampling circuit is provided. It is possible to reduce noise generated when other sampling circuits are turned on at the moment when is turned off.

According to the structure of claim 3, since the buffer circuit connected to the sampling circuit is formed on the same substrate as the sampling circuit, a flexible substrate or the like for connecting the buffer circuit and the sampling circuit. It is possible to suppress deterioration of the data signal due to contact resistance, wiring resistance, and the like. In addition, it is possible to suppress an increase in the number of connection terminals for connecting the buffer circuit and the sampling circuit, and it is possible to improve reliability associated with mounting.

According to the structure of claim 4, the data signal line is divided into a plurality of lines in the horizontal direction of the display, and each divided signal line is connected to the sampling circuit via a different buffer circuit. Therefore, the load on the data signal line can be reduced. As a result, the resistance and capacitance of the data signal line can be reduced, so that deterioration of the data signal on the data signal line can be further reduced and noise at the time of sampling can be reduced.

According to the structure of claim 5, different data bus lines are connected to the plurality of picture element portions adjacent to each other in the column direction among the plurality of picture element portions, and these data bus lines are connected to these picture element portions. Since the same sampling circuit is connected via the buffer circuit, it is possible to suppress the interference between the picture element portions adjacent in the column direction. As a result, crosstalk between the picture element portions can be reduced, so that the display quality can be improved.

According to the sixth aspect of the invention, the drive circuit and the image display section including a plurality of picture element sections are monolithically formed on the same substrate, so that the pixel transistors are driven in accordance with the increase in screen size. It is possible to improve the power and reduce the mounting cost of the drive IC.

[0046]

【Example】

[Embodiment 1] One embodiment of the present invention will be described with reference to FIGS.
The explanation is based on the following. In this embodiment, a liquid crystal display device (hereinafter referred to as LCD) will be described as a display device, and the same applies to other embodiments described later.

As shown in FIG. 2, the LCD according to the present embodiment serves as a display unit 1 having a plurality of picture element portions 4 arranged in a matrix and a drive circuit for driving each picture element portion 4. Of the source driver 2 and the gate driver 3.

In the display unit 1, a plurality of source bus lines 5 connected to the source driver 2 and a gate driver 3 are connected.
Are arranged so as to be orthogonal to each other, and the pixel portion 4 is arranged at the intersection of the source bus line 5 and the gate bus line 6. That is, the display unit 1 drives the picture element unit 4 by the data signal such as the video signal from the source driver 2 and the scanning signal from the gate driver 3 to change the alignment state of the liquid crystal of the liquid crystal layer (not shown) to obtain a desired signal. It is designed to display an image.

The picture element portion 4 is a TFT (Thin film trans
a pixel transistor 7 composed of istor), a pixel capacitor 8 and
The pixel terminal of the pixel transistor 7 is connected to the gate bus line 6, the source terminal is connected to the source bus line 5, and the drain terminal is connected to the pixel capacitor 8 and the additional capacitor 9. That is, when the pixel transistor 7 is turned on by the scanning signal, the source bus line signal (video signal) from the source bus line 5 is written in the pixel capacitor 8 and the additional capacitor 9.

The source driver 2 is provided with a source shift register 10 and a sample hold circuit 11 for sampling the data signal from the data signal line 12 by the sampling pulse from the source shift register 10. The data signal line 12 is branched into three in the source driver 2 and connected to the three data signal lines 16 to 18 via the buffer circuits 13 to 15. Although the buffer circuits 13 to 15 are provided in the source driver 2 in the present embodiment, the present invention is not limited to this and may be provided outside. That is, the data signal line 12
May be branched outside the source driver 2 instead of being branched inside the source driver 2.

A start pulse (SP) and a drive clock (CK, / CK) are input to the source shift register 10, and the input SP is sequentially shifted according to CK and / CK, and is sampled as a sampling pulse. It is output to the hold circuit 11.

As shown in FIG. 1, the sample and hold circuit 11 is supplied with the data signal from the data signal line 12 from three data signal lines 16 to 18 connected through buffer circuits 13 to 15, and The data signal is sampled according to the sampling pulse from the source shift register 10. That is, the same data signal is branched into three, and each signal is sampled separately.

The sample and hold circuit 11 has sampling switches 19 to 23 formed of TFTs for sequentially sampling a data signal according to the sampling pulse of the source shift register 10, and hold capacitors 24 to 28 for holding the sampled data. are doing. In addition, one sampling switch and one sampling capacitor connected thereto constitute one sampling circuit.

The output lines 10a from the source shift register 10 are connected to the gate terminals of the sampling switches 19 to 23, and the data signal lines branched from one data signal line 12 are connected to the source terminals. 16
To 18 are respectively connected. That is, the data signal line 16 is connected to the source terminal of the sampling switch 19, the data signal line 17 is connected to the source terminal of the sampling switch 20, and the data signal line 18 is connected to the source terminal of the sampling switch 21. Connected again to the source terminal of the sampling switch 19,
The data signal line 16 is connected, and thereafter, the data signal lines 16 to 18 are repeatedly connected in order.

As described above, the sampling switches 19 to 23 are connected so that the sampling switches connected to the same data signal line, for example, the sampling switch 19 and the sampling switch 22 connected to the data signal line 16 are not turned on at the same time. Has been done. That is,
The sampling switches 19 to 23 are sparsely electrically connected to each other.

The operation of the LCD having the above structure will be described below with reference to the operation timing chart of FIG.

First, for one scanning period, the SP input to the source shift register 10 of the source driver 2 is
It is sequentially shifted by CK and / CK and output to the sample hold circuit 11, and becomes a sampling pulse in the sample hold circuit 11. Then, each sampling switch 19 to 23 is turned on by the input sampling pulse, and the data signals on the data signal lines 16 to 18 at the time when the sampling pulse is input are sampled.

Then, each data signal sampled by the sampling pulse is applied to each hold capacitor 2
4 to 28, and is output to the source bus lines 5 ... As a source bus line signal.

On the other hand, the output of each row in the gate driver 3 is sequentially output to the gate bus lines 6 as a scanning signal (gate bus line signal), and the picture element transistors 7 connected to the selected gate bus line 6 are turned on, At that time, the source bus line signal from the source bus line 5 in one scanning period is sequentially written as image data in the pixel capacitor 8 and the additional capacitor 9.

Then, a desired display is performed by driving the liquid crystal corresponding to each picture element portion 4.

In the next scanning period, the source bus line signal with the voltage polarity reversed is written in the picture element capacitor 8 and the additional capacitor 9 as image data. In this way, each time the scanning period is switched, the voltage polarity of the source bus line signal is inverted and written as image data in the picture element capacitor 8 and the additional capacitor 9, and each time, the picture element portion 4 is dealt with. A desired display is performed by driving the liquid crystal.

Therefore, as shown in FIG. 3, when the SP is input to the source driver 2, the sampling pulses SMP1 to SMP5 are shifted in phase by 1/2 according to the input timing of CK and / CK. It is designed to output. As a result, the sampling pulses SMP1 to SMP5 have a temporal overlap, so that two adjacent sampling switches are always in the ON state.

However, in this embodiment, the sampling switches 19 to 23 are not electrically connected to each other. That is, since two adjacent sampling switches are not connected to the same data signal line, the load on one data signal line can be reduced from two sampling capacitors to one. As a result, rounding of the data signal due to the load on the data signal line can be reduced.

Furthermore, since the phases of the sampling pulses are shifted by 1/2, as shown in FIG. 3, the falling edge of the sampling pulse SMP1 and the rising edge of the sampling pulse SMP3 should not overlap in time. Has become. Actually, due to the rounding and delay of the sampling pulse, a time occurs in which the sampling transistor 19 and the sampling transistor 21 are simultaneously turned on.

In this case, the sampling transistor 19
And the sampling transistor 21 are connected to the same data signal line, the sampling transistor 19
Is turned off, an erroneous data signal is sampled under the influence of noise generated when the sampling transistor 21 is turned on.

However, in the present embodiment, as shown in FIG. 1, since the sampling transistor 19 and the sampling transistor 21 are connected to different data signal lines, the sampling pulse is rounded or delayed as described above. It is possible to sample an accurate data signal without being affected by the generated noise.

As described above, the adjacent sampling transistors are not affected by the ON / OFF state of each other, and an accurate data signal can always be supplied to the source bus line 5 as the source bus line signal. Can be reduced.

Therefore, the LCD of the present embodiment enables high resolution display in which the deterioration of the display quality due to the ghost phenomenon caused by the distortion of the data signal and the noise is suppressed.

In this embodiment, the data signal line 12 is set to 3 so that the sampling switches 19 to 23 of the source driver 2 are electrically connected as loosely as possible.
After branching into two, the data signals are supplied from the data signal lines 16 to 18 to the respective sampling switches 19 to 23 via the buffer circuits 13 to 15.

However, the above-mentioned buffer circuit 13
Is not limited to the above, but the data signal line 12 is branched into three without providing the buffer circuits 13 to 15, and then the data signal is directly input to each sampling switch 19.
23 to 23 may be supplied. In this case, the buffer circuit 13
Each sampling switch 1 than through
Since 9 to 23 are less likely to become electrically sparse, the effect is halved.

Further, in the present embodiment, the sampling method in the source driver 2 is the panel sample hold method in which the display unit 1 side holds the image data as the data signal, but the source driver side holds the image data. The same can be applied to the source driver of the driver sample hold method, and the same effect can be obtained. In this case, by using the driver sample hold type source driver, it is possible to take a sufficient time for writing the image data in the pixel portion connected to the source driver.

[Embodiment 2] Another embodiment of the present invention will be described below with reference to FIG. For convenience of explanation, members having the same functions as those in the first embodiment are designated by the same reference numerals, and the description thereof will be omitted. The same applies to each of the following embodiments. Further, in this embodiment,
The configuration applied to the source driver 2 of the first embodiment is LC
A case where it is applied to the display unit 1 of D will be described.

The LCD according to this embodiment includes the source bus lines 5 ... Connected to the source driver 2 of the first embodiment.
However, as shown in FIG. 4, in front of the display unit 1, it is branched into three and connected to the source bus lines 34 to 36 via the three buffer circuits 31 to 33, respectively. In FIG. 4, the horizontal direction is the row direction and the vertical direction is the column direction.

The source terminals of the pixel transistors 7 arranged in the column direction are connected to the source bus lines 34 to 36.
The pixel transistors 7 adjacent to each other in the column direction are connected so as not to be connected to the same source bus line.

The operation of the LCD according to the present embodiment is the same as that of the LCD according to the first embodiment except that the source bus line signal supplied to the display unit 1 is divided into three and supplied.

In the above structure, since the picture element transistors 7 adjacent to each other in the column direction are connected to different source bus lines from each other, the picture element transistors 7 are turned ON / O.
Even if FF, it does not affect each other. As a result, the adjacent picture element units 4 ... Are not affected by the noise generated when the picture element transistors 7 adjacent to each other are turned on / off, so that a high-resolution image without a ghost phenomenon can be obtained.

Further, the source driver 2 may be constructed as shown in FIG. 1 of the first embodiment. In this case, a data signal without rounding or delay can be supplied to the display unit 1, and the data signal can be written in the display unit 1 without rounding or delay, so that an LCD with further improved display quality can be provided.

[Embodiment 3] The following description will explain still another embodiment of the present invention with reference to FIGS. 5 and 6.

The display device of this embodiment is provided with a source driver 41 as shown in FIG. 5, instead of the source driver 2 shown in FIG. 1 of the first embodiment.

As shown in FIG. 5, the source driver 41 includes four systems of shift registers 42 to 45, AND circuits 46 to 50 for obtaining a logical product based on the outputs from the shift registers 42 to 45, AND circuits 46 to 50
The sample hold circuit 11 is supplied with the sampling pulse from the.

The AND circuits 46 to 50 are connected to the inverters 46a to 50a for inverting the output from the shift register of the next digit, respectively, and the outputs of the shift registers 42 to 45 and the output of the next shift register 42 to 45, respectively. A logical product of the digit output and the inverted signal is obtained, and the obtained logical product is supplied to the sample hold circuit 11 as a sampling pulse.

In addition to the sampling pulse, the sample hold circuit 11 is supplied with a data signal such as a video signal from the data signal line 51.

The data signal line 51 is branched into two inside the display unit 1 or outside the source driver 41, and then the data signal line 54 is passed through the buffer circuits 52 and 53.
-Connected to 55. The data signal line 54 is connected to each source terminal of the sampling switches 19, 21 and 23, and the data signal line 54 is connected to each source terminal of the sampling switches 20 and 22. As a result, the sampling switches 19 to 23 are alternately connected to the data signal lines 54 and 55, so that they are electrically disconnected from each other.

The operation of the source driver 41 having the above configuration will be described below. As shown in FIG. 6, SP and CK and / CK having different phases are input to the above-described four systems of shift registers 42 to 45. At this time, the output signals SR1 to S of the shift registers 42 to 45, respectively.
R9 is a pulse whose phase shifts by 1/8.

The shift register output SRi and the inverted signal of the shift register output SRi + 1 of the next digit are input to AND circuits 46 to 50. And A
The logical products obtained by the ND circuits 46 to 50 are input to the sampling switches 19 to 23 of the sample hold circuit 11 as sampling pulses SMP1 to SMP1.

On the other hand, the sampling switches 19-2
The data signal supplied from the data signal line 51 is input to the data signal 3 via the data signal lines 54 and 55 connected alternately.

Then, the sampling pulses SMP1 to SMP
Each data signal sampled by MP3 is held by each hold capacitor 24 to 28 and output to the source bus line 5 ... As a source bus line signal.

In the above structure, the sampling pulses SMP1 to SMP3 are short pulses that do not overlap the output SRi of the shift registers 42 to 43 in the AND circuits 46 to 50 as shown in FIG. ing.
As a result, two or more sampling pulses are simultaneously O
It does not become N state.

In this way, the sampling switch 1 is always
Since only one of 9 to 23 is in the ON state, the load seen from the data signal lines 54 and 55 is one sampling capacitor. Therefore, the load of the data signal line can be reduced to ⅛ as compared with the source driver having the four-system shift register configuration without using the AND circuit, for example, the source driver shown in the related art, so that the rounding of the data signal is suppressed. It can be reduced. Further, since the load on the data signal line can be reduced to ⅛, the time constant of the output CR from the shift register can also be reduced to ⅛, so that the rounding of the data signal can be made smaller than in the conventional case.

By the way, each sampling pulse SMP1
3 to 3 are actually due to the delay and rounding of the data signal,
The falling edge of SMPi (i = integer) and the rising edge of SMPi + 1 do not coincide with each other, and there is a period of slight overlap. However, in the present embodiment, the data signal lines 54 and 55 whose adjacent sampling switches are different from each other.
Connected to each other, the data signal line 5
It is possible to eliminate the influence of noise of 4.55.

Therefore, the LCD of this embodiment can reduce the distortion of the data signal due to the load of the data signal line, and reduce the ghost phenomenon due to the noise of the data signal due to the adjacent transistors being turned on at the same time. You can

Therefore, it is possible to realize a high resolution display in which the deterioration of the display quality due to the ghost phenomenon caused by the distortion of the data signal and the noise of the data signal is suppressed.

In this embodiment, the case where the shift register has four lines has been described, but the present invention is not limited to this and at least two lines may be used.

In this embodiment, the AND circuit is used to obtain the logical product from the output of the shift register. However, the present invention is not limited to this, and a NOR circuit or the like may be used. When ANDing SRi and SRi + 7, an inverter connected to the input stage of the AND circuit is not particularly required.

Further, in this embodiment, the source driver 4
The data signal line 51 is branched into two so that the respective sampling switches 19 to 23 in 1 are electrically sparse as much as possible, and then the data signal is transmitted from the data signal lines 54 and 55 via the buffer circuits 52 and 53. It is supplied to each sampling switch 19-23.

However, the above-mentioned buffer circuit 52
The data signal line 51 is not limited to via the signal line 53, but the data signal line 51 is branched into two without providing the buffer circuits 52 and 53, and the data signal is directly fed to each sampling switch 19.
23 to 23 may be supplied. In this case, the buffer circuit 52
・ Each sampling switch 1 more than via 53
Since 9 to 23 are less likely to become electrically sparse, the effect is halved.

Further, in this embodiment, the source driver 41
The sampling method in is a panel sample hold method in which image data as a data signal is held on the display unit 1 side, but it can be similarly applied to a driver sample hold method source driver in which image data is held on the source driver side. , A similar effect can be obtained. In this case, by using the driver sample hold type source driver, it is possible to take a sufficient time for writing the image data in the pixel portion connected to the source driver.

[Fourth Embodiment] The following description will explain still another embodiment of the present invention with reference to FIG.
In this embodiment, the source driver 41 of the above-mentioned third embodiment is used.
A case where the configuration applied to the above is applied to signal input in the display unit 1 of the LCD will be described.

In the LCD according to this embodiment, as shown in FIG. 7, the source bus lines 5 ... Connected to the source driver 41 of the above-mentioned Embodiment 3 are branched into two in front of the display unit 1, The source bus lines 58 and 59 are connected via the two buffer circuits 56 and 57, respectively. In FIG. 7, the horizontal direction is the row direction and the vertical direction is the column direction.

The source bus lines 58 and 59 have the source terminals of the pixel transistors 7 arranged in the column direction,
The pixel transistors 7 adjacent to each other in the column direction are connected so as not to be connected to the same source bus line.

Further, the gate driver 3 is connected to the gate bus lines 6 ... through AND circuits 60 ... And these AND circuits 60 ...
Inverter 60a for inverting the signal output to the circuit 60
... are connected. In the AND circuit 60, the logical product of the output of the gate driver 3 and the inverted signal of the output from the gate driver 3 to the AND circuit 60 in the next row is obtained, and the obtained logical product is used as the gate signal. It outputs to the gate bus line 6.

In the operation of the LCD in this embodiment, the source bus line signal supplied to the display unit 1 is branched into two and supplied, and the gate signal supplied from the gate driver 3 is supplied to the AND circuit. Other than is output via
The operation is similar to that of the source driver 41 of the third embodiment.

In the above structure, the pixel transistor 7
The gate signal that controls the ON / OFF of the AND circuit 60
Is output to the gate bus line 6 via, the gate signals do not overlap in time. As a result, the adjacent picture element units 4 ... Are not affected by noise due to the ON / OFF of the picture element transistors 7 adjacent to each other, so that a high-resolution image without a ghost phenomenon can be obtained.

Further, the source driver 41 may be constructed as shown in FIG. 1 of the first embodiment. in this case,
A data signal without rounding or delay can be supplied to the display unit 1,
In addition, since the data signal can be written in the display unit 1 without blunting or delay, the LCD with further improved display quality can be obtained.
Can be provided.

[Fifth Embodiment] The following description will explain still another embodiment of the present invention with reference to FIG.

The LCD according to this embodiment has a source driver 61 as shown in FIG. 8 in place of the source driver 2 shown in FIG. 1 of the first embodiment.

As shown in FIG. 8, the source driver 61 comprises a source shift register 10, a sample hold circuit 11, and a data signal line 12.

A buffer circuit 62 is connected to the data signal line 12.
To 66 are connected, and each of these buffer circuits 62 to
The output side of 66 is connected to the source terminals of the sampling switches 19 to 23 of the sample hold circuit 11, respectively. That is, the data signal output from the data signal line 12 is supplied to the sampling switches 19 to 23 via the buffer circuits 62 to 66 and held in the sampling capacitors 24 to 27, respectively.

As a result, the sampling switches 19-
23 is connected to the data signal line 12 via the buffer circuits 62 to 66, the buffer circuits 62 to 6
By 6, the electrical connection is sparse.

The operation of the source driver 61 having the above configuration will be described below. The SP input to the source shift register 10 is the source shift register 1
The signals are sequentially shifted and output according to CK and / CK input to 0. Then, the output pulse of each digit is sequentially input as the sampling pulse to the gate terminals of the respective sampling switches 19 to 23 in the sample hold circuit 11.

On the other hand, the data signal from the data signal line 12 is input to the source terminals of the sampling switches 19 to 23 via the buffer circuits 62 to 66.

Therefore, the source shift register 1
The sampling pulses supplied from 0 turn on the sampling switches 19 to 23, and hold the data signals output from the data signal line 12 in the sampling capacitors 24-27.

By the way, in the buffer circuits 13 to 15 and the buffer circuits 52 and 53 arranged in the source driver 2 and the source driver 41 described in the first and third embodiments, the load is the wiring load of the data signal line and the sampling capacitor. It is necessary to make the buffer circuit a circuit having a size that can cope with the above load.

However, the buffer circuit 6 of this embodiment
2 to 66, each has a sampling capacitor 24
To 27 are connected one by one, the buffer circuit 6
The load for each of 2 to 66 is only one sampling capacitor. Therefore, the buffer circuits 13 to 15 and the buffer circuits 52 and 53 described in the first and third embodiments are provided.
Can be a smaller circuit.

In addition, in the first and third embodiments, when a defect occurs in one buffer circuit, the number of source bus lines is reduced to three.
The data signal is not supplied to every one book or every two books. As a result, 1/3 or 1/2 of the entire display on the display unit 1 becomes a display defect.

However, in the present embodiment, when a defect occurs in the buffer circuits 62 to 66, the data signal is not supplied only to the source bus line connected to the defective buffer circuit, so that the display defect is also caused. Only the source bus line connected to the defective buffer circuit can be suppressed.

Further, since the adjacent sampling switches 19 to 23 are electrically disconnected from each other by the buffer circuits 62 to 66, the sampling transistors 19 to 23 are turned off by the irradiation of light from the outside, for example.
Even when the FF resistance decreases, the sampling switches 19 connected to the same data signal line 12 are adjacent to each other.
It is possible to prevent the data signals held in the sampling transistors 24 to 27 from cross-talking through the OFF resistors of 23 to 23.

In general, a plurality of signal wirings other than the data signal wirings are arranged in the source driver, so that each signal wiring passes through its wiring capacitance or the capacitance at the intersection of intersecting wirings and other factors. The precision of the sampling data will be reduced due to the presence of noise through the parasitic capacitance.

However, the source driver 61 of this embodiment is
Then, since there is only one data signal line 12, the influence of noise on the data signal line 12 can be reduced.

As described above, the adjacent sampling transistors can be always supplied with an accurate data signal as the source bus line signal to the source bus line 5 without being influenced by the ON / OFF of each other.

Therefore, in the LCD of the present embodiment, the ghost phenomenon caused by the rounding of the data signal waveform due to the load on the data signal line 12 or the noise of the data signal due to the adjacent transistors being simultaneously turned ON, and In addition, it is possible to realize a high-resolution display in which the deterioration of the display quality due to the crosstalk caused by the lack or deterioration of the OFF characteristics of the sampling transistor is suppressed.

In this embodiment, the sampling method in the source driver 61 is the panel sample and hold method in which the image data as the data signal is held on the display unit 1 side, but the image data is held on the source driver side. The same can be applied to the source driver of the driver sample hold method, and the same effect can be obtained. In this case, by using the driver sample hold type source driver, it is possible to take a sufficient time for writing the image data in the pixel portion connected to the source driver.

[Sixth Embodiment] The following description will explain still another embodiment of the present invention with reference to FIG.
In this embodiment, the source driver 61 of the above-mentioned fifth embodiment is used.
A case where the configuration applied to the above is applied to signal input in the display unit 1 of the LCD will be described.

In the LCD according to this embodiment, as shown in FIG. 9, the buffer circuits 67 are connected to the source bus lines 5 connected to the source driver 61, and the picture is provided on the output side of the buffer circuits 67. The source terminal of the elementary transistor 7 is connected. In FIG. 9, the left-right direction is the row direction,
The vertical direction is the column direction.

That is, although a plurality of picture element transistors 7 are connected to the same source bus line 5 in the column direction, each picture element transistor 7 is formed by the buffer circuit 67.
Are connected to the source bus line 5 so as to be electrically sparse to each other.

In the operation of the LCD of this embodiment, the source bus line signal is supplied to the picture element transistor 7 of the display section 1 through the buffer circuit 67 ... The operation is similar.

In the above structure, the source bus line 5
The source bus line signals from the above are supplied to the plurality of pixel transistors 7 connected to the same source bus line 5 via the buffer circuits 67, respectively, so that the source bus line signals influence each other. Absent. Therefore, the adjacent picture element units 4 ... Are not affected by the noise generated when the picture element transistors 7 are in the ON state, and a high resolution image in which crosstalk due to the OFF resistance of the picture element transistors is suppressed is obtained. Obtainable.

Further, the source driver 61 may be constructed as shown in FIG. 1 of the first embodiment. in this case,
A data signal without rounding or delay can be supplied to the display unit 1,
In addition, since the data signal can be written in the display unit 1 without blunting or delay, the LC with further improved display quality can be obtained.
D can be provided.

[Embodiment 7] The following description will discuss still another embodiment of the present invention with reference to FIG. For convenience of explanation, members having the same functions as those in the above-mentioned respective embodiments will be designated by the same reference numerals, and the description thereof will be omitted.

As shown in FIG. 10, the LCD according to the present embodiment has a display section 1 having a plurality of picture element sections 4, a source driver 71 and a gate driver as a drive circuit for driving the picture element sections 4. 3 and 3. In FIG. 10, the horizontal direction is the row direction and the vertical direction is the column direction.

The source driver 71 supplies the source shift register 10, AND circuits 72, 72 for obtaining the logical product of the outputs from the source shift register 10, and the data signal (video signal) of different polarity. Data signal lines 73 and 74 and a sample hold circuit 11 that samples a data signal according to the output from the source shift register 10.

Inverters 72a and 72a are connected to the AND circuits 72 and 72 so that the output of the next digit of the source shift register 10 is inverted and input. That is, the AND circuit 72 obtains the logical product of the output of the source shift register 10 and the inverted signal obtained by inverting the output input to the AND circuit 72 of the next digit by the inverter 72a,
This logical product is output to the sample hold circuit 11 as a sampling pulse.

Further, to the data signal lines 73 and 74, data signals having polarities different from each other and the polarities of which are inverted for each field are supplied from a data signal generating circuit (not shown) via buffer circuits 75 and 76. .

The data signal line 73 is connected to the source terminals of the sampling switches 19 and 21 of the sample and hold circuit 11, and the data signal line 74 is connected to the source terminals of the sampling switches 20 and 22 of the sample and hold circuit 11. There is.

Therefore, the sampling switch 1
Sampling pulses are supplied from the same AND circuit 72 to the source terminals of 9 and 20, and the same AND circuit is supplied to the source terminals of the sampling switches 21 and 22.
A sampling pulse is supplied from the circuit 72. The AND circuit 72 supplies the sample hold circuit 11 with a pulse width that does not overlap the output from the source shift register 10 in terms of time.

The operation of the source driver 71 having the above configuration will be described below. The SP input to the source shift register 10 is the source shift register 1
It is sequentially shifted and output according to the drive clocks CK and / CK input to 0. Then, the output pulse of each digit is input to the AND circuit 72. Then AN
The output SR of the source shift register 10 in the D circuit 72
A logical product is obtained from i and the inverted signal of the output SRi + 1 of the next digit, and the value of this logical product is output to the sample hold circuit 11 as a sampling pulse.

The output from the AND circuit 72 is sequentially input to the gate terminals of the sampling switches 19 to 23 in the sample hold circuit 11 as sampling pulses.

On the other hand, the data signal from the data signal line 12 is input to the source terminals of the sampling switches 19 to 23 via the buffer circuits 62 to 66.

Therefore, the source shift register 1
When the sampling pulse output from 0 is input to the gate terminals of the sampling switches 19 to 23, the data signal output from the data signal line 12 is held in the sampling capacitors 24-27.

The held data signals are transferred from the source bus lines 5 arranged on both the left and right sides of the picture element section 4 to the buffer circuit 7.
Every other one of the gate bus lines 6 ... Is inputted via the 7 to the picture element transistors 7 ... Which are alternately connected.

According to the source driver 61 having the above structure,
The output from the source shift register 10 is the AND circuit 7
Since it is inputted to the sample hold circuit 11 via 2, ..., The width of the sampling pulse becomes small,
The relationships do not overlap with each other in terms of time. Therefore, the load seen from each of the data signal lines 73 and 74 is smaller than that in the conventional case, so that the rounding of the data signal can be made smaller than in the conventional case.

The gate driver 3 is composed of a gate shift register 3a and an AND circuit 81 for obtaining a logical product from the output of the gate shift register 3a.

The AND circuits 81 are connected to the inverters 81a so that the output of the next row of the gate shift register 3a is inverted and input. That is, the AND circuit 81 obtains the logical product of the output of the gate shift register 3a and the inverted signal obtained by inverting the output input to the AND circuit 81 of the next row by the inverter 81a, and calculates the logical product. The gate signal (scanning signal) is supplied to the gate bus lines 6 ... The AND circuit 81
Output the gate shift register 3a to the pixel transistors 7 with pulse widths that do not overlap in time.

Therefore, since the gate signals input from the gate driver 3 to the picture element transistors 7 of the display section 1 are logical products obtained from the output of the gate shift register 3a, the gate signals are temporally related to each other. It is a relationship that has no overlap. Therefore, it is possible to prevent the influence of noise due to the pixel transistors 7 ... Which are adjacent in the column direction being simultaneously turned on.

Since the pixel transistors 7 ... Which are adjacent in the column direction are connected to different source bus lines 5 ..., The gate bus line signal Gi and the gate bus line signal Gi + 1 in the next row are signals. Even if there is a period in which the pixel transistors 7 adjacent to each other in the column direction are simultaneously turned on due to a delay or rounding, the pixel capacitors 8 ... And the additional capacitors 9 ... This prevents the accuracy of the source bus line signal from decreasing.

In general, the signal applied to the source bus line 5 has its applied voltage polarity inverted every scanning period in order to prevent a decrease in reliability due to application of a DC voltage to the liquid crystal. In this case, if there is a period in which the pixel transistors 7 adjacent to each other in the column direction are simultaneously turned on, there arises a problem that the accuracy of the source bus line data sampled in the pixel capacitors 8 is further deteriorated. It will be.

However, in this embodiment, the picture element transistors 7 ... Which are adjacent in the column direction are supplied with the source bus line signals via the different source bus lines 5 provided on both sides of the picture element portions 4 ... Therefore, it is possible to eliminate the period in which the picture element transistors 7 adjacent in the column direction are simultaneously turned on, and as a result,
It is possible to prevent the accuracy of the source bus line data sampled in the pixel capacitors 8 ...

In general, when the polarity of the voltage applied to the source bus line 5 is inverted every scanning period, the source bus line 5 charged in a certain scanning period is charged to the opposite polarity in the next scanning period. Therefore, a large driving force is required to drive the source bus lines 5 ... As a result, there is a problem that the power consumption of the entire source driver increases due to the power required to drive the source bus lines 5.

However, in this embodiment, since the data signals having different polarities are alternately supplied to the source bus lines 5 in advance, the data signals having the same polarity are arranged on both sides of the picture element portion 4. Since it is sufficient to supply the signal to the source bus lines 5 ..., It is not necessary to supply a signal having a polarity opposite to the polarity supplied to the source bus lines 5 every scanning period. As a result, the power required to drive the source bus lines 5 ... Can be reduced, so the source driver 61
The overall power consumption can be reduced.

In the present embodiment, the two source bus lines 5 are arranged on both sides of each picture element portion 4 ... However, the present invention is not limited to this, and one side of the picture element portion 4, for example. Two source bus lines 5 and 5 may be arranged in each. However, in this case, every other one of the gate bus lines 6 crosses the source bus line 5 and the source bus line 5 and the pixel transistor 7 are connected to each other, so that noise from the parasitic capacitance or the like at the crossing portion is generated. Therefore, the effect cannot be obtained as much as when the source bus lines 5, 5 are arranged on both sides of the picture element portion 4.

[Embodiment 8] The following description will discuss still another embodiment of the present invention with reference to FIG. The LCD of the present embodiment has the same configuration of the display unit and the gate driver as those of the above-described embodiments, and the source driver will be described.

As shown in FIG. 11, the LCD source driver according to the present embodiment has data signal lines 82 for supplying data signals such as a plurality of video signals, and the respective data signal lines 82. T of sample hold circuit 85
Sampling switch 8 consisting of transistors such as FT
6 ... Source terminals are connected.

A sampling timing control circuit 84 for controlling the sampling timing of the data signal is connected to the gate terminals of the sampling switches 86.

The data signal line 82 is connected to a data signal generation circuit (not shown) via the buffer circuit 83. The data signal lines 82 are connected to the sampling switch 86 one by one. As a result, the load on the data signal lines 82 becomes only one sampling switch 86, and therefore the data signal before being divided is more than when the plurality of sampling switches 86 are connected to one data signal line 82. The impedance of the line can be lowered.

That is, by dividing the data signal output from the data signal generating circuit into a plurality of pieces in the horizontal direction of the display, the impedance of the data signal line before the division,
In particular, the capacity component can be reduced to about 1 / N (N: number of divisions). As a result, the time constant of the data signal line can be significantly improved, and the occurrence of crosstalk can be suppressed.

Since the input of the data signal to the display unit 1 can be input to the display unit 1 from the vicinity of the sample hold circuit 85, the time constant can be greatly improved also by this.

This embodiment can also be applied to each of the above-mentioned embodiments, whereby a high-resolution display device with less crosstalk can be obtained.

As described above, each of the above-described first to eighth embodiments shows a basic configuration, and the circuit configuration is changed, for example, the sampling pulse generating circuit is configured by a so-called decoder type circuit instead of the shift register described above. You may change it when it is done.

Further, for example, when the capacity of the sampling capacitor connected to the sampling transistor is small, the same data signal can be supplied to each series of shift registers via the buffer circuit.

Furthermore, in Examples 1 to 8 described above,
The source driver and the gate driver as the drive circuit including the sampling circuit and the display unit including the picture element unit as the image display unit may be monolithically formed on the same substrate. In this case, it is possible to improve the driving force of the pixel transistor associated with the increase in screen size and reduce the mounting cost of the driving IC.

[0161]

As described above, the display device of the present invention samples a plurality of data signal lines to which data signals are respectively supplied and a data signal supplied from the plurality of data signal lines. A plurality of sampling circuits; a plurality of data bus lines respectively connected to the plurality of sampling circuits; a plurality of picture element parts connected to the plurality of data bus lines and arranged in a matrix; A drive circuit for driving the data bus line, the circuit including a circuit, and at least two of the plurality of data signal lines are supplied with the same data signal, and are supplied to different sampling circuits via different buffer circuits. It is a connected configuration.

As a result, the adjacent sampling circuits can reduce the ghost phenomenon by always sampling the accurate data signal without being influenced by the ON / OFF of each other. Further, it is possible to reduce crosstalk due to the OFF resistance of the transistors in the picture element portion and the sampling circuit portion.

Therefore, there is an effect that it is possible to realize a high resolution display in which the deterioration of the display quality due to the ghost and the crosstalk is suppressed.

As described above, in the display device according to the second aspect of the present invention, in the display device according to the first aspect, among the plurality of sampling circuits, the sampling circuits whose sampling timings are synchronized are connected to different data signal lines. In addition to being connected, the ON periods of the respective sampling circuits do not overlap in time.

Thus, in addition to the effect of the first aspect, it is possible to reduce the noise generated when the other sampling circuits are turned on at the moment when the sampling circuit is turned off.

As described above, the display device of the invention of claim 3 is the display device of claim 1 or 2, wherein the buffer circuit is formed on the same substrate as the sampling circuit.

As a result, it is possible to suppress the deterioration of the data signal related to the contact resistance due to the flexible substrate connecting the buffer circuit and the sampling circuit. In addition, it is possible to suppress an increase in the number of connection terminals for connecting the buffer circuit and the sampling circuit, and it is possible to improve reliability associated with mounting.

As described above, a display device according to a fourth aspect of the present invention includes a plurality of data signal lines to which data signals are respectively supplied and a plurality of data signals supplied from the plurality of data signal lines. A sampling circuit; a plurality of data bus lines respectively connected to the plurality of sampling circuits; a plurality of picture element portions connected to the plurality of data bus lines and arranged in a matrix; and the sampling circuit. And a drive circuit for driving the data bus line, wherein the data signal line is divided into a plurality of pieces in the horizontal direction of display, and each divided signal line is sampled through a different buffer circuit. It is connected to the circuit.

With this, the resistance and capacitance of the data signal line can be reduced, so that the deterioration of the data signal on the data signal line can be further reduced and the noise at the time of sampling can be reduced. Produce an effect.

As described above, a display device according to a fifth aspect of the present invention includes a plurality of data signal lines to which data signals are respectively supplied, and a plurality of data signals supplied from the plurality of data signal lines. A sampling circuit; a plurality of data bus lines respectively connected to the plurality of sampling circuits; a plurality of picture element portions connected to the plurality of data bus lines and arranged in a matrix; and the sampling circuit. A plurality of picture element portions adjacent to each other in the column direction of the plurality of picture element portions are connected to different data bus lines, respectively. The same sampling circuit is connected to the bus line via a buffer circuit.

As a result, it is possible to suppress the interference between the picture element portions adjacent to each other in the column direction, so that it is possible to reduce crosstalk between the picture element portions, and as a result, it is possible to improve the display quality. Play.

As described above, a display device according to a sixth aspect of the present invention is the display device according to the first aspect, further comprising a drive circuit and an image display portion including a plurality of picture element portions. Are monolithically formed on the same substrate.

As a result, it is possible to improve the driving force of the pixel transistor associated with the enlargement of the screen and to reduce the mounting cost of the driving IC.

[Brief description of drawings]

FIG. 1 is a schematic block diagram of a source driver of an LCD according to an embodiment of the present invention.

FIG. 2 is a schematic configuration block diagram of an LCD including the source driver shown in FIG.

FIG. 3 is an operation timing chart of the source driver shown in FIG.

FIG. 4 is a schematic block diagram of an LCD according to another embodiment of the present invention.

FIG. 5 is a schematic configuration block diagram of a source driver of an LCD according to still another embodiment of the present invention.

6 is an operation timing chart of the source driver shown in FIG.

FIG. 7 is a schematic block diagram of an LCD according to still another embodiment of the present invention.

FIG. 8 is a schematic block diagram of a source driver of an LCD according to still another embodiment of the present invention.

FIG. 9 is a schematic block diagram of an LCD according to still another embodiment of the present invention.

FIG. 10 is a schematic block diagram of an LCD according to still another embodiment of the present invention.

FIG. 11 is a schematic block diagram of a source driver of an LCD according to still another embodiment of the present invention.

FIG. 12 is a schematic block diagram of a conventional LCD.

FIG. 13 is a schematic block diagram of a source driver included in the LCD shown in FIG.

FIG. 14 is a schematic block diagram of another conventional source driver.

15 is an operation timing chart of the source driver shown in FIG.

[Explanation of symbols]

1 Display Part (Image Display Part) 2 Source Driver (Drive Circuit) 3 Gate Driver (Drive Circuit) 4 Picture Element Part 5 Source Bus Line (Drive Circuit) 6 Gate Bus Line (Drive Circuit) 10 Source Shift Register 11 Sample Hold Circuit 12 data signal lines 13 to 15 buffer circuit 16 to 18 data signal lines 19 to 23 sampling switch (sampling circuit) 24 to 28 sampling capacitor (sampling circuit) 41 source driver (driving circuit) 51 data signal lines 52 and 53 buffer circuit 54 -55 data signal line 61 source driver (driving circuit) 62-66 buffer circuit 54-55 data signal line 73-74 data signal line 75-80 buffer circuit

Claims (6)

[Claims] 1. A plurality of data signal lines to which data signals are respectively supplied, a plurality of sampling circuits for sampling the data signals supplied from the plurality of data signal lines, and a plurality of sampling circuits respectively connected to the plurality of sampling circuits. A plurality of data bus lines, a plurality of picture element portions connected to the plurality of data bus lines and arranged in a matrix, and a drive circuit including the sampling circuit and driving the data bus lines. At least two of the plurality of data signal lines are supplied with the same data signal, and are connected to different sampling circuits via different buffer circuits, respectively. 2. A sampling circuit of which sampling timing is synchronized among the plurality of sampling circuits,
The display device according to claim 1, wherein the display circuits are connected to different data signal lines, and the ON periods of the respective sampling circuits have no temporal overlap. 3. The display device according to claim 1, wherein the buffer circuit is formed on the same substrate as the sampling circuit. 4. A plurality of data signal lines to which data signals are respectively supplied, a plurality of sampling circuits for sampling the data signals supplied from the plurality of data signal lines, and a plurality of sampling circuits respectively connected to the plurality of sampling circuits. A plurality of data bus lines, a plurality of picture element portions connected to the plurality of data bus lines and arranged in a matrix, and a drive circuit including the sampling circuit and driving the data bus lines. The display device is characterized in that the data signal line is divided into a plurality of lines in the horizontal direction of display, and each divided signal line is connected to a sampling circuit via a different buffer circuit. . 5. A plurality of data signal lines to which data signals are respectively supplied, a plurality of sampling circuits for sampling the data signals supplied from the plurality of data signal lines, and a plurality of sampling circuits respectively connected to the plurality of sampling circuits. A plurality of data bus lines, a plurality of picture element portions connected to the plurality of data bus lines and arranged in a matrix, and a drive circuit including the sampling circuit and driving the data bus lines. Of the plurality of picture element units, different picture element units adjacent to each other in the column direction are connected to different data bus lines, and the same sampling is performed on these data bus lines via a buffer circuit. A display device having a circuit connected thereto. 6. The driving circuit and the image display section including the plurality of picture element sections are monolithically formed on the same substrate.
Display device described.