JP4538712B2 - Display device - Google Patents

Description

  The present invention relates to a display device, and more particularly to a display device including a display panel corresponding to an active matrix driving method.

  In recent years, as a display device (display) for displaying images, character information, etc. in imaging devices such as digital video cameras and digital still cameras, which are remarkably popular, and portable devices such as mobile phones and personal digital assistants (PDAs), Liquid crystal displays (LCDs) that are thin, lightweight, low power consumption, and have excellent display image quality as monitors and displays for information devices such as computers and video equipment such as televisions. Is frequently used.

Hereinafter, a conventional liquid crystal display device will be briefly described.
FIG. 17 is a block diagram showing a schematic configuration of a liquid crystal display device provided with a thin film transistor (TFT) type display pixel in the prior art, and FIG. 18 is an equivalent diagram showing an example of a main configuration of a liquid crystal display panel in the prior art. It is a circuit diagram.
As shown in FIGS. 17 and 18, the liquid crystal display device 100P according to the prior art is schematically a liquid crystal display panel (display panel) 110P in which display pixels Px are two-dimensionally arranged (for example, arranged in n rows × m columns). And a gate driver (scanning driver) 120P that sequentially scans the display pixels Px group in each row of the liquid crystal display panel 110P to set the selected state, and a display pixel Px group in the row that is set to the selected state. Generates and outputs a source driver (data driver) 130P that collectively outputs display signal voltages based thereon, and control signals (horizontal control signal, vertical control signal, etc.) for controlling operation timing in the gate driver 120P and the source driver 130P LCD controller 150P, and various timing signals (horizontal synchronization signal, vertical synchronization signal, composite Display signal generation circuit 160P that generates display data consisting of luminance signals and outputs it to the data driver 130P, and a polarity inversion signal generated by the LCD controller 150P. Based on FRP, a common signal drive amplifier (drive amplifier) that applies a common signal voltage Vcom having a predetermined voltage polarity to a common electrode (counter electrode) provided in common to each display pixel Px of the liquid crystal display panel 110P ) 170P.

  Here, the liquid crystal display panel 110P includes, for example, a plurality of scanning lines SL and a plurality of data lines DL arranged between the opposing transparent substrates so as to be orthogonal to each other in the matrix direction, as shown in FIG. And a plurality of display pixels (liquid crystal display pixels) Px arranged in the vicinity of the intersections of the scanning lines SL and the data lines DL. Each display pixel Px includes a pixel transistor TFT composed of a thin film transistor having a source-drain (current path) connected between the pixel electrode and the data line DL, and a gate (control terminal) connected to the scan line SL, and a pixel electrode. And a pixel capacitance (liquid crystal capacitance) Clc composed of liquid crystal molecules filled and held between the common electrode provided in common to all the display pixels Px and the pixel electrode, and the pixel capacitance Clc. And an auxiliary capacitor (storage capacitor) Cs for holding the signal voltage applied to the pixel capacitor Clc.

  Note that the scanning line SL and the data line DL provided on the liquid crystal display panel 110P are connected to the gate driver 120P and the source driver 130P provided separately from the liquid crystal display panel 110P via the connection terminals TMg and TMs, respectively. Configured to be connected. In addition, an electrode (auxiliary electrode) on the other end side of the auxiliary capacitor Cs is configured to be applied with a predetermined voltage Vcs (for example, a common signal voltage Vcom) via a common connection line CL.

  In the liquid crystal display device 100P having such a configuration, display data corresponding to display pixels for one row of the liquid crystal display panel 110P supplied from the display signal generation circuit 160P is supplied from the LCD controller 150P. Are sequentially captured and held by the source driver 130P. On the other hand, based on the vertical control signal supplied from the LCD controller 150P, a scanning signal is sequentially applied to each scanning line SL provided on the liquid crystal display panel 110P by the gate driver 120P, and the pixel transistors of the display pixels Px group in each row. The TFT is turned on and is set to a selection state in which the display signal voltage can be taken. In synchronization with the selection timing of the display pixel Px group in each row, the source driver 130P supplies the display signal voltage based on the captured and held display data to the display pixels Px all at once via the data lines DL. To do.

  As a result, the liquid crystal molecules filled in the pixel capacitor Clc change the alignment state according to the display signal voltage via the pixel transistor TFT of each display pixel Px set to the selected state, and display a predetermined gradation. As the operation is performed, the auxiliary capacitor Cs connected in parallel to the pixel capacitor Clc is charged with the voltage applied to the pixel capacitor Clc. By repeating such a series of operations for each row for one screen, desired image information based on the video signal is displayed on the liquid crystal display panel 110P.

  As shown in FIGS. 17 and 18, the mounting structure of the liquid crystal display device is separated from an insulating substrate such as a glass substrate (on which a pixel array is formed) constituting the liquid crystal display panel 110P. In addition to a configuration in which a gate driver 120P and a source driver 130P, which are circuits, are provided and the liquid crystal display panel 110P and peripheral circuits are electrically connected via connection terminals TMg and TMs, on the insulating substrate, for example, a gate A configuration is also known in which the driver 120P and the source driver 130P are formed integrally with a pixel array (display pixel Px) by applying a polysilicon transistor. The schematic configuration, mounting structure, and the like of such a liquid crystal display device are described in, for example, Patent Document 1 and the like.

JP 2000-267590 (3rd page, FIG. 1)

However, the liquid crystal display device as described above has the following problems.
That is, as shown in FIGS. 17 and 18, in the configuration in which the gate driver 120P and the source driver 130P are separately provided as peripheral circuits with respect to the liquid crystal display panel 110P, the liquid crystal display panel is improved in order to improve the display image quality. When the resolution of 110P is increased, the number of data lines is increased, thereby increasing the number of connection terminals for connecting the liquid crystal display panel 110P and the gate driver 120P or the source driver 130P, and the pitch between the connection terminals. Therefore, the number of steps in the connection process for connecting the liquid crystal display panel 110P and the peripheral circuit (the gate driver 120P and the source driver 130P) increases, and high connection accuracy is required. And increase the mounting area for externally attaching peripheral circuits. I had a problem.

  As a technique for solving the problem of man-hours and connection accuracy related to the connection between the liquid crystal display panel and the peripheral circuit, and further the problem of the mounting area, as shown in the above-mentioned Patent Document 1 and the like, There is known a configuration in which a liquid crystal display panel, a gate driver and a source driver are integrally formed on a single insulating substrate by applying polysilicon transistors. Here, as is well known, unlike an amorphous silicon transistor, a polysilicon transistor has a complicated manufacturing process unlike a transistor element that has already established manufacturing technology and has obtained good element characteristics (operation characteristics). In addition, since the manufacturing cost is expensive and the operation characteristics are insufficient, the product cost of the liquid crystal display device is increased, and it is difficult to obtain stable display characteristics.

  Therefore, in view of the above-described problems, the present invention reduces the mounting area (apparatus scale) at a relatively low manufacturing cost without requiring an increase in man-hours and high connection accuracy in the connection process between the display panel and the peripheral circuit. It is an object of the present invention to provide a display device that can be reduced in size and improved in operating characteristics (display characteristics).

According to the first aspect of the present invention, a plurality of scanning lines and a plurality of signal lines are arranged so as to be orthogonal to each other, and a plurality of display pixels are two-dimensionally arranged in the vicinity of the intersection of the signal lines and the scanning lines. In the display device for displaying the desired image information by supplying each of the plurality of display pixels with gradation by supplying a display signal voltage based on display data to the plurality of display pixels. At least a scanning signal is sequentially applied to the scanning lines of each row at a predetermined timing to set the display pixels of the row to a selected state, and the display data supplied from the outside is fetched, in parallel. And the display data held in parallel in the data holding unit into pixel data arranged in a time-sharing manner for each predetermined number of display data A signal driving unit having a data conversion unit for conversion, and interposed between the display panel and the signal driving unit, directly connected to the plurality of signal lines, and provided in common for the predetermined number of the signal lines. A plurality of switches for applying the display signal voltage based on the pixel data supplied from the signal driving means to the predetermined number of the signal lines in a time-sharing manner through the plurality of connection terminals provided has, on the plurality of display pixels in the row set to the selected state, a data distribution means for applying individually the display signal voltage the distribution via the signal lines of the predetermined number, the is disposed between each of the plurality of connection terminal and the data distribution unit, a plurality of signal lines for transmitting the display signal voltage before the data distribution means, based on a predetermined timing signal, said Switch driving control means for generating a switch switching signal for controlling a conduction state of the plurality of switches in the data distribution means, an output contact point of the switch switching signal in the switch drive control means, and the data distribution means in the data distribution means It is connected to a pair of signal input contacts provided at both ends of a switching control line for supplying the switch switching signal to a plurality of switches, and is connected to two signal paths between the output contact and the pair of signal input contacts. And the connection wiring arranged in one of the two signal paths in the connection wiring via the plurality of signal wirings and an insulating film. And the plurality of signal wires are arranged in a region intersecting with the connection wiring provided in the one signal path. The wiring pattern is disposed so as to be orthogonal to the connection wiring and includes a wiring pattern extending in an oblique direction so as to connect to the data distribution means in a region not intersecting with the connection wiring. To do.

According to a second aspect of the present invention, in the display device according to the first aspect, the plurality of switches are provided corresponding to each of the plurality of signal lines, and based on the switch switching signal, in the data conversion unit. A conductive state is selectively set in synchronization with a time division timing used for the conversion of the display data.
According to a third aspect of the present invention, in the display device according to the first or second aspect, the switch drive control means is configured integrally with the scan drive means.

According to a fourth aspect of the present invention, in the display device according to any one of the first to third aspects, at least the display panel, the scanning drive unit, and the data distribution unit are integrated on a single insulating substrate. It is comprised by these.
According to a fifth aspect of the present invention, in the display device according to any one of the first to fourth aspects, the scanning driving unit is configured integrally with the signal driving unit.

According to a sixth aspect of the present invention, in the display device according to any one of the first to fourth aspects, the scan driving unit is uniquely disposed on one direction side of the display panel so as to be adjacent to the signal driving unit. It is characterized by .

According to a seventh aspect of the present invention, in the display device according to any one of the first to sixth aspects, the plurality of display pixels each have a gate electrode connected to the scanning line and a drain electrode connected to the signal line. A pixel transistor in which a source electrode is connected to the pixel electrode, a pixel capacitor in which liquid crystal molecules are filled between the pixel electrode and a common electrode provided in common opposite to the pixel electrode, and the pixel capacitor An auxiliary capacitor connected in parallel, and by applying the display signal voltage based on the pixel data, the alignment state of the liquid crystal molecules filled in the display pixel is controlled to display a gray scale It is characterized by being.

  That is, a display device according to the present invention includes a display panel in which display pixels are arranged in a matrix in the vicinity of intersections of a plurality of scanning lines and a plurality of signal lines (data lines) orthogonal to each other. , A scanning driving means (gate driver) for sequentially applying scanning signals to display pixels in each row at a predetermined timing to set the display pixels in the row to a selected state, and display data for each predetermined number of display data Signal driving means (source driver) having means for converting into pixel data arranged in a time division manner, and a plurality of switches interposed between the display panel and the signal driving means and connected to each of the plurality of signal lines A data distribution means (traffic) that distributes and applies a display signal voltage based on pixel data to the display pixels set in a selected state in a time-sharing manner via the switch. A switch driving control unit (switch driving unit) for generating a switch switching signal for controlling a conduction state of a plurality of switches in the data distribution unit, and a switch switching signal of the switch driving control unit A connection wiring (wiring group) connected between an output contact and a pair of signal input contacts provided at both ends of a switching control line for supplying a switch switching signal to a plurality of switches in the data distribution means is two signals. It has a configuration in which the path is branched.

  Here, at least the display panel, the scanning drive means, and the data distribution means are integrally formed on the same insulating substrate. Further, the switch drive control means may be configured integrally with the scanning drive means, and further, the scan drive means is configured integrally with the signal drive means or adjacent to the signal drive means. It may be arranged in the area to be.

  As described above, according to the display device of the present invention, the display signal voltage supplied to the display pixels connected to each signal line constituting the display panel is set to a set of a plurality of signal lines inside the signal driving means. Are converted into serial data (pixel data) at a predetermined time division timing and output to the data distribution means through the connection terminals for the number of sets, and the serial data of each set is time-divided by the data distribution means. Since it can be supplied while being sequentially distributed to each set of signal lines according to the timing, the data distributing means provided on the insulating substrate and the signal driving means attached to the insulating substrate are connected to the signal lines. Connections can be made with fewer connection terminals.

  Therefore, the number of connection terminals between the display panel (pixel area) and the signal driving means can be greatly reduced, and the pitch between the connection terminals can be designed to be relatively wide, thereby reducing the number of steps in the connection process. In addition, it is possible to connect well even with relatively low connection accuracy, and it is possible to reduce the manufacturing cost and the mounting area of the peripheral circuit (driver IC).

  In addition, the switch switching signal generated by the switch drive control means is parallel to both ends of the switching control line provided in the data distribution means via connection wiring that is branched into two signal paths. When the switch switching signal is applied to any switch connected to the switching control line, the transmission distance of the signal is ½ of the wiring length of the switching control line. Therefore, the resistance component and the capacitance component added to the switching control line can be reduced, the time constant defined by the product of both can be reduced, and the transmission delay of the switch switching signal can be greatly suppressed. Therefore, it is possible to suppress deterioration in image quality such as display unevenness due to defective writing of display data to display pixels.

Here, as the arrangement structure of the connection wiring, one of the two signal paths is a connection wiring between the switch drive control means and the data distribution means (specifically, an output contact and a signal between input contacts) are disposed so as to be substantially shortest path connecting wire serving as one of the signal paths are disposed so as to pass through the region between the signal driving means and a data distributing means.

In this arrangement structure, by having a crossing structure of connecting wiring and signal wiring intersect, since it is considered to be a direct effect on the signal level of the display signal voltage, for suppressing configured such effects, the signal The wiring pattern is formed so that the intersection structure of the signal wiring (transfer connection line group) for transmitting the display signal voltage output from the driving means and the connection wiring serving as the one signal path is orthogonal to each other . .

  According to this, since the parasitic capacitance added to each wiring can be made uniform at the intersection, the influence (transmission delay) on the display signal voltage transmitted by the signal wiring can be suppressed, It is possible to improve the electrical connection state, wiring pattern abnormality, and the like. In addition, since the connection wiring can be arranged in the area between the signal driving means and the data distribution means, the circuit formation area can be reduced as compared with the case where it is arranged on the edge side of the insulating substrate. Thus, the substrate size of the insulating substrate on which the display panel is mounted can be reduced.

  In addition, the display device according to the present invention has a configuration in which at least the display panel (a plurality of display pixels), the scanning drive unit, and the data distribution unit are integrally formed on the same insulating substrate. Therefore, the pixel transistors constituting the display pixels and the functional elements constituting the scanning drive means and the data distribution means can be formed by the same manufacturing process by applying, for example, amorphous silicon. As a result, a display device can be manufactured at low cost by applying an amorphous silicon manufacturing process that has already been established technically, and a functional element with stable operating characteristics can be realized. Characteristics can be improved.

Hereinafter, a display device according to the present invention will be described with reference to the drawings. In the following embodiments, the case where the display device according to the present invention is applied to a liquid crystal display device employing an active matrix driving method will be described.
(Display device)
First, the overall configuration of a liquid crystal display device to which the display device according to the present invention can be applied will be described.
FIG. 1 is a schematic block diagram showing an overall configuration of a liquid crystal display device to which the display device according to the present invention is applied, and FIG. 2 shows an example of a main configuration of the liquid crystal display device to which the display device according to the present invention is applied. It is a schematic block diagram. Here, about the structure equivalent to the prior art (FIG. 17 and FIG. 18) mentioned above, description is simplified by attaching | subjecting the same or same code | symbol.

  As shown in FIGS. 1 and 2, the liquid crystal display device 100 according to this configuration example is roughly in the vicinity of the intersection of a plurality of scanning lines SL and a plurality of data lines DL, similarly to the above-described conventional technique (see FIG. 17). A plurality of display pixels Px are arranged in a two-dimensional (n rows × m columns) liquid crystal display panel 110 (display panel: or a pixel array provided in a predetermined region on an insulating substrate SUB as shown in FIG. PXA), a gate driver (scanning signal means) 120 for sequentially applying a scanning signal to each scanning line SL at a predetermined timing, and a source driver (signal for applying a display signal voltage based on display data to each data line DL. Driving means) 130, and various controls for controlling the operating state of at least the gate driver 120, the source driver 130, and a transfer switch circuit 140 described later. The LCD controller 150 that generates and outputs signals (vertical control signals, horizontal control signals, and transfer switch control signals, which will be described later) and display data to be supplied to the source driver 130 based on the video signal are generated. A display signal generation circuit 160 that generates a timing signal to be supplied; a common voltage driving amplifier 170 that applies a common signal voltage Vcom having a predetermined voltage polarity to a common electrode provided in common to all the display pixels Px; Further, as a configuration unique to the present invention, a display signal voltage composed of serial data output from the source driver 130 is disposed in the liquid crystal display panel 110 between the liquid crystal display panel 110 and the source driver 130. Transfer switch circuit distributing and applying to each data line DL (Data distribution means) 140 is provided.

  Here, in this configuration example, as shown in FIG. 2, at least a pixel array PXA in which a plurality of display pixels Px constituting the liquid crystal display panel 110 are two-dimensionally arranged, a gate driver 120, and a transfer switch circuit 140 are provided. In addition, the structure is integrally formed on an insulating substrate SUB such as a glass substrate. The source driver 130 is formed as a driver chip separate from the insulating substrate SUB, and is electrically connected via wiring electrodes (connection contacts; corresponding to connection terminals TMs described later) formed on the insulating substrate SUB. Connected to each other and mounted as an external (retrofit) component on the insulating substrate SUB.

In this case, a pixel transistor (corresponding to the pixel transistor TFT shown in FIG. 18) constituting the display pixel Px, and each functional element (thin film transistor or the like) constituting the gate driver 120 and the transfer switch circuit 140 described later are, for example, Amorphous silicon can be applied and formed by the same manufacturing process. Accordingly, a liquid crystal display device can be manufactured at a low cost by applying an already established technically established amorphous silicon manufacturing process, and a functional element with stable operating characteristics can be realized. Display characteristics can be improved.
The above-described liquid crystal display panel 110 (pixel array PXA) has the same configuration as the configuration shown in the prior art (the liquid crystal display panel 110P shown in FIG. 18), and thus detailed description thereof is omitted. .

Next, each configuration of the liquid crystal display device described above will be specifically described.
FIG. 3 is a schematic configuration diagram illustrating a specific example of a gate driver and a switch driving unit applied to the liquid crystal display device according to this configuration example, and FIG. 4 is applied to the liquid crystal display device according to this configuration example. It is a schematic block diagram which shows an example of a source driver and a transfer switch circuit. Here, description will be made with reference to the configuration shown in FIGS. 1 and 2 as appropriate.

  As shown in FIG. 3, the gate driver 120 includes a shift register 121 that sequentially outputs a shift signal at a predetermined timing based on a gate start signal GSRT and a gate clock signal GPCK supplied as vertical control signals from the LCD controller 150. A 2-input AND operation circuit (hereinafter referred to as an “AND circuit”) having the shift signal output from the shift register 121 as one input and the gate reset signal GRES supplied as a vertical control signal from the LCD controller 150 as the other input. And a plurality of (two stages) level shifters 123 and 124 and an output amplifier (amplifier) 125 for setting (boosting) the output signal from the AND circuit 122 to a predetermined signal level. It has a configuration. Here, the level shifters 123 and 124 and the output amplifier 125 are mainly for driving the shift register 121 at a low voltage, and according to the signal level of the scanning signal applied to the scanning line SL (display pixel Px). It is appropriately provided at the output stage of the gate driver 120.

  In the gate driver 120 having such a configuration, when the gate start signal GSRT and the gate clock signal GPCK are supplied as the vertical control signals from the LCD controller 150, the gate register 120 receives the gate start signal based on the gate clock signal GPCK by the shift register 121. The shift signal is input to one input contact of a plurality of AND circuits 122 provided corresponding to each scanning line while sequentially shifting the GSRT.

  Here, in the state where the gate reset signal GRES is set to the high level (“1”) (the driving state of the gate driver), the “1” level is always input to the other input contact of the AND circuit 122. Based on the start signal GSRT and the gate clock signal GPCK, a high level (“1”) signal is output from the AND circuit 122 at the timing when the shift signal is output from the shift register 121, and the level shifters 123 and 124 and the output amplifier 125 are output. , Scanning signals G1, G2, G3,... Having a predetermined high level are generated and sequentially applied to the scanning lines SL1, SL2, SL3,. As a result, the display pixels Px connected to the scanning lines SL1, SL2, SL3,... Of each row to which the scanning signals G1, G2, G3,.

  On the other hand, in the state where the gate reset signal GRES is set to the low level (“0”) (the reset state of the gate driver 120), the “0” level is always input to the other input contact of the AND circuit 122. Regardless of whether or not a shift signal is output from 121, a low level (“0”) signal is always output from AND 122, so that scanning signals G1, G2, G3,. The display pixels Px that are generated and connected to the scanning lines SL1, SL2, SL3,... Of each row are set in a non-selected state.

  In this configuration example, as shown in FIGS. 2 and 3, a switch driver (switch drive control means) SWD for driving and controlling a transfer switch circuit 140 described later is integrated in the gate driver 120. It has a formed configuration. Here, as shown in FIG. 3, the switch driver SWD has a predetermined timing based on transfer switch control signals (timing signals: multiplexer control signals CNmx0, CNmx1 and switch reset signal SDRES) supplied from the LCD controller 150. In the same manner as the AND circuit 122 described above, the decoder 126 that sequentially outputs the decode signal, and the decode signal output from the decoder 126 as one input, and the gate reset signal GRES supplied from the LCD controller 150 as the other input. An AND circuit 127, a plurality of level shifters (the same configuration as the level shifters 123 and 124 shown in the gate driver 120 described above) and an output amplifier 128 for setting the output signal from the AND circuit 127 to a predetermined signal level, The We have the example was constructed.

  In the switch drive unit SWD having such a configuration, the decode signal generated by the decoder 126 based on the multiplexer control signals CNmx0 and CNmx1 and the switch reset signal SDRES supplied as the transfer switch control signal from the LCD controller 150, The signal is input to one input contact of a plurality of (for example, three) AND circuits 127 provided corresponding to each transfer gate (switch) of the transfer switch circuit 140 described later.

  Here, in the switch driver SWD, the LCD controller 150 in the state where the gate reset signal GRES described above is set to a high level (“1”) (the driving state of the gate driver) as shown in Table 1. When the low level (“0”) switch reset signal SDRES is supplied from the decoder 126, the low level (“0”) decode signal is output from the decoder 126 regardless of the signal levels of the multiplexer control signals CNmx0 and CNmx1. Is constantly input to one of the input contacts, the low level (“0”) switch switching signals SD1 to SD3 are supplied to the transfer switch circuit 140, and the display signal voltage generated by the source driver 130 described later is displayed. The supply to the data line DL of each column is cut off.

  When the high level (“1”) switch reset signal SDRES is supplied from the LCD controller 150, as shown in Table 1, the multiplexer control signals CNmx0, CNmx0, When both CNmx1 are at a low level, only the switch switching signal SD1 is at a high level, when the multiplexer control signal CNmx1 is at a high level, only the switch switching signal SD2 is at a high level, and when the multiplexer control signal CNmx0 is at a high level, the switch is switched. When only the signal SD3 is at a high level and both the multiplexer control signals CNmx0 and CNmx1 are at a high level, the switch switching signals SD1 to SD3 are all set to a low level and are provided in common with the gate driver 120. Level The signal levels of the switch switching signals SD1 to SD3 are boosted through the shifters 123 and 124 and the output amplifier 128, and sequentially transferred to the transfer switch circuit 140 via individual signal lines so as not to overlap each other in time. Applied. As a result, the transfer gates to which the high-level switch switching signals SD1 to SD3 are applied are turned on sequentially (in time series), and the display signal voltage generated by the source driver 130 described later becomes the data line DL of each column. (Signal supply state).

  On the other hand, when the gate reset signal GRES is set to a low level (“0”) (the reset state of the gate driver 120), the “0” level is always input to the other input contact of the AND circuit 127. Regardless of the signal level of the decode signal output from 126, a low level (“0”) signal is always output from the AND circuit 127, and a low level (“0”) switch switching signal SD1 is output to the transfer switch circuit 140. -SD3 are supplied, each transfer gate is turned off, and the supply of the display signal voltage to the data line of each column is cut off (signal cut off state).

  For example, as illustrated in FIG. 4, the source driver 130 outputs a shift register 131 that sequentially outputs a shift signal at a predetermined timing based on a horizontal shift clock signal SCK and a horizontal period start signal STH, and an output from the shift register 131. Display data of a plurality of systems supplied in parallel from the display signal generation circuit 160 according to the shift signal, for example, red component (R), green component (G), and blue component (B) constituting image information A latch circuit (data holding unit) 132 that sequentially fetches three display data Rdata, Gdata, and Bdata consisting of the above and simultaneously outputs the display data fetched in the previous horizontal period in response to a control signal STB, and a multiplexer control Based on the signals CNmx0 and CNmx1, the display data Rdata, A three-input multiplexer (data conversion unit) 133 that converts Gdata, Bdata (that is, parallel data) into one line of pixel data (R, G, B) (that is, serial data) arranged in a time-sharing manner; A digital-analog converter (hereinafter referred to as an analog signal) having a predetermined signal polarity based on the polarity control signal POL is converted from digital-analog to the pixel data (R, G, B) output from the 3-input multiplexer 133. , Abbreviated as “D / A converter”) 134, and the pixel data (R, G, B) subjected to analog conversion are amplified to a predetermined signal level on the basis of the output enable signal OE, and connected via the connection terminal TMs. And an output amplifier 135 that outputs the display signal voltage Vrgb to the transfer switch circuit 140. Here, the horizontal shift clock signal SCK, the horizontal period start signal STH, the control signal STB, the multiplexer control signals CNmx0 and CNmx1, the polarity control signal POL, and the output enable signal OE supplied to each of the above-described components are all LCD controller 150. This is a horizontal control signal supplied from.

  Further, as schematically shown in FIG. 4, the transfer switch circuit 140 is connected in parallel to the connection terminal TMs from which the display signal voltage Vrgb configured in a time division manner is output from the source driver 130 described above. Transfer gates (switches) TG1 to TG3 are provided for the respective data lines DL1 to DL3, DL4 to DL6,... Connected to the display pixels Px corresponding to the RGB colors (in units of 3). It has a configuration. The transfer switch circuit 140 includes three switching control signal lines TL1 to TL3, and the control terminals of the transfer gates TG1 to TG3 are individually connected to the switching control signal lines TL1 to TL3. It is comprised so that.

  Here, each switching control signal line TL <b> 1 to TL <b> 3 has signal input contacts at both ends, and each signal input contact is arranged at both ends of the transfer switch circuit 140. The switch switching signals SD1 to SD3 individually generated and output by the switch driving unit SWD described above are branched into two signal paths, respectively, and a pair of signal inputs provided at both ends of the corresponding switching control signal lines TL1 to TL3. It is supplied from both ends of the switching control signal lines TL1 to TL3 through the contacts. Thereby, the on / off states of the transfer gates TG1 to TG3 are set according to the signal levels of the switch switching signals SD1 to SD3.

  That is, in the source driver 130 and the transfer switch circuit 140 having such a configuration, the display data Rdata, Gdata, and Bdata corresponding to the display pixels Px for each color of RGB for one row from the display signal generation circuit 160 are parallel and The display data Rdata, Gdata, and Bdata corresponding to a set of RGB display pixels are sequentially fetched and held by the latch circuit after being sequentially supplied, and then converted into time-division serial data by the 3-input multiplexer 133. The signal is output to the transfer switch circuit 140 via the converter 134, the output amplifier 135, and the connection terminal TMs.

  At this time, switch switch signals SD1 to SD3 generated based on multiplexer control signals CNmx0 and CNmx1 for controlling serial conversion processing in the three-input multiplexer 133 are transferred from the switch driver SWD provided in the data driver 120 to the transfer switch. By supplying to the circuit 140, the transfer gates TG1 to TG1 provided in the data lines DL1 to DL3, DL4 to DL6,... In synchronization with the time division timing of the display signal voltage Vrgb composed of the time division serial data. The TG3 is selectively turned on so as not to overlap in time.

  Thereby, the display signal voltage Vr based on the red component Rdata of the display data among the time division serial data is supplied to the data lines DL1, DL4, DL7,... DL (k + 1), and the display based on the green component Gdata is performed. The signal voltage Vg is supplied to the data lines DL2, DL5, DL8,... DL (k + 2), and the display signal voltage Vb based on the blue component Bdata is supplied to the data lines DL3, DL6, DL9,. Supplied to 3). Here, k representing the column number of the data line DL is k = 0, 1, 2, 3,.

  For example, the display signal generation circuit 160 extracts a horizontal synchronization signal, a vertical synchronization signal, and a composite synchronization signal from a video signal (composite video signal or the like) supplied from the outside of the liquid crystal display device 100, and sends it to the LCD controller 150 as a timing signal. And supplying predetermined display signal generation processing (pedestal clamp, chroma processing, etc.) to extract R, G, B color luminance signals (display data) included in the video signal, and then analog or digital signals. To the source driver 130.

The LCD controller 150 generates a horizontal control signal and a vertical control signal based on various timing signals such as a horizontal synchronization signal, a vertical synchronization signal, and a system clock supplied from the display signal generation circuit 160, and each of them generates a gate driver. 120 and the source driver 130, and as a function unique to the present invention, a transfer switch control signal for controlling the operation state of the transfer switch circuit 140 is generated, and the switch driver SWD and the source driver 130 of the gate driver 120 are generated. The transfer gates TG1 to TG3 provided in the transfer switch circuit 140 are selectively turned on in synchronization with the supply timing of the display signal voltage Vrgb consisting of time-division serial data from the source driver 130, and Display signal The Vrgb controlled to distribute to the data lines (display pixels).
In this configuration example, the switch driver SWD, the source driver 130, and the transfer switch circuit 140 provided integrally with the gate driver 120 described above are just examples of circuit configurations applicable to the display device according to the present invention. It is only what was shown and this invention is not limited to this structure.

(Drive control method for liquid crystal display device)
Next, a drive control operation in the liquid crystal display device according to this configuration example will be briefly described with reference to the drawings.
FIG. 5 is a timing chart showing the drive control operation of the liquid crystal display device according to this configuration example.

  As shown in the timing chart of FIG. 5, the drive control operation in the liquid crystal display device having the above-described configuration is performed as one scan period SLi (1) from the gate driver 120 with one horizontal period (1H) as one cycle. ≦ i ≦ n), the display pixel Px group in the row is set to a selected state by applying the scanning signal Gi, and three data lines are respectively supplied via the source driver 130 and the transfer switch circuit 140 during the selection period. DL1 to DL3, DL4 to DL6,... As a set, and at the application timing of the switch switching signals SD1 to SD3 (ON operation timing of the transfer gates TG1 to TG3), the data lines DL1 to DL3, DL4 to DL6,. .. Individual display by distributing display signal voltage Vrgb corresponding to display data corresponding to display pixel Px connected to No. Voltage Vr, Vg, by sequentially applied as Vb, executes an operation of writing display data to each display pixel Px in the row.

  Such a write operation is performed in one vertical period (1V = (n + 1) × H) in each of the scanning lines SL1, SL2,... SLn (in this configuration example, the liquid crystal display panel). 110 includes 320 scanning lines SL. N = 320), by sequentially applying scanning signals G1, G2, G3,... Gn, display data for one screen of the liquid crystal display panel. Is written in each display pixel Px. Thereby, each display pixel Px is set to a gradation state corresponding to the display data, so that desired image information is displayed on the liquid crystal display panel 110.

  Therefore, according to the liquid crystal display device according to this configuration example, the display signal voltage supplied to the display pixel Px connected to each data line DL configuring the liquid crystal display panel 110 (pixel area PXA) is generated inside the source driver 130. A plurality of data lines DL are converted into time-division serial data as a set, and output to the transfer switch circuit 140 integrally formed with the pixel area PXA on the insulating substrate SUB. A set of time-division serial data is distributed according to the time-sharing timing and sequentially supplied to each set of data lines DL, whereby a transfer switch circuit 140 provided on the insulating substrate SUB, the insulating substrate 140, Are provided separately, and the data driver is connected to the source driver 130 attached later. It can be connected by a set number of the connection terminals TMs of DL.

  As a result, the number of connection terminals between the liquid crystal display panel 110 and the source driver 130 is reduced to a fraction (1 / number of data lines included in each set; in this configuration example, 1/3 of the number of data lines). Since the pitch between the connection terminals can be designed to be relatively wide, the number of steps in the connection process can be reduced, and a good connection can be achieved even with a relatively low connection accuracy. Thus, the manufacturing cost and the source driver mounting area can be reduced.

  Further, in the configuration in which the display signal voltage is supplied in parallel corresponding to each data line arranged in the liquid crystal display panel as shown in the prior art, display data (pixel data) supplied as a digital signal. It is necessary to provide a D / A converter for analogizing, an output amplifier for amplifying the analog pixel data to a predetermined signal level for each data line. Since the configuration can be reduced to a fraction (a fraction of the number of data lines included in each set), the circuit scale of the source driver can be reduced and the output stage (D / A converter, The power consumed by the output amplifier can be reduced.

  In this configuration example, a switch driver SWD that generates switch switching signals SD1 to SD3 for controlling the conduction states of the transfer gates TG1 to TG3 provided in the transfer switch circuit 140 is provided in the gate driver 120. However, the present invention is not limited to this, and a configuration provided outside the gate driver 120 may be applied. However, as described above, the switch driver has the same configuration as the AND circuit, level shifter, and output amplifier provided in the gate driver, and is controlled based on the gate reset signal GRES that controls the operating state of the gate driver. Therefore, as shown in this configuration example (FIG. 3), it is advantageous to apply the configuration formed integrally with the gate driver to reduce the circuit scale and the number of connection terminals. is doing.

  Further, in this configuration example, the data is supplied as parallel data of a plurality of systems (j is an arbitrary positive integer; 3 systems (j = 3) in the case of corresponding to each color component of RGB as described above). Display data is converted into serial data by a multiplexer (3-input multiplexer 133A) and output from the source driver 130. In the transfer switch circuit 140 attached to the liquid crystal display panel 110 (pixel area PXA), each transfer gate (3 Each set of transfer gates TG1 to TG3) is turned on based on time-division timing to distribute to a plurality (j) of data lines DL, so that display data is simply captured and held. Compared to the conventional source driver that converts the display signal voltage to output, the source driver 130 and the transfer switch circuit 140 is set to perform signal processing in j times the operating speed (j times the clock frequency). Here, it goes without saying that the display data processed by the source driver and the transfer switch circuit is not limited to the three systems described above.

Next, a characteristic configuration of the display device according to the present invention will be specifically described with reference to the drawings.
<First Embodiment>
FIG. 6 is a schematic configuration diagram showing the arrangement of peripheral circuits (gate driver, source driver, and transfer switch circuit) applied to the liquid crystal display device according to the first embodiment and the arrangement structure of connection wirings. Here, about the structure equivalent to the liquid crystal display device mentioned above, the same or equivalent code | symbol is attached | subjected and the description is simplified or abbreviate | omitted.

  In the present embodiment, as shown in FIG. 6, in the liquid crystal display device having the above-described configuration (see FIG. 2), in particular, the switch switching signal SD (SD1 to SD3) generated by the switch driving unit SWD is used. In order to transmit to the transfer switch circuit 140, the connection wiring (wiring groups LA1, LA2) disposed between the gate driver 120 (switch drive unit SWD) and the transfer switch circuit 140 is not shown in the figure. The output contact point of the SWD branches so as to have two signal paths, and one wiring group LA1 is connected to one end side of the switching control line TL (TL1 to TL3) disposed in the transfer switch circuit 140 (in the drawing, Individually connected to signal input contacts NL (NL1 to NL3) provided on the left end side of the transfer switch circuit 140) The other wiring group LA2 is individually connected to the signal input contacts NR (NR1 to NR3) provided on the other end side of the switching control line TL (the right end side of the transfer switch circuit 140 in the figure). Have.

Here, in the present embodiment, for example, as shown in FIG. 6, the wiring group LA1 is arranged so as to have a wiring path that is the shortest path between the gate driver 120 (switch drive unit SWD) and the transfer switch circuit 140. The wiring group LA2 is arranged so as to have a wiring path that bypasses the outside of the mounting region of the source driver 130 (the edge side of the insulating substrate SUB).
That is, the switch switching signal SD generated and output by the switch driving unit SWD is applied in parallel from both ends of each switching control line TL via two signal paths branched from the same signal level. It is configured. For example, the switch switching signal SD1 is transmitted in parallel via the wiring groups LA1 and LA2, and is applied from both ends of the switching control line TL1 via the individual signal input contacts NL1 and NR1.

Here, the effect of applying the arrangement structure of such connection wiring (wiring group) will be described in detail.
First, the effect of the connection structure in which the switch switching signal SD is branched into two signal paths and applied in parallel from both ends of the switching control line TL will be described.
As shown in FIG. 4, the transfer switch circuit 140 has a configuration including a transfer gate TG corresponding to each data line DL, and a plurality of (three in the above configuration example) data lines DL. As a set, a display signal voltage consisting of time-division serial data is supplied, and therefore, the number of switching control lines TL (TL) corresponding to the set of data lines DL group (transfer gate TG group) is provided. TL1 to TL3).

  Therefore, in the operation of applying a predetermined display signal voltage from the source driver 130 to the data lines DL arranged on the display panel 110 via the transfer switch circuit 140 as described above, Control is performed such that a single switch switching signal SD is applied to a plurality of transfer gates TG connected to the control line TL at a predetermined timing (see FIG. 5). Here, each switching control line TL has a capacitance component (load capacitance) such as a gate capacity of a thin film transistor (field effect transistor) constituting each transfer gate TG and a wiring capacity of the switching control line, and the switching control line is originally a switching control line. It has a state equivalent to a configuration in which resistance components such as wiring resistance are connected.

  Therefore, for example, a signal input contact is provided only on one end side with respect to the switching control line TL arranged in the transfer switch circuit 140 (for example, only the left end of the transfer switch circuit 140), and the signal input contact is provided via the signal input contact. When the switch switching signal SD is applied, as the distance from the signal input contact of the switching control signal line TL becomes longer (away from the signal input contact), the resistance component and the capacitance component added to the switching control line become smaller. The time constant (= resistance × capacitance) defined by these resistance components and capacitance components gradually increases, and the rounding of the signal waveform (signal level) of the switch switching signal SD becomes significant. have.

  For this reason, the transfer gate TG arranged at a position farther from the signal input contact gradually delays the operation timing, and the time (writing time) allocated to the writing operation of the display data to each display pixel Px is insufficient. As a result, the writing state becomes insufficient (writing failure occurs), and the area (display area) of the liquid crystal display panel 110 on the signal input contact side of the transfer switch circuit 140 (switching control line TL) and the signal input contact There is a possibility that a difference in light emission luminance occurs between the distant display area (that is, the left and right display areas of the liquid crystal display panel 110) and image quality such as display unevenness is deteriorated.

  Therefore, in the liquid crystal display device according to the first embodiment, as shown in FIG. 6, connection wiring (wiring groups LA1, LA2) for applying the switch switching signal SD to the transfer switch circuit 140 is, for example, Branching from the output end of the switch drive unit SWD so as to have two signal paths, each connected to each signal input contact NL (NL1 to NL3) and NR (NR1 to NR3) provided at both ends of the transfer switch circuit 140 At the same time, one wiring group LA1 of the connection wirings is connected to the signal input contact NL on one end side of the transfer switch circuit 140, for example, so as to have a substantially shortest distance, and the other wiring group LA2 is connected to the transfer wiring circuit LA2. The outside of the source driver 130 (the edge side of the insulating substrate) is connected to the signal input contact NR on the other end side of the switch circuit 140. It has a configuration which is arranged to be connected by turned.

  As a result, the same switch switching signal SD (SD1 to SD3) is applied substantially simultaneously to each of the switching control lines TL (TL1 to TL3) disposed in the transfer switch circuit 140 from both ends. At this time, in the transfer switch circuit 140, the distance from the signal input contact NL or NR of the switching control line TL to any transfer gate TG is ½ or less of the wiring length Ltl of the switching control line TL. Compared with the case where the switch switching signal is applied only from one end side of such a switching control line (which corresponds to the wiring length Ltl of the switching control line TL at the longest), it is added to the switching control line TL. The resistance component and the capacitance component (that is, the time constant defined by the product of both) can be substantially reduced, and the transmission delay of the switch switching signal SD can be greatly suppressed. Therefore, it is possible to suppress the occurrence of defective writing of display data to the display pixels Px, and it is possible to suppress a difference in light emission luminance in the left and right regions of the liquid crystal display panel 110 and suppress deterioration in image quality such as display unevenness. .

  In the present embodiment, of the two signal paths to which the switch switching signal SD is applied, the other wiring group LA2 is arranged to bypass the outside of the source driver 130 (the edge side of the insulating substrate SUB). Therefore, it is possible to avoid a structure in which the wiring between the liquid crystal display panel 110, the transfer switch circuit 140, and the source driver 130 and the connection wiring (wiring group LA2) interfere electrically or physically. A good display operation can be realized by applying a display signal voltage having an appropriate signal level to the display pixel Px.

  Note that, in a region outside the source driver 130 in which the wiring group LA2 is disposed, input signal lines to the source driver 130 (the horizontal control signal and display data shown in FIG. 2 are transmitted) and power supply lines Since the wiring for anodization and the like are arranged, the wiring group LA2 has an intersecting structure (part A in FIG. 6), and the mutual signal level is reduced. Although a variation may occur, a transfer signal to which a display signal voltage output from the source driver 130 is transmitted in an area inside the source driver 130 (that is, an area on the liquid crystal display panel 110 side of the source driver 130). Compared to a structure in which the line group VL and the wiring group LA2 intersect, the direct influence on the display operation can be greatly suppressed.

  In the present embodiment, one wiring group LA1 is disposed so as to have a wiring path that is substantially the shortest between the switch driver SWD and the transfer switch circuit 140, whereas the other wiring group LA2 is disposed. Are arranged so as to bypass the outside of the source driver 130, the wiring lengths are inevitably different, and the transmission time of the switch switching signal SD output from the switch driver SWD is the wiring path (wiring group LA1). , LA2).

  Therefore, in the present embodiment, a low-resistance metal material such as aluminum or aluminum alloy (for example, aluminum-titanium alloy) is applied as the wiring material of the connection wiring, and the connection wiring (wiring) on the side where the wiring length becomes longer is used. In the group LA2), the wiring width and thickness are increased, the wiring structure is laminated, etc., thereby reducing the wiring resistance and switching between the two signal paths between the switch driver SWD and the transfer switch circuit 140. Setting is made so that the transmission delay of the signal SD does not become noticeable.

  When the display device according to this embodiment is applied to a relatively small electronic device such as a mobile phone or a portable information terminal, the wiring length of the connection wiring does not become extremely long, and two signals Since the bias of the switch switching signal transmission delay between paths can be suppressed to a relatively small value, it is not limited to the low-resistance metal material as described above. For example, non-metallic wiring material such as polysilicon or ITO (Indium Tin A transparent electrode material such as Oxide (indium tin oxide) can also be applied.

<Second Embodiment>
Next, a second embodiment of the display device according to the present invention will be described with reference to the drawings.
FIG. 7 is a schematic configuration diagram showing an arrangement of peripheral circuits and a connection wiring arrangement applied to the liquid crystal display device according to the second embodiment, and FIG. It is the schematic which shows the intersection structure of the connection wiring applied. Here, about the liquid crystal display device mentioned above and the structure equivalent to 1st Embodiment, the same or equivalent code | symbol is attached | subjected and the description is simplified or abbreviate | omitted.

  In the first embodiment described above, the arrangement structure of the connection wiring between the switch driver SWD integrally provided in the gate driver 120 and the transfer switch circuit 140 is branched from the switch driver SWD. The case where the other connection wiring (wiring group LA2) of the two arranged signal paths is arranged to bypass the outside of the source driver 130 (the edge side of the insulating substrate SUB) has been described. In this embodiment, the connection wiring is arranged in an inner region of the source driver 130 (specifically, a region between the source driver 130 and the transfer switch circuit 140).

  Specifically, as shown in FIG. 7, in the configuration of the first embodiment described above (see FIG. 6), a connection having two signal paths arranged between the switch driver SWD and the transfer switch circuit 140. Among the wirings, the other wiring group LA2 is disposed so as to pass through a region between the source driver 130 and the transfer switch circuit 140, and is disposed between the wiring group LA2, the source driver 130, and the transfer switch circuit 140. The transfer connection line group VL is configured to have an intersecting structure (B portion in FIG. 7) having wiring patterns orthogonal to each other.

  That is, in the intersecting structure (B portion) applied to this embodiment, as shown in FIG. 8A, the region between the source driver 130 and the transfer switch circuit 140 is defined as the extending direction of the source driver 130 (drawing). In the wiring group LA2 arranged in parallel in the left-right direction), each signal line VLa constituting the transfer connection line group VL is at least in the intersection and the vicinity thereof (intersection wiring area ARc). In a region (inclined wiring region ARs) that is disposed so as to be orthogonal to the wiring group LA2 and is closer to the transfer switch circuit 140 than the intersecting wiring region ARc, the transfer switch circuit 140 extends in the extending direction (left-right direction in the drawing). Each signal line VLa is connected to the cross wiring area AR so as to correspond to the inter-terminal pitch of a plurality of input terminals (not shown). Against the wiring direction, (the alpha 0 ° or more) predetermined angle alpha with a, has disposed the wiring pattern so as to extend in an oblique direction.

  In such a connection wiring arrangement structure, as shown in FIG. 8A, the transfer connection line group VL to which the display signal voltage is transmitted intersects with the wiring group LA2 by applying a laminated structure. However, in the cross wiring area ARc, all the signal lines VLa and the wiring group LA2 constituting the transfer connection line group VL are configured to be orthogonal to each other. The resulting parasitic capacitance can be set substantially uniformly.

  On the other hand, when the transfer connection line group VL and the wiring group LA2 intersect with each other with different predetermined inclination angles as shown in FIG. Since the area varies from wiring to wiring, the parasitic capacitance generated at the intersections varies, and wiring that has an angle of inclination with respect to the orthogonal direction has an electrical connection error or wiring pattern error due to defective etching due to a manufacturing process. Has a problem of being likely to occur.

  Therefore, in order to deal with the problem of such an arrangement structure, in this embodiment, as described above, the intersection structure of the wiring group LA2 and the transfer connection line group VL is arranged so as to be always orthogonal. As a result, the parasitic capacitance generated at the intersection can be made uniform and variation in the wiring capacitance added to the transfer connection line group VL or the wiring group LA2 can be suppressed. Therefore, the capacitance component added to each signal line VLa can be reduced. It can be made substantially uniform to suppress the influence (transmission delay) on the display signal voltage transmitted by the transfer connection line group VL, and the electrical connection state and wiring pattern abnormality of the transfer connection line group VL can be suppressed. Can be improved.

  As a result, as in the first embodiment described above, the same switch switching signal is applied to the switching control line TL (TL1 to TL3) disposed in the transfer switch circuit 140 from both ends of the line TL. Since SD (SD1 to SD3) are applied substantially in parallel, the transmission delay of the switch switching signal SD to each transfer gate TG (TG1 to TG3) is greatly suppressed, and display data is written to the display pixel Px. The occurrence of defects can be suppressed, and the difference in light emission luminance between the left and right regions of the liquid crystal display panel 110 can be suppressed to suppress the deterioration of display image quality.

  Further, according to the arrangement structure of the connection wiring according to the present embodiment, the connection wiring (wiring group LA2) provided between the switch drive unit SWD and the transfer switch circuit 140 is connected to the inside of the source driver 130, that is, Since it can be disposed in the region between the source driver 130 and the transfer switch circuit 140, compared to the case where the connection wiring is disposed outside the source driver 130 (on the edge side of the insulating substrate SUB), By reducing the circuit formation area, the substrate size of the insulating substrate SUB on which the liquid crystal display panel 110 is mounted can be reduced.

<Third Embodiment>
Next, a third embodiment of the display device according to the present invention will be described with reference to the drawings.
FIG. 9 is a schematic configuration diagram showing an example of the arrangement of peripheral circuits and the arrangement structure of connection wirings applied to the liquid crystal display device according to the third embodiment. FIG. 10 is a schematic configuration diagram showing another example of the arrangement of peripheral circuits and the arrangement structure of connection wirings applied to the liquid crystal display device according to the present embodiment. Here, about the liquid crystal display device mentioned above and each structure equivalent to each embodiment, the same or equivalent code | symbol is attached | subjected and the description is simplified or abbreviate | omitted.

  In the first and second embodiments described above, the gate driver 120 including the switch driver SWD, the transfer switch circuit 140, and the source driver 130 are arranged in different directions with respect to the liquid crystal display panel 110 ( That is, the gate driver 120 is arranged in the X direction (left side of the drawing), and the transfer switch circuit 140 and the source driver 130 are arranged in the Y direction (lower side of the drawing). The driver 120 (including the switch driving unit SWD) is formed integrally with the source driver 130 and has a single-chip configuration.

  Specifically, as shown in FIG. 9, the liquid crystal display device according to the present embodiment has each data line DL on one direction side (lower side in the drawing) of the liquid crystal display panel 110 as in the above-described embodiments. A transfer switch circuit 140 having a plurality of transfer gates TG connected to each other, and a display signal voltage composed of time-division serial data based on display data supplied in parallel, and output to the transfer switch circuit 140 At the same time, a scanning signal is applied to each scanning line SL via the lead line group PLA, and a gate / source driver 180 for outputting a switch switching signal SD to the transfer switch circuit 140, and the gate / source The switch switching signal SD generated by the driver 180 is arranged in the transfer switch circuit 140. For outputting to have been switching signal input contact provided on both ends of the control line TL, it comprises connection of two signal paths wiring (wiring group LB1, LB2), the.

  Here, of the connection wirings arranged between the output contact (not shown) of the switch switching signal SD of the gate / source driver 180 and the transfer switch circuit 140, one wiring group LB1 is one end of the transfer switch circuit 140. The signal input contacts NL (NL1 to NL3) provided on the side (the left end side of the transfer switch circuit 140 in the figure) are arranged so as to be connected by the wiring route that is the shortest route, and the other wiring group LB2 is outside (insulated) the gate / source driver 180 with respect to the signal input contacts NR (NR1 to NR3) provided on the other end side of the transfer switch circuit 140 (the right end side of the transfer switch circuit 140 in the figure). In other words, it is configured to be connected by a wiring route that bypasses the edge of the conductive substrate SUB).

  Further, the gate / source driver 180 applied to the present embodiment includes the gate transistor 120 including the switch driver SWD and the source driver 130 shown in the first embodiment (see FIG. 6) described above. However, for example, on one side (left side of the drawing) of the gate / source driver 180, a circuit configuration unit having functions equivalent to those of the switch driving unit and the gate driver (in the figure, a dotted line) CTG) is provided. For this reason, as shown in FIG. 9, a connection wiring (wiring group) which is provided on the left side of the gate / source driver 180 and is branched from the output contact point of the switch switching signal SD and has two signal paths. LB1 and LB2) are individually connected to respective signal input contacts NL and NR provided at both ends of the transfer switch circuit 140 (switching control line TL).

  According to the liquid crystal display device having such a configuration, the gate driver 120 is not disposed in the side region of the liquid crystal display panel 110 (pixel array PXA) (the left and right regions of the liquid crystal display panel 110 in the drawing). The width of the region can be designed to be narrow, and when the liquid crystal display device according to this embodiment is applied to, for example, a mobile phone or a personal digital assistant (PDA), the display device can be narrowed. In addition, since the gate driver (including the switch driver) and the source driver can be integrally formed into one chip, the number of peripheral circuit components can be reduced and the manufacturing process can be simplified. The product cost of the liquid crystal display device can be reduced.

  In the configuration example shown in FIG. 9, the other side of the two signal paths connecting the gate / source driver 180 (specifically, the output contact of the switch switching signal SD) and the transfer switch circuit 140 is provided. The configuration in which the wiring group LB2 is arranged so as to bypass the outside of the gate / source driver 180 has been shown, but as shown in FIG. 10, the area inside the gate / source driver 180 (specifically, The wiring group LB2 may be disposed in a region between the gate / source driver 180 and the transfer switch circuit 140.

Also in this case, as in the configuration shown in FIG. 8, the transfer connection line group VL connecting the gate / source driver 180 and the transfer switch circuit 140 is at least in the intersection region with the wiring group LB2. A wiring pattern is formed so as to be orthogonal to.
According to such a circuit configuration, the capacitance component added to each signal line VLa of the transfer connection line group VL due to the crossing structure with the wiring group LB2 is made substantially uniform, and each display pixel Px (each data line) DL) can be suppressed from being influenced by the display signal voltage, and the side area and the upper and lower areas of the liquid crystal display panel 110 can be narrowed to reduce the product size.

<Fourth Embodiment>
Next, a fourth embodiment of a display device according to the present invention will be described with reference to the drawings.
FIG. 11 is a schematic configuration diagram showing a peripheral circuit arrangement and a connection wiring arrangement applied to the liquid crystal display device according to the fourth embodiment. Here, about the liquid crystal display device mentioned above and each structure equivalent to each embodiment, the same or equivalent code | symbol is attached | subjected and the description is simplified or abbreviate | omitted.

  In the above-described third embodiment, the gate driver (including the switch driving unit) is integrally formed with the source driver, and the gate / source driver 180 is configured as one chip. Although the case where the output contact of the signal SD is arranged biased to one side (left side) of the gate / source driver 180 has been described, in this embodiment, the internal structure of the gate / source driver 180 is further increased. Customized (specialized), the output contacts of the switch switching signal SD are arranged so as to correspond to the signal input contacts NL and NR provided at both ends of the transfer switch circuit 140.

  Specifically, as shown in FIG. 11, in the liquid crystal display device according to the present embodiment, the gate driver and the source driver are integrally formed, and in the gate / source driver 180 formed as one chip, the switch switching signal SD is formed. The output contacts are provided at both ends of the gate / source driver 180 so as to correspond to the positions of the signal input contacts provided at both ends of the transfer switch circuit 140. In this case, for example, a circuit component (indicated by a dotted line in the figure) CTG that is provided in the gate / source driver 180 and generates both ends of the gate / source driver 180. By connecting a contact (not shown) by the internal wiring group LC3, the switch switching signal SD is sent from the output contact disposed near the signal input contacts NL and NR provided at both ends of the transfer switch circuit 140. Configure for output.

  As a result, any of the connection wirings (wiring groups LC1 and LC2) having two signal paths disposed between the output contact of the switch switching signal SD of the gate / source driver 180 and the transfer switch circuit 140 is transferred to the transfer switch circuit. Since each signal input contact NL, NR provided in 140 is connected by a wiring path that is substantially the shortest path, the wiring length between the gate / source driver 180 and the transfer switch circuit 140 is The variation in the signal delay of the switch switching signal SD caused by the difference can be suppressed to suppress the display data writing failure, the display image quality can be improved, and the wiring route of the connection wiring can be shortened and simplified. The product size can be reduced.

<Fifth Embodiment>
Next, a display device according to a fifth embodiment of the invention will be described with reference to the drawings.
FIG. 12 is a schematic configuration diagram showing an example of a peripheral circuit arrangement and a connection wiring arrangement applied to the liquid crystal display device according to the fifth embodiment. FIG. 13 is a schematic configuration diagram showing another example of the arrangement of peripheral circuits and the arrangement structure of connection wirings applied to the liquid crystal display device according to the present embodiment. Here, about the liquid crystal display device mentioned above and each structure equivalent to each embodiment, the same or equivalent code | symbol is attached | subjected and the description is simplified or abbreviate | omitted.

  In the third and fourth embodiments described above, the case where the gate driver (including the switch driving unit) is integrally formed with the source driver and is configured as one chip as the gate / source driver 180 has been described. However, in the present embodiment, the gate is arranged in the same arrangement direction as the source driver 130 (the lower region of the liquid crystal display panel 110) with respect to the liquid crystal display panel 110 and adjacent to the source driver 130. The driver 120 is arranged individually.

  Specifically, as shown in FIG. 12, in the liquid crystal display device according to the present embodiment, the transfer switch circuit 140 and the source driver 130 are arranged on one direction side (lower side in the drawing) of the liquid crystal display panel 110. In addition, a scanning signal is applied to each scanning line SL provided in the liquid crystal display panel 110 in a region adjacent to the source driver 130 (for example, on the left side in the drawing) via the lead line group PLA, and transfer is performed. The switch circuit 140 has a configuration in which a gate driver 120 including a switch driving unit (not shown) that outputs a switch switching signal SD is disposed, and the switch switching signal SD generated in the switch driving unit is the gate driver 120. A connection wiring (wiring group L) composed of two parallel signal paths from an output contact (not shown) provided in 1, LD2) via a transfer switch circuit 140 at both ends provided with signal input contacts NL, and is configured to be input to the NR.

Here, of the connection wirings arranged between the output contact (not shown) of the switch switching signal SD of the gate driver 120 and the transfer switch circuit 140, one wiring group LD1 is connected to one end side of the transfer switch circuit 140 ( In the figure, a signal input contact NL (NL1 to NL3) provided on the left end side of the transfer switch circuit 140 is disposed so as to be connected by a wiring path that is substantially the shortest path, and the other wiring group LD2 However, with respect to the signal input contacts NR (NR1 to NR3) provided on the other end side (the right end side of the transfer switch circuit 140 in the figure) of the transfer switch circuit 140, the outside of the source driver 130 (insulating substrate SUB). The edge side) of the circuit board is connected by a wiring route that bypasses the edge side.
According to the display device having such a configuration, as in the case of the third and fourth embodiments described above, the lateral region of the liquid crystal display panel 110 (pixel array PXA) (the left and right sides of the liquid crystal display panel 110). Since the gate driver 120 is not disposed in the region), the display device can be narrowed by designing the region to be narrow.

  In the configuration example shown in FIG. 12, the wiring group LD2 on the other side of the two signal paths connecting the gate driver 120 and the transfer switch circuit 140 is bypassed outside the source driver 130. As shown in FIG. 13, the wiring group LD2 is arranged in the inner region of the source driver 130 (that is, the region between the source driver 130 and the transfer switch circuit 140). Also good.

Also in this case, as shown in FIG. 8, the transfer connection line group VL connecting the source driver 130 and the transfer switch circuit 140 is orthogonal to each other at least in the intersection region with the wiring group LD2. A wiring pattern is formed.
According to such a circuit configuration, it is possible to uniformize the capacitance component caused by the crossing structure with the wiring group LB2 and suppress the influence on the display signal voltage, It is possible to reduce the product size by narrowing the upper and lower regions.

<Sixth Embodiment>
Next, a sixth embodiment of the display device according to the present invention will be described with reference to the drawings.
FIG. 14 is a schematic configuration diagram showing an example of a peripheral circuit arrangement and a connection wiring arrangement applied to the liquid crystal display device according to the sixth embodiment. FIG. 15 is a schematic configuration diagram showing another example of the peripheral circuit arrangement and the connection wiring arrangement applied to the liquid crystal display device according to the present embodiment. Here, about the liquid crystal display device mentioned above and each structure equivalent to each embodiment, the same or equivalent code | symbol is attached | subjected and the description is simplified or abbreviate | omitted.

  In the above-described fifth embodiment, the liquid crystal display panel 110 has the same arrangement direction as the source driver 130 (the lower region of the liquid crystal display panel 110) and is adjacent to the source driver 130. In the present embodiment, the case of having a configuration in which only one gate driver 120 is arranged has been described. However, in this embodiment, the gate driver (including the switch driving unit) is set to 2 corresponding to the scanning line SL arranged in the liquid crystal display panel 110. It has a configuration in which it is divided and individually arranged in regions on both sides of the source driver 130.

  Specifically, as shown in FIG. 14, in the liquid crystal display device according to the present embodiment, a transfer switch circuit 140 and a source driver 130 are arranged on one direction side (lower side in the drawing) of the liquid crystal display panel 110. The lead line groups PLL and PLR are respectively arranged in adjacent regions (left and right adjacent to the drawing) on both sides of the source driver 130 with respect to the scanning line groups arranged in a predetermined region of the liquid crystal display panel 110. And a switch drive unit (not shown) for individually supplying a switch switching signal SD to the signal input contacts NL and NR provided at both ends of the transfer switch circuit 140. The gate drivers 120L and 120R thus arranged (one pair) are arranged.

  Here, the gate driver 120R provided in the region on the right side of the source driver 130 is, for example, a scanning line disposed in the display region of the upper half (first half) of the liquid crystal display panel 110 via the lead line group PLR. On the other hand, the gate driver 120L connected to the SL and provided in the region on the left side of the source driver 130 is disposed in the lower half (second half) display region of the liquid crystal display panel 110 via the lead line group PLL. It is connected to the scanning line SL.

  Therefore, in the drive control operation of the liquid crystal display panel 110, in the first half of the display period, the scanning signal output from the gate driver 120R is scanned from the uppermost scanning line of the liquid crystal display panel 110 to the scanning line (liquid crystal display) in the substantially central portion. The display signal voltage (display data) is sequentially applied downward to the display pixels Px of each row until the scanning line (the lowermost display area in the upper half of the display area of the panel 110), and then in the second half of the display period. The scanning signal output from the gate driver 120L is from the scanning line at the substantially central portion of the liquid crystal display panel 110 (the scanning line which is the uppermost portion of the display area of the lower half of the liquid crystal display panel 110) to the lowermost scanning line. The display signal voltage (display data) is written to the display pixels Px in each row by being sequentially applied downward. By being continuously performed, a desired image information is displayed.

  Further, an output contact (not shown) of the switch switching signal SD of the gate driver 120L and a signal input contact NL (NL1 to NL1) provided on one end side of the transfer switch circuit 140 (left end side of the transfer switch circuit 140 in the figure). NL3) is connected to, for example, a wiring group LE1 connected so as to have a wiring path that is substantially the shortest path, an output contact (not shown) of a switch switching signal SD of the gate driver 120R, and a transfer For example, a wiring path that is substantially the shortest path is provided between the switch circuit 140 and the signal input contacts NR (NR1 to NR3) provided on the other end side (the right end side of the transfer switch circuit 140 in the figure). The wiring group LE2 connected to is connected.

  Here, it is desirable that the wiring groups LE1 and LE2 are configured to have the same or equivalent wiring length. The switch switching signals SD (SD1 to SD3) generated in the gate drivers 120L and 120R are synchronized with each other corresponding signals (for example, the switch switching signals SD1 generated individually in the gate drivers 120L and 120R). And they are set to have the same signal level.

  According to the display device having such a configuration, the wiring lengths of the connection wirings (wiring groups LE1, LE2) disposed between the gate drivers 120L, 120R and the transfer switch circuit 140 can be made uniform, Since it can be shortened, signal delay and signal level deterioration caused by the resistance component and capacitance component added to the connection wiring are suppressed, and the switching control line TL (TL1) provided in the transfer switch circuit 140 is suppressed. To TL3), the switch switching signal SD can be supplied from both ends, and the display image quality can be further improved. In addition, the wiring path of the display device can be simplified, the display device can be narrowed, and the display device can be reduced in size and product cost.

  In the configuration example shown in FIG. 14, the gate drivers 120 </ b> R and 120 </ b> L arranged on both sides of the source driver 130 cause the display pixels Px arranged in the display area above or below the liquid crystal display panel 110 to be displayed. FIG. 15 shows a configuration in which the lead wiring groups PLR and PLL of the scanning line SL are connected so that the display signal voltage is sequentially written. As shown in FIG. 15, each gate driver arranged on both sides of the source driver 130 is shown. 120R and 120L lead wiring groups so that display signal voltages are sequentially written to display pixels Px connected to odd-numbered scan lines (odd-numbered lines) or even-numbered scan lines (even-numbered lines) of the liquid crystal display panel 110. The PLR is connected between the gate driver 120R and the odd lines, and the lead wiring group PLL is the gate driver. It may be configured to apply the connection configurations between 20L and even lines.

<Seventh Embodiment>
Next, a display device according to a seventh embodiment of the invention will be described with reference to the drawings.
FIG. 16 is a schematic configuration diagram showing a peripheral circuit arrangement and a connection wiring arrangement applied to the liquid crystal display device according to the seventh embodiment. Here, about the liquid crystal display device mentioned above and each structure equivalent to each embodiment, the same or equivalent code | symbol is attached | subjected and the description is simplified or abbreviate | omitted.

  In the above-described sixth embodiment, the liquid crystal display panel 110 is adjacent to both sides of the source driver 130 in the same arrangement direction as the source driver 130 (lower region of the liquid crystal display panel 110). As described above, the configuration is shown in which the gate drivers (including the switch drive unit) 120R and 120L divided into two are individually arranged. However, in this embodiment, the two gate drivers are integrally formed with the source driver. It has a one-chip configuration.

  Specifically, as shown in FIG. 16, in the liquid crystal display device according to the present embodiment, a transfer switch circuit 140 is disposed on one direction side (lower side in the drawing) of the liquid crystal display panel 110, and a time-division serial interface is provided. A display signal voltage composed of data is generated and output to the transfer switch circuit 140, and the scanning line SL group disposed in a predetermined area of the liquid crystal display panel 110 is respectively connected to the scanning line SL via the lead line groups PLL and PLR. And a gate / source driver 190 for individually outputting the switch switching signal SD to the signal input contacts NL and NR provided at both ends of the transfer switch circuit 140.

  Here, the gate / source driver 190 has a configuration in which the gate transistors 120L and 120R and the source driver 130 are integrally formed as shown in the above-described sixth embodiment (see FIG. 14). For example, one side (left side of the drawing) of the gate / source driver 190 is connected to the above-mentioned signal input contacts NL and NR provided at both ends of the transfer switch circuit 140 (switching control line TL). A circuit configuration unit (shown by a dotted line in the drawing) CTL having a function equivalent to that of the gate driver 120L is provided, and a circuit configuration unit having a function equivalent to that of the gate driver 120R is provided on the other side (right side of the drawing). A CTR (indicated by the dotted line in the figure) is provided.

  Therefore, as shown in FIG. 16, the output contact of the switch switching signal SD provided on one side of the gate / source driver 190 and the signal input contact NL provided on one end of the transfer switch circuit 140 (switching control line TL). For example, a wiring group LF1 connected so as to have a wiring path that is substantially the shortest path is connected to the output contact point of the switch switching signal SD provided on the other side of the gate / source driver 190 and the transfer Also connected to the signal input contact NR provided on the other end side of the switch circuit 140 is, for example, a wiring group LF1 connected so as to have a wiring path that is substantially the shortest path.

Here, it is desirable that the wiring groups LF1 and LF2 are configured to have the same or equivalent wiring length. The switch switching signals SD (SD1 to SD3) output from the left and right sides of the gate / source driver 190 are set so that corresponding individual signals are synchronized with each other and have the same signal level. ing.
Note that the scanning lines SL arranged in the upper half (first half) display area of the liquid crystal display panel 110 are connected to, for example, a circuit configuration unit CTR on the right side of the gate / source driver 190 via the lead line group PLR. On the other hand, the scanning lines arranged in the lower half (second half) display area of the liquid crystal display panel 110 are connected to the circuit configuration unit CTL on the left side of the gate / source driver 190 via the lead line group PLL. ing.

  According to the display device having such a configuration, the wiring lengths of the connection wirings (wiring groups LF1 and LF2) disposed between the gate / source driver 190 and the transfer switch circuit 140 can be made uniform and short. Therefore, signal delay and signal level deterioration due to the resistance component and capacitance component added to the connection wiring can be suppressed, and display image quality can be further improved. In addition, the wiring path of the display device can be simplified, the lateral region of the liquid crystal display panel 110 can be designed to be narrow, the display device can be narrowed, and the gate driver (switch drive unit) And the source driver can be formed as a single chip, so that the number of components in the peripheral circuit can be reduced to reduce the size of the display device and the product cost.

  In each of the embodiments described above, the case where the display device according to the present invention is applied to a liquid crystal display device has been described. However, the present invention is not limited to this, and the display image quality is increased. The technical idea of the present invention can be applied satisfactorily when the number of data lines of the display panel increases and the pitch between terminals becomes narrow, resulting in problems in the manufacturing process. Therefore, it goes without saying that the present invention can be applied not only to a liquid crystal display panel but also to other display panels such as an organic EL panel. Furthermore, in the case of application to a display panel that supports an active matrix drive system, the gate driver and the switch drive unit can be configured integrally, so that the circuit configuration and the drive control method (control signal Common to both sides of processing and the like.

It is a schematic block diagram which shows the whole structure of the liquid crystal display device to which the display apparatus which concerns on this invention is applied. It is a schematic block diagram which shows the principal part structural example of the liquid crystal display device to which the display apparatus which concerns on this invention is applied. It is a schematic block diagram which shows a specific example of the gate driver applied to the liquid crystal display device which concerns on this structural example, and a switch drive part. It is a schematic block diagram which shows a specific example of the source driver applied to the liquid crystal display device which concerns on this structural example, and a transfer switch circuit. 6 is a timing chart illustrating a drive control operation of the liquid crystal display device according to the present configuration example. FIG. 2 is a schematic configuration diagram showing an arrangement of peripheral circuits (gate driver, source driver, and transfer switch circuit) applied to the liquid crystal display device according to the first embodiment and an arrangement structure of connection wirings. It is a schematic block diagram which shows arrangement | positioning structure of the peripheral circuit applied to the liquid crystal display device which concerns on 2nd Embodiment, and arrangement | positioning of connection wiring. It is the schematic which shows the intersection structure of the connection wiring applied to the liquid crystal display device which concerns on this embodiment. It is a schematic block diagram which shows an example of arrangement | positioning of the peripheral circuit applied to the liquid crystal display device which concerns on 3rd Embodiment, and the arrangement structure of connection wiring. It is a schematic block diagram which shows the other example of arrangement | positioning of the peripheral circuit applied to the liquid crystal display device which concerns on this embodiment, and the arrangement structure of connection wiring. It is a schematic block diagram which shows the arrangement | positioning structure of the peripheral circuit applied to the liquid crystal display device which concerns on 4th Embodiment, and the arrangement | positioning of connection wiring. It is a schematic block diagram which shows an example of arrangement | positioning of the peripheral circuit applied to the liquid crystal display device which concerns on 5th Embodiment, and the arrangement structure of connection wiring. It is a schematic block diagram which shows the other example of arrangement | positioning of the peripheral circuit applied to the liquid crystal display device which concerns on this embodiment, and the arrangement structure of connection wiring. It is a schematic block diagram which shows an example of arrangement | positioning of the layout of the peripheral circuit applied to the liquid crystal display device which concerns on 6th Embodiment, and connection wiring. It is a schematic block diagram which shows the other example of arrangement | positioning of the peripheral circuit applied to the liquid crystal display device which concerns on this embodiment, and the arrangement structure of connection wiring. It is a schematic block diagram which shows the arrangement structure of the peripheral circuit applied to the liquid crystal display device which concerns on 7th Embodiment, and the arrangement structure of connection wiring. It is a block diagram which shows schematic structure of the liquid crystal display device provided with the thin film transistor (TFT) type display pixel in a prior art. It is an equivalent circuit diagram which shows an example of the principal part structure of the liquid crystal display panel in a prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Liquid crystal display device 110 Liquid crystal display panel 120 Gate driver 130 Source driver 140 Transfer switch circuit 150 LCD controller 180, 190 Gate source driver SWD Switch drive part

Claims (7)

A plurality of scanning lines and a plurality of signal lines are arranged so as to be orthogonal to each other, and a display panel in which a plurality of display pixels are two-dimensionally arranged in the vicinity of the intersection of the signal lines and the scanning lines is provided. In a display device that displays a desired image information by supplying a display signal voltage based on display data to a pixel, causing each of the plurality of display pixels to display a gradation,
at least,
Scan driving means for sequentially applying scanning signals to the scanning lines of each row at a predetermined timing to set the display pixels of the row to a selected state;
A data holding unit that takes in the display data supplied from the outside and holds it in parallel, and the display data held in parallel in the data holding unit is time-divided for each predetermined number of display data Signal driving means having a data conversion unit for converting into pixel data arranged in an array,
The signal is interposed between the display panel and the signal driving means, directly connected to the plurality of signal lines, and connected to the predetermined number of the signal lines via a plurality of connection terminals. A row having a plurality of switches for applying the display signal voltage based on the pixel data supplied from the driving means to the predetermined number of the signal lines in a time-sharing manner and set in the selected state Data distribution means for individually applying the distributed display signal voltage to the plurality of display pixels via the predetermined number of the signal lines;
A plurality of signal wirings disposed between each of the plurality of connection terminals and the data distribution unit, and transmitting the display signal voltage before the data distribution unit;
Switch drive control means for generating a switch switching signal for controlling the conduction state of the plurality of switches in the data distribution means based on a predetermined timing signal;
Connected to an output contact of the switch switching signal in the switch drive control means and a pair of signal input contacts provided at both ends of a switching control line for supplying the switch switching signal to the plurality of switches in the data distribution means. A connection wiring arranged to be branched into two signal paths between the output contact and the pair of signal input contacts ;
Equipped with,
The connection wiring disposed in one of the two signal paths in the connection wiring is disposed so as to pass through a region intersecting with the plurality of signal wirings via an insulating film,
The plurality of signal wirings are disposed so as to be orthogonal to the connection wiring in a region intersecting with the connection wiring disposed in the one signal path, and in the region not intersecting with the connection wiring, the data distribution unit A display device comprising a wiring pattern extending in an oblique direction so as to be connected to the display device.   The plurality of switches are provided corresponding to each of the plurality of signal lines, and selectively based on the switch switching signal in synchronization with time division timing used for conversion of the display data in the data conversion unit. The display device according to claim 1, wherein the display device is set in a conductive state.   The display device according to claim 1, wherein the switch drive control unit is configured integrally with the scan drive unit.   The display device according to claim 1, wherein at least the display panel, the scan driving unit, and the data distribution unit are integrally formed on a single insulating substrate. .   5. The display device according to claim 1, wherein the scanning driving unit is configured integrally with the signal driving unit.   5. The display device according to claim 1, wherein the scanning driving unit is uniquely arranged on one side of the display panel so as to be adjacent to the signal driving unit. Each of the plurality of display pixels includes a pixel transistor having a gate electrode connected to the scan line, a drain electrode connected to the signal line, and a source electrode connected to the pixel electrode, and the pixel electrode and the pixel electrode. A pixel capacitor formed by filling liquid crystal molecules between common electrodes that are commonly provided opposite to each other, and an auxiliary capacitor connected in parallel to the pixel capacitor,
By applying the display signal voltage based on the pixel data, any one of claims 1 to 6, characterized in that the alignment state of the liquid crystal molecules filled in the display pixel is controlled gray scale display The display device described in 1.

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