JP2005055616A - Display device and its driving control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device which can be reduced in a packaging area and can be improved in operation characteristics at a relatively low manufacturing cost without requiring an increase of man-hours for connection of a display panel and peripheral circuits and high connection accuracy and its driving control method. <P>SOLUTION: The liquid crystal display device 100 has a configuration equipped with at least a liquid crystal display panel 110 (a pixel area PXA) arranged two-dimensionally with a plurality of display pixels Px, a gate driver 120 which successively applies scanning signals to respective scanning lines SL, a source driver 130 which applies the display signal voltage based on display data to respective data lines DL, and a transfer switch circuit 140 which applies the display signal voltage consisting of the serial data outputted from the source driver 130 between the liquid crystal display panel 110 and the source driver 130 by distributing the display signal voltage to the respective data lines DL disposed in the liquid crystal display panel 110. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a display device and a drive control method thereof, and more particularly, to a display device including a display panel corresponding to an active matrix drive method and a drive control method thereof.

  In recent years, as a display device (display) for displaying images, character information, etc. in imaging devices such as digital video cameras and digital still cameras, which are remarkably popular, and portable devices such as mobile phones and personal digital assistants (PDAs), Liquid crystal displays (LCDs) that are thin, lightweight, low power consumption, and have excellent display image quality as monitors and displays for information devices such as computers and video equipment such as televisions. Is frequently used.

Hereinafter, a conventional liquid crystal display device will be briefly described.
FIG. 13 is a block diagram illustrating a schematic configuration of a liquid crystal display device including a thin film transistor (TFT) type display pixel according to the prior art, and FIG. 14 is an equivalent diagram illustrating an example of a main configuration of a liquid crystal display panel according to the prior art. It is a circuit diagram.
As shown in FIGS. 13 and 14, the liquid crystal display device 100P according to the prior art is roughly a liquid crystal display panel (display panel) 110P in which display pixels Px are two-dimensionally arranged (for example, arranged in n rows × m columns). And a gate driver (scanning driver) 120P that sequentially scans the display pixels Px group in each row of the liquid crystal display panel 110P to set the selected state, and a display pixel Px group in the row that is set to the selected state. Generates and outputs a source driver (data driver) 130P that collectively outputs display signal voltages based thereon, and control signals (horizontal control signal, vertical control signal, etc.) for controlling operation timing in the gate driver 120P and the source driver 130P LCD controller 150P, and various timing signals (horizontal synchronization signal, vertical synchronization signal, composite Display signal generation circuit 160P that generates display data consisting of luminance signals and outputs it to the data driver 130P, and a polarity inversion signal generated by the LCD controller 150P. Based on FRP, a common signal drive amplifier (drive amplifier) that applies a common signal voltage Vcom having a predetermined voltage polarity to a common electrode (counter electrode) provided in common to each display pixel Px of the liquid crystal display panel 110P ) 170P.

  Here, the liquid crystal display panel 110P includes, for example, a plurality of scanning lines SL and a plurality of data lines DL arranged between the opposing transparent substrates so as to be orthogonal to each other in the matrix direction, as shown in FIG. And a plurality of display pixels (liquid crystal display pixels) Px arranged in the vicinity of the intersections of the scanning lines SL and the data lines DL. Each display pixel Px includes a pixel transistor TFT composed of a thin film transistor having a source-drain (current path) connected between the pixel electrode and the data line DL, and a gate (control terminal) connected to the scan line SL, and a pixel electrode. And a pixel capacitor (liquid crystal capacitor) Clc composed of liquid crystal molecules filled and held between the common electrode and the pixel electrode provided in common to all display pixels Px, and a pixel capacitor Clc. And an auxiliary capacitor (storage capacitor) Cs for holding the signal voltage applied to the pixel capacitor Clc.

  Note that the scanning line SL and the data line DL provided on the liquid crystal display panel 110P are connected to the gate driver 120P and the source driver 130P provided separately from the liquid crystal display panel 110P via the connection terminals TMg and TMs, respectively. Configured to be connected. In addition, an electrode (auxiliary electrode) on the other end side of the auxiliary capacitor Cs is configured to be applied with a predetermined voltage Vcs (for example, a common signal voltage Vcom) via a common connection line CL.

  In the liquid crystal display device having such a configuration, the display data corresponding to the display pixels for one row of the liquid crystal display panel 110P supplied from the display signal generation circuit 160P is the horizontal control signal supplied from the LCD controller 150P. Based on this, it is sequentially captured and held by the source driver 130P. On the other hand, based on a vertical control signal supplied from the LCD controller 150P, a scanning signal is sequentially applied to each scanning line SL disposed on the liquid crystal display panel 110P by the gate driver 120P, and the display pixels Px group in each row are selected. Set to The source driver 130P supplies the display signal voltages based on the held display data to the display pixels Px simultaneously through the data lines DL in synchronization with the selection timing of the display pixels Px group in each row. By repeating such a series of operations for each row for one screen, desired image information based on the video signal is displayed on the liquid crystal display panel 110P.

  As the mounting structure of the liquid crystal display device, as shown in FIG. 13 and FIG. 14, separately from an insulating substrate such as a glass substrate that constitutes the liquid crystal display panel 110P (where the display pixels Px are formed), In addition to the configuration in which the gate driver 120P and the source driver 130P, which are peripheral circuits, are provided and the liquid crystal display panel 110P and the peripheral circuit are electrically connected via the connection terminals TMg and TMs, on the insulating substrate, for example, There is also known a configuration in which the gate driver 120P and the source driver 130P are formed integrally with the display pixel Px by applying a polysilicon transistor. The schematic configuration, mounting structure, and the like of such a liquid crystal display device are disclosed in, for example, Patent Document 1 and the like.

JP 2000-267590 (3rd page, FIG. 1)

However, the liquid crystal display device as described above has the following problems.
That is, as shown in FIGS. 13 and 14, in the configuration in which the liquid crystal display panel 110P and the gate driver 120P and the source driver 130P as peripheral circuits are separately provided, the liquid crystal display panel 110P is provided to improve the display image quality. In the case of high definition, the number of data lines is increased, thereby increasing the number of connection terminals for connecting the liquid crystal display panel 110P and the gate driver 120P or the source driver 130P and reducing the pitch between the connection terminals. Therefore, the number of steps in the connection process for connecting the peripheral circuit to the liquid crystal display panel 110P increases, and high connection accuracy is required, resulting in an increase in manufacturing cost and the mounting area of the gate driver and the source driver. Had the problem of increasing.

  As a technique for solving the problem of man-hours and connection accuracy related to the connection between the liquid crystal display panel and the peripheral circuit, and further the problem of the mounting area, as shown in the above-mentioned Patent Document 1 and the like, There is known a configuration in which a liquid crystal display panel, a gate driver, and a source driver are integrally formed on a single insulating substrate by applying a polysilicon transistor. Here, as is well known, the manufacturing process of a polysilicon transistor is complicated and the manufacturing cost is expensive compared to an amorphous silicon transistor in which a manufacturing technique has already been established and good element characteristics (operation characteristics) can be obtained. In addition, since the operation characteristics are insufficient, the product cost of the liquid crystal display device is increased, and it is difficult to obtain stable display characteristics.

  Therefore, in view of the above-described problems, the present invention reduces the mounting area (device scale) at a relatively low manufacturing cost without requiring an increase in the number of connection steps between the display panel and the peripheral circuit and high connection accuracy. It is another object of the present invention to provide a display device and a drive control method thereof that can improve operation characteristics (display characteristics).

  The invention according to claim 1 is a display panel in which a plurality of signal lines and a plurality of scanning lines are arranged so as to be orthogonal to each other, and a plurality of display pixels are two-dimensionally arranged in the vicinity of the intersection of the signal lines and the scanning lines. In addition, in a display device that displays desired image information based on display data, at least a scanning signal is sequentially applied to the scanning lines of each row at a predetermined timing to set the display pixels of the row to a selected state. Drive means, a data holding unit that takes in the display data supplied from the outside and holds it in parallel, and the display data held in parallel in the data holding unit for each predetermined number of display data A data conversion unit that converts the data into pixel data arranged in a time-sharing manner, and interposed between the display panel and the signal drive unit, the predetermined number of A plurality of switches for sequentially applying the display signal voltage based on the pixel data supplied from the signal driving means to the predetermined number of the signal lines via a connection terminal provided in common for each signal line. And data distribution means for individually applying display signal voltages based on the display data to the plurality of display pixels in the row set in the selected state.

According to a second aspect of the present invention, in the display device according to the first aspect, the data holding unit fetches a plurality of lines of the display data in parallel and holds them in parallel.
According to a third aspect of the present invention, in the display device according to the first aspect, the data holding unit sequentially takes in the display data of one system and holds it in parallel.
According to a fourth aspect of the present invention, in the display device according to any one of the first to third aspects, the plurality of switches are individually provided for each of the signal lines to convert the display data in the data conversion unit. It is characterized in that it is selectively set in a conductive state in synchronization with the time division timing used.

According to a fifth aspect of the present invention, in the display device according to any one of the first to fourth aspects, the display device controls a conduction state of the plurality of switches in the data distribution unit based on a predetermined timing signal. The apparatus further comprises switch drive control means for generating a switch switching signal for the purpose.
According to a sixth aspect of the present invention, in the display device according to the fifth aspect, the switch drive control means is configured integrally with the scan drive means.

According to a seventh aspect of the present invention, in the display device according to the fifth or sixth aspect, the display device is based on a vertical control signal supplied to the scan driving means and a horizontal control signal supplied to the signal driving means. And a control signal generating means for generating the timing signal.
According to an eighth aspect of the present invention, in the display device according to any one of the first to seventh aspects, the data distribution unit is configured integrally with the signal driving unit.
According to a ninth aspect of the present invention, in the display device according to any one of the first to seventh aspects, at least the display panel, the scanning drive unit, and the data distribution unit are integrated on a single insulating substrate. It is comprised by these.

  According to a tenth aspect of the present invention, in the display device according to any one of the first to ninth aspects, each of the plurality of display pixels has a gate electrode connected to the scanning line and a drain electrode connected to the signal line. A pixel transistor in which a source electrode is connected to the pixel electrode, a pixel capacitor in which liquid crystal molecules are filled between the pixel electrode and a common electrode provided in common opposite to the pixel electrode, and the pixel capacitor An auxiliary capacitor connected in parallel, and by applying the display signal voltage according to the display data, the alignment state of the liquid crystal molecules filled in the display pixel is controlled. Features.

  The invention according to claim 11 is a display panel in which a plurality of signal lines and a plurality of scanning lines are arranged so as to be orthogonal to each other, and a plurality of display pixels are two-dimensionally arranged near the intersection of the signal lines and the scanning lines. Further, in a display device drive control method for displaying desired image information based on display data, at least the step of capturing the display data and holding the display data in parallel; and Converting the display data into pixel data arranged in a time-sharing manner for each of the display data, and supplying the pixel data via connection terminals provided in common for the predetermined number of the signal lines. And the predetermined number of the signal lines in synchronization with time division timing used for converting the display data, the display signal voltage based on the pixel data. Selectively sequentially applied, characterized in that it comprises the steps of applying individually the display signal voltage to the plurality of display pixels in the row set to the selected state, the.

According to a twelfth aspect of the present invention, in the display device drive control method according to the eleventh aspect, in the step of capturing and holding the display data, the display data of a plurality of systems is fetched in parallel and held in parallel. It is characterized by doing.
The invention according to claim 13 is the drive control method for a display device according to claim 11, wherein the step of fetching and holding the display data sequentially fetches one series of the display data and holds it in parallel. To do.

  According to a fourteenth aspect of the present invention, in the display device drive control method according to any one of the eleventh to thirteenth aspects, the step of converting the display data into pixel data, and the display signal voltage of the predetermined number. The step of selectively sequentially applying to the signal line is based on a vertical control signal that defines a timing for sequentially setting the display pixels in each row to a selected state and a horizontal control signal that defines a timing for capturing and holding the display data. It is executed.

  That is, the display device and the drive control method thereof according to the present invention include a display panel in which display pixels are arranged in a matrix in the vicinity of intersections of a plurality of scanning lines and a plurality of signal lines (data lines) orthogonal to each other. In a display device comprising: a scanning drive means (gate driver) for sequentially applying scanning signals to display pixels in each row at a predetermined timing to set the display pixels in the row to a selected state; and a predetermined number of display data The signal driving means (source driver) having means for converting the display data into pixel data arranged in a time-sharing manner for each display data is interposed between the display panel and the signal driving means, and is directly connected to a plurality of signal lines. And a data distribution means (transfer switch circuit) for applying a display signal voltage based on the display data to the display pixels set in the selected state. There. Here, at least the display panel, the scanning drive unit, and the data distribution unit have a configuration in which they are integrally formed on the same insulating substrate.

  In the signal driving means, the data holding unit (latch circuit) takes in display data supplied from the outside and holds it in parallel, and the data conversion unit holds the display data (red, Green and blue color component data (parameter data) is converted into pixel data (serial data) arranged in series in a time-sharing manner, and provided in common for a predetermined number (three or two) of signal lines The data distribution means is supplied via the connected terminal. Then, in the data distribution means, the pixel provided by selectively conducting the switch provided for each signal line based on the processing timing (time division timing) used for the time division processing of the display data. Data is distributed for each signal line and supplied to each display pixel as a display signal voltage.

  As described above, according to the display device and the drive control method thereof according to the present invention, a plurality of display signal voltages supplied to the display pixels connected to the respective signal lines constituting the display panel are provided inside the signal driving means. A set of signal lines is converted into serial data (pixel data) at a predetermined time division timing and output to the data distribution means via the connection terminal corresponding to the number of sets, and each data set is serialized by the data distribution means. Since data can be supplied while being sequentially distributed to each set of signal lines according to the time division timing, data distribution means provided on the insulating substrate and signal driving means provided outside the insulating substrate Can be connected with fewer connection terminals than the number of signal lines.

  Therefore, the number of connection terminals between the display panel (pixel area) and the signal driving means can be greatly reduced, and the pitch between the connection terminals can be designed to be relatively wide, thereby reducing the number of steps in the connection process. In addition, it is possible to connect well even with relatively low connection accuracy, and it is possible to reduce the manufacturing cost and the mounting area of the peripheral circuit (driver IC).

  In the display device according to the present invention, since the display data is converted into pixel data composed of serial data in the signal driving means, the pixel data can be converted to analog and amplified to a predetermined signal level. Since the configuration of the output circuit (D / A converter, output amplifier, etc.) can be greatly reduced, the circuit scale of the signal driving means (driver IC) can be reduced and the power consumed in the output circuit can be reduced. Can be reduced.

  Furthermore, in the display device according to the present invention, at least the plurality of display pixels constituting the display panel (pixel area), the scanning drive means, and the data distribution means are integrally formed on the same insulating substrate. Since it has a configuration, pixel transistors (thin film transistors) that constitute display pixels and functional elements that constitute scan drive means and data distribution means are formed in the same manufacturing process by applying amorphous silicon, for example. can do. As a result, a display device can be manufactured at low cost by applying an amorphous silicon manufacturing process that has already been established technically, and a functional element with stable operating characteristics can be realized. Characteristics can be improved.

  In the display device according to the present invention, the signal driving means converts the display data into serial data (pixel data), and the data distribution means distributes the serial data for each signal line to display the display signal voltage. The timing for executing the processing to be supplied can be set based on the existing vertical control signal and horizontal control signal supplied to the scanning drive means and the signal drive means. Thereby, it is possible to realize a good display driving operation while reducing the number and types of control signals supplied from outside the insulating substrate and further reducing the number of connection terminals.

Hereinafter, a display device and a drive control method thereof according to the present invention will be described with reference to the drawings.
<First Embodiment>
(Liquid crystal display device)
FIG. 1 is a schematic block diagram showing an overall configuration of a display device according to the present invention, and FIG. 2 is a main part configuration diagram showing a first embodiment of a display device according to the present invention. Here, about the structure equivalent to the prior art (FIG. 13 and FIG. 14) mentioned above, description is simplified by attaching | subjecting an equivalent or the same code | symbol.

  As shown in FIGS. 1 and 2, the liquid crystal display device 100 according to the present embodiment is roughly in the vicinity of the intersection of a plurality of scanning lines SL and a plurality of data lines DL, as in the conventional technique (see FIG. 13) described above. A plurality of display pixels Px are arranged in a two-dimensional (n rows × m columns) liquid crystal display panel 110 (display panel: or a pixel area provided in a predetermined region on an insulating substrate SUB as shown in FIG. PXA), a gate driver (scanning signal means) 120 for sequentially applying a scanning signal to each scanning line SL at a predetermined timing, and a source driver (signal for applying a display signal voltage based on display data to each data line DL. Drive means) 130, and control for controlling the operating state of at least the gate driver 120, the source driver 130, and a transfer switch circuit 140 described later. LCD controller 150 that generates and outputs a signal (vertical control signal, horizontal control signal, transfer switch control signal), and display data to be supplied to source driver 130 based on the video signal, and supplies to LCD controller 150 A display signal generation circuit 160 that generates a timing signal, and a common voltage drive amplifier 170 that applies a common signal voltage Vcom having a predetermined voltage polarity to a common electrode provided in common to all the display pixels Px. Further, as a configuration unique to the present embodiment, a display signal voltage composed of serial data output from the source driver 130 is provided between the liquid crystal display panel 110 and the source driver 130. Transfer switch circuit for distributing and applying to the data line DL (data Data distribution means) 140 is provided.

In this embodiment, as shown in FIG. 2, at least a pixel area PXA in which a plurality of display pixels Px constituting the liquid crystal display panel 110 are two-dimensionally arranged, a gate driver 120, and a transfer switch circuit 140 are provided. In addition, the structure is integrally formed on an insulating substrate SUB such as a glass substrate. In this case, a pixel transistor (corresponding to the pixel transistor TFT shown in FIG. 14) constituting the display pixel Px and each functional element (thin film transistor or the like) constituting the gate driver 120 and the transfer switch circuit 140 described later are, for example, Amorphous silicon can be applied and formed by the same manufacturing process. Accordingly, a liquid crystal display device can be manufactured at a low cost by applying an already established technically established amorphous silicon manufacturing process, and a functional element with stable operating characteristics can be realized. Display characteristics can be improved.
The above-described liquid crystal display panel 110 (pixel area PXA) has the same configuration as the configuration shown in the prior art (the liquid crystal display panel 110P shown in FIG. 14), and thus detailed description thereof is omitted. .

Each configuration will be specifically described below.
FIG. 3 is a schematic configuration diagram illustrating a configuration example of a gate driver and a switch driving unit applied to the liquid crystal display device according to the present embodiment, and FIG. 4 is applied to the liquid crystal display device according to the present embodiment. It is a schematic block diagram which shows one structural example of a source driver and a transfer switch circuit. Here, description will be made with reference to the configuration shown in FIGS. 1 and 2 as appropriate.

  As shown in FIG. 3, the gate driver 120 sequentially outputs a shift signal at a predetermined timing based on a gate start signal GSRT and a gate clock signal GPCK (vertical control signal) supplied from the LCD controller 150. And a two-input AND operation circuit (hereinafter referred to as “a”) having the shift signal output from the shift register 121 as one input and the gate reset signal GRES (vertical control signal) supplied from the LCD controller 150 as the other input. 122 (abbreviated as “AND circuit”), a plurality of (two-stage) level shifters 123 and 124 and an output amplifier (amplifier) 125 for setting (boosting) the output signal from the AND circuit 122 to a predetermined signal level. It has the composition provided. Here, the level shifters 123 and 124 and the output amplifier 125 are mainly for driving the shift register 121 at a low voltage, and according to the signal level of the scanning signal applied to the scanning line SL (display pixel Px). It is appropriately provided at the output stage of the gate driver 120.

  In the gate driver 120 having such a configuration, when the gate start signal GSRT and the gate clock signal GPCK are supplied as the vertical control signals from the LCD controller 150, the gate register 120 receives the gate start signal based on the gate clock signal GPCK by the shift register 121. The shift signal is input to one input contact of a plurality of AND circuits 122 provided corresponding to each scanning line while sequentially shifting the GSRT.

  Here, in the state where the gate reset signal GRES is set to the high level (“1”) (the driving state of the gate driver), the “1” level is always input to the other input contact of the AND circuit 122. Based on the start signal GSRT and the gate clock signal GPCK, a high level (“1”) signal is output from the AND circuit 122 at the timing when the shift signal is output from the shift register 121, and the level shifters 123 and 124 and the output amplifier 125 are output. , Scanning signals G1, G2, G3,... Having a predetermined high level are generated and sequentially applied to the scanning lines SL1, SL2, SL3,. As a result, the display pixels Px connected to the scanning lines SL1, SL2, SL3,... Of each row to which the scanning signals G1, G2, G3,.

  On the other hand, when the gate reset signal GRES is set to a low level (“0”) (gate driver reset state), the “0” level is always input to the other input contact of the AND circuit 122. Regardless of whether or not a shift signal is output from the AND 122, a low level (“0”) signal is always output from the AND 122, thereby generating scanning signals G1, G2, G3,... Having a predetermined low level. Then, the display pixels Px connected to the scanning lines SL1, SL2, SL3,... Of each row are set to a non-selected state.

  In the present embodiment, as shown in FIGS. 2 and 3, a switch driver (switch drive control means) SWD that drives and controls a transfer switch circuit 140 described later is integrally formed in the gate driver 120. It has a configuration. Here, as shown in FIG. 3, the switch driver SWD has a predetermined timing based on transfer switch control signals (timing signals: multiplexer control signals CNmx0, CNmx1 and switch reset signal SDRES) supplied from the LCD controller 150. In the same manner as the AND circuit 122 described above, the decoder 126 that sequentially outputs the decode signal, and the decode signal output from the decoder 126 as one input, and the gate reset signal GRES supplied from the LCD controller 150 as the other input. An AND circuit 127, a plurality of level shifters (the same configuration as the level shifters 123 and 124 shown in the gate driver 120 described above) and an output amplifier 128 for setting the output signal from the AND circuit 127 to a predetermined signal level, The We have the example was constructed.

  In the switch drive unit SWD having such a configuration, the decode signal generated by the decoder 126 based on the multiplexer control signals CNmx0 and CNmx1 and the switch reset signal SDRES supplied as the transfer switch control signal from the LCD controller 150, The signal is input to one input contact of a plurality (three) of AND circuits 127 provided corresponding to each transfer gate (switch) of the transfer switch circuit 140 described later.

  Here, in the switch driver SWD, the LCD controller 150 in the state where the gate reset signal GRES described above is set to a high level (“1”) (the driving state of the gate driver) as shown in Table 1. When the low level (“0”) switch reset signal SDRES is supplied from the low-level (“0”) switch reset signal SDRES, the low-level (“0”) decode signal is sent to one of the AND circuits 127 regardless of the signal levels of the multiplexer control signals CNmx0 and CNmx1. By constantly inputting to the input contact, low level (“0”) switch switching signals SD1 to SD3 are supplied to the transfer switch circuit 140, and each column of display signal voltages generated by the source driver 130 described later. Is not supplied to the data line DL.

  When the high level (“1”) switch reset signal SDRES is supplied from the LCD controller 150, as shown in Table 1, the multiplexer control signals CNmx0, CNmx0, When both CNmx1 are at a low level, only the switch switching signal SD1 is at a high level, when the multiplexer control signal CNmx1 is at a high level, only the switch switching signal SD2 is at a high level, and when the multiplexer control signal CNmx0 is at a high level, When only the signal SD3 is at a high level and both the multiplexer control signals CNmx0 and CNmx1 are at a high level, the switch switching signals SD1 to SD3 are all set to a low level and are provided in common with the gate driver 120. Level The signal levels of the switch switching signals SD1 to SD3 are boosted through the shifters 123 and 124 and the output amplifier 128, and sequentially transferred to the transfer switch circuit 140 via individual signal lines so as not to overlap each other in time. Applied. As a result, the transfer gates to which the high-level switch switching signals SD1 to SD3 are applied are turned on sequentially (in time series), and the display signal voltage generated by the source driver 130 described later becomes the data line DL of each column. (Signal supply state).

  On the other hand, when the gate reset signal GRES is set to a low level (“0”) (the reset state of the gate driver 120), the “0” level is always input to the other input contact of the AND circuit 127. Regardless of the signal level of the decode signal output from 126, a low level (“0”) signal is always output from the AND circuit 127, and each transfer gate of the transfer switch circuit 140 is turned off, and data in each column The supply of the display signal voltage to the line is cut off (signal cut off state).

  As shown in FIG. 4, the source driver 130 outputs a shift register 131 that sequentially outputs a shift signal at a predetermined timing based on the horizontal shift clock signal SCK and the horizontal period start signal STH, and is output from the shift register 131. A plurality of lines of display data supplied in parallel from the display signal generation circuit 160 according to the shift signal, for example, a red component (R), a green component (G), and a blue component (B) constituting image information. A latch circuit (data holding unit) 132 that sequentially captures the three systems of display data Rdata, Gdata, and Bdata, and simultaneously outputs the display data captured in the previous horizontal period according to the control signal STB, and a multiplexer control signal CNmx0 , CNmx1, and the display data Rdata, Gdata, 3-input multiplexer (data conversion unit) 133A for converting data (that is, parallel data) into a single system of serial data (pixel data) arranged in a time division manner, and pixel data output from the 3-input multiplexer 133A A digital-analog converter (hereinafter abbreviated as “D / A converter”) 134 that converts (R, G, B) into an analog signal having a predetermined signal polarity based on the polarity control signal POL. Based on the output enable signal OE, the analog-converted pixel data (R, G, B) is amplified to a predetermined signal level, and is sent to the transfer switch circuit 140 via the connection terminal TMs as the display signal voltage Vrgb. And an output amplifier 135 for outputting. Here, the horizontal shift clock signal SCK, the horizontal period start signal STH, the control signal STB, the multiplexer control signals CNmx0 and CNmx1, the polarity control signal POL, and the output enable signal OE supplied to each of the above-described components are all LCD controller 150. This is a horizontal control signal supplied from.

  Also, as shown in FIG. 4, the transfer switch circuit 140 is connected in parallel to the connection terminal TMs from which the display signal voltage Vrgb configured in a time-sharing manner is output from the source driver 130 described above. A structure including transfer gates (switches) TG1 to TG3 for each of the data lines DL1 to DL3, DL4 to DL6,. And control to selectively set the ON states of the transfer gates TG1 to TG3 by the switch switching signals SD1 to SD3 that are individually generated and supplied by the switch driver SWD provided in the gate driver 120 described above. Is done.

  In the source driver 130 and the transfer switch circuit 140 having such a configuration, display data Rdata, Gdata, and Bdata corresponding to each row of RGB display pixels Px for one row are supplied in parallel and sequentially from the display signal generation circuit 160. The display data Rdata, Gdata, and Bdata corresponding to each set of RGB display pixels are sequentially fetched and held by the latch circuit, and then converted into time-division serial data by the 3-input multiplexer 133A. 134 and the output amplifier 135 to the transfer switch circuit 140 via the single connection terminal TMs.

  At this time, the switch switching signals SD1 to SD3 generated based on the multiplexer control signals CNmx0 and CNmx1 for controlling the serial conversion processing in the three-input multiplexer 133A from the switch driver SWD provided in the data driver 120 In synchronization with the time division timing of the display signal voltage Vrgb composed of time division serial data, the transfer gates TG1 to TG3 provided on the data lines DL1 to DL3, DL4 to DL6,. Is selectively turned on.

  Thereby, the display signal voltage Vr based on the red component Rdata of the display data among the time division serial data is supplied to the data lines DL1, DL4, DL7,... DL (k + 1), and the display based on the green component Gdata is performed. The signal voltage Vg is supplied to the data lines DL2, DL5, DL8,... DL (k + 2), and the display signal voltage Vb based on the blue component Bdata is supplied to the data lines DL3, DL6, DL9,. Supplied to 3). Here, k representing the column number of the data line DL is k = 0, 1, 2, 3,.

  For example, the display signal generation circuit 160 extracts a horizontal synchronization signal, a vertical synchronization signal, and a composite synchronization signal from a video signal (composite video signal or the like) supplied from the outside of the liquid crystal display device 100, and sends it to the LCD controller 150 as a timing signal. And supplying predetermined display signal generation processing (pedestal clamp, chroma processing, etc.) to extract R, G, B color luminance signals (display data) included in the video signal, and then analog or digital signals. To the source driver 130.

  The LCD controller 150 generates a horizontal control signal and a vertical control signal based on various timing signals such as a horizontal synchronization signal, a vertical synchronization signal, and a system clock supplied from the display signal generation circuit 160, and each of them generates a gate driver. In addition to being supplied to 120 and the source driver 130, as a function unique to the present embodiment, a transfer switch control signal for controlling the operation state of the transfer switch circuit 140 is generated, and the switch driver SWD and the source driver 130 of the gate driver 120 are generated. The transfer gates TG1 to TG3 provided in the transfer switch circuit 140 are selectively turned on in synchronization with the supply timing of the display signal voltage Vrgb consisting of time-division serial data from the source driver 130, Display signal above Controls to distribute voltage Vrgb to the data lines (display pixels).

(Drive control method for liquid crystal display device)
Next, a drive control operation in the liquid crystal display device according to the present embodiment will be described with reference to the drawings.
FIG. 5 is a timing chart showing the drive control operation of the liquid crystal display device according to the present embodiment.

  As shown in the timing chart of FIG. 5, the drive control operation in the liquid crystal display device having the above-described configuration is performed as one scan period SLi (1) from the gate driver 120 with one horizontal period (1H) as one cycle. ≦ i ≦ n), the display pixel Px group in the row is set to a selected state by applying the scanning signal Gi, and three data lines are respectively supplied via the source driver 130 and the transfer switch circuit 140 during the selection period. DL1 to DL3, DL4 to DL6,... As a set, and at the application timing of switch switching signals SD1 to SD3 (conduction timing of transfer gates TG1 to TG3), each data line DL1 to DL3, DL4 to DL6,. The display signal voltage Vrgb corresponding to the display data corresponding to the display pixel Px connected to is distributed, and individual display signals Pressure Vr, Vg, by sequentially applied as Vb, executes an operation of writing display data to each display pixel Px in the row.

  Then, such a writing operation is performed in one vertical period (1V = (n + 1) × H) in each of the scanning lines SL1, SL2,... SLn constituting the liquid crystal display panel 110 (in this embodiment, the liquid crystal display panel). 110 includes 320 scanning lines SL. N = 320), by sequentially applying scanning signals G1, G2, G3,... Gn, display data for one screen of the liquid crystal display panel. Is written in each display pixel Px. Thereby, each display pixel Px is set to a gradation state corresponding to the display data, so that desired image information is displayed on the liquid crystal display panel 110.

  Therefore, according to the liquid crystal display device and the drive control method thereof according to the present embodiment, the display signal voltage supplied to the display pixels Px connected to the data lines DL constituting the liquid crystal display panel 110 (pixel area PXA) is Within the source driver 130, a plurality of data lines DL are converted into time-division serial data as a set, and output to the transfer switch circuit 140 integrally formed with the pixel area PXA on the insulating substrate SUB. The switch circuit 140 distributes each set of time-division serial data according to the time-sharing timing and sequentially supplies each set to the data line DL, thereby transferring the transfer switch circuit 140 provided on the insulating substrate SUB; Between the insulating substrate 140 and the source driver 130 provided separately, the above It can connect by a set number of the connection terminals TMs of Tarain DL.

  As a result, the number of connection terminals between the liquid crystal display panel 110 and the source driver 130 is reduced to a fraction (a fraction of the number of data lines included in each set), and the pitch between the connection terminals is relatively reduced. Since it can be designed widely, the number of man-hours in the connection process can be reduced, and a good connection can be achieved even with relatively low connection accuracy, reducing the manufacturing cost and the source driver mounting area. Can be achieved.

  Further, in the configuration in which the display signal voltage is supplied in parallel corresponding to each data line arranged in the liquid crystal display panel as shown in the prior art, display data (pixel data) supplied as a digital signal. It is necessary to provide a D / A converter for converting the analog data, an output amplifier for amplifying the analog pixel data to a predetermined signal level for each data line. Since the configuration can be reduced to a fraction, the circuit scale of the source driver can be reduced, and the power consumed by the output stage (D / A converter, output amplifier, etc.) can be reduced. .

  In this embodiment, a switch driver SWD that generates switch switching signals SD1 to SD3 for controlling the conduction states of the transfer gates TG1 to TG3 provided in the transfer switch circuit 140 is provided in the gate driver 120. However, the present invention is not limited to this, and a configuration provided outside the gate driver 120 may be applied. Here, as described above, the switch drive unit has the same configuration as the AND circuit, level shifter, and output amplifier provided in the gate driver, and based on the gate reset signal GRES that controls the operation state of the gate driver. Therefore, as shown in the present embodiment (FIG. 3), it is possible to reduce the circuit scale and the number of connection terminals by applying the configuration integrally formed with the gate driver. Have.

  In the present embodiment, the data is supplied as parallel data of a plurality of systems (j is an arbitrary positive integer; 3 systems (j = 3) when corresponding to each RGB color component as described above). The display data is converted into serial data by the 3-input multiplexer 133A and output from the source driver 130. In the transfer switch circuit 140 attached to the liquid crystal display panel 110 (pixel area PXA), the transfer gates TG1 to TG3 are connected to the time. Since it is configured to distribute to a plurality (j) of data lines DL by performing an ON operation based on the division timing, the display data is simply captured and held, converted into a display signal voltage, and output. Compared to a conventional source driver, the source driver 130 and the transfer switch circuit 140 are j It is set to perform signal processing at a speed of operation (j times the clock frequency).

<Second Embodiment>
Next, a second embodiment of the display device according to the present invention will be described with reference to the drawings.
FIG. 6 is a schematic configuration diagram illustrating a configuration example of a gate driver and a switch driving unit applied to the liquid crystal display device according to the second embodiment, and FIG. 7 is applied to the liquid crystal display device according to the present embodiment. It is a schematic block diagram which shows the example of 1 structure of the source driver and transfer switch circuit. FIG. 8 is a timing chart showing the drive control operation of the liquid crystal display device according to this embodiment. Further, FIG. 9 is a schematic configuration diagram showing another configuration example of the source driver and transfer switch circuit applied to the liquid crystal display device according to the present embodiment. Here, about the structure equivalent to 1st Embodiment mentioned above, the same or equivalent code | symbol is attached | subjected and the description is simplified or abbreviate | omitted.

  The liquid crystal display device according to this embodiment generally has a configuration equivalent to that of the first embodiment described above (see FIGS. 1 and 2). In particular, the gate driver 120, the source driver 130, and the transfer switch circuit 140 are included. As shown below, the display data supplied in parallel corresponding to the two display pixels Px connected to the two data lines DL as a set is converted into time-division serial data. After being converted and output to the transfer switch circuit 140, the data is distributed to each set of data lines at time division timing.

  That is, as shown in FIG. 6, the gate driver 120 applied to the liquid crystal display device according to the present embodiment has a configuration in which the switch driver SWD is provided inside, as in the first embodiment described above. The switch driver SWD receives a decode signal output from the decoder 126 based on the multiplexer control signal CNmx and the switch reset signal SDRES supplied from the LCD controller 150, and a gate supplied from the LCD controller 150 to the gate driver 120. Based on a signal output from the AND circuit 127 that receives the reset signal GRES, two types (two systems) of switch switching signals SD1 and SD2 to be supplied to the transfer switch circuit 140 are generated. . Here, the gate driver 120 (a configuration excluding the switch driving unit SWD) according to the present embodiment has the same configuration as that of the gate driver described in the first embodiment, and a description thereof will be omitted. .

  In the switch driver SWD having such a configuration, in the state where the gate reset signal GRES described above is set to a high level (“1”) (the driving state of the gate driver 120), the signal logic shown in Table 2 is obtained. When the low level (“0”) switch reset signal SDRES is supplied from the LCD controller 150, the transfer switch circuit 140 has a low level (“0”) switch regardless of the signal level of the multiplexer control signal CNmx. The switching signals SD1 and SD2 are supplied, and the supply of the display signal voltage generated by the source driver 130, which will be described later, to the data lines DL in each column is cut off.

  When the high level (“1”) switch reset signal SDRES is supplied from the LCD controller 150, the multiplexer control signal CNmx is set to the low level based on the signal level of the multiplexer control signal CNmx as shown in Table 2. At this time, only the switch switching signal SD1 is set to the high level, and when the multiplexer control signal CNmx is at the high level, only the switch switching signal SD2 is set to the high level. Accordingly, the transfer gates to which the switch switching signals SD1 and SD2 are applied are turned on sequentially (in time series), and the display signal voltage generated by the source driver 130 described later is supplied to the data line DL of each column. The

  On the other hand, when the gate reset signal GRES is set to a low level (“0”) (the reset state of the gate driver 120), the “0” level is always input to the other input contact of the AND circuit 127. Regardless of the signal level of the decode signal output from 126 (that is, the signal level of the multiplexer control signal CNmx and the switch reset signal SDRES), the transfer switch circuit 140 has a low level (“0”) switch switching signal SD1, SD2. Is supplied, and the supply of the display signal voltage generated by the source driver 130 to be described later to the data lines DL in each column is cut off.

  As shown in FIG. 7, the source driver 130 includes a shift register circuit 131, a latch circuit 132, a D / A converter 134, and an output amplifier 135, similarly to the configuration shown in the first embodiment. Further, as a configuration unique to the present embodiment, two systems of display data (Rdata and Gdata, Bdata and Rdata) among a plurality of systems (three systems) of display data Rdata, Gdata, and Bdata that are sequentially fetched and held in the latch circuit 132. Or parallel data of any combination of Gdata and Bdata) having a two-input multiplexer 133B that converts serial data (pixel data) arranged in a time-division manner into one system.

  As shown in FIG. 7, the transfer switch circuit 140 is connected in parallel to the connection terminal TMs from which the display signal voltages Vrg, Vbr, and Vgb are output as time-division serial data from the source driver 130 described above. Of the above-described three systems of display data, each of the data lines DL connected to the display pixels corresponding to each of the two systems of display data has a configuration provided with transfer gates TG1 and TG2. Control is performed to selectively set the on states of the transfer gates TG1 and TG2 by the switch switching signals SD1 and SD2 individually supplied from the switch driver SWD provided in the gate driver 120.

  In the source driver 130 and the transfer switch circuit 140 having such a configuration, as in the first embodiment described above, three lines corresponding to display pixels of each color of RGB for one row from the display signal generation circuit 160 are provided. The display data Rdata, Gdata, and Bdata are sequentially supplied as parallel data, and are sequentially captured and held by the plurality of latch circuits 132 in accordance with the shift signal output from the shift register 131, and the captured display data is transferred to the control signal STB. Output from the LCD controller 150 for every two systems of display data (Rdata and Gdata, Bdata and Rdata, or Gdata and Bdata) corresponding to the adjacent display pixels Px in the pixel area PXA. Based on a single multiplexer control signal CNmx, Mux 133B D / A converter 134 converts the divided serial data when the output amplifiers 135, via the connection terminal TMs, is output to the transfer switch circuit 140 as the display signal voltage Vrgb.

  At this time, the pixel data (display) is displayed by the switch switching signals SD1 and SD2 generated based on the multiplexer control signal CNmx for controlling the serial conversion processing in the multiplexer 133B from the switch driver SWD provided in the data driver 120. The transfer gates TG1 and TG2 provided in the data lines DL1, DL3,..., DL2, DL4. To turn on.

  As a result, a display composed of time-division serial data at a predetermined timing when the switch switching signal SD1 or SD2 is supplied (that is, time-division timing of display data Rdata, Gdata, and Bdata converted based on the multiplexer control signal CNmx). Of the signal voltage Vrg, the display signal voltage Vr based on the red component Rdata of the display data is supplied to the data lines DL1, DL4, DL7,... DL (k + 1), and the display signal voltage Vg based on the green component Gdata is obtained. Supplied to the data lines DL2, DL5, DL8,... DL (k + 2) and the display signal voltage Vb based on the blue component Bdata is supplied to the data lines DL3, DL6, DL9,. Is done.

  Then, the drive control operation in the liquid crystal display device according to the present embodiment is performed from the gate driver 120 to the scanning line SLi (1) with one horizontal period (1H) as one cycle, as in the case of the first embodiment described above. 1 ≦ i ≦ n) to apply the scanning signal Gi to set the display pixel Px in the row to the selected state, and as shown in the timing chart of FIG. 8, the source driver 130 and the transfer switch circuit in the selected period Display data corresponding to each display pixel Px at the application timing of switch switching signals SD1 and SD2 (conduction timing of transfer gates TG1 and TG2) with two data lines DL adjacent to each other as a set via 140. By sequentially applying display signal voltages Vr, Vg, and Vb corresponding to each of the display pixels, a predetermined table is applied to each display pixel Px in the row. To perform the operation of writing the data.

  Such a writing operation is sequentially performed on the scanning lines SL1, SL2,... SLn (in this embodiment, n = 320) constituting the liquid crystal display panel 110, and the scanning signals G1, G2, G3,. By applying Gn, display data for one screen of the liquid crystal display panel is written to each display pixel Px. Thereby, each display pixel Px is set to a gradation state corresponding to the display data, so that desired image information is displayed on the liquid crystal display panel 110.

  In the present embodiment, display data (three systems of display data) Rdata, Gdata, and Bdata of each color of RGB supplied in parallel (as parallel data) from the display signal generation circuit 160 are converted into the shift register 131. Although the configuration in which the touch circuit 132 captures and holds the signal collectively based on the output timing of the shift signal from is described, the present invention is not limited to this. For example, as shown in FIG. Display data Rdata, Gdata, and Bdata of RGB color components supplied in a time division manner (as serial data) from the signal generation circuit 160 to individual latch circuits (LCT) 132 based on the output timing of the shift signal. Sequential capture and hold, and a two-input multiplexer 133B in the subsequent stage (or a three-input multi-channel as shown in the first embodiment) Configuration may have a which is adapted to convert the divided serial data when the Lexus 133A).

<Third Embodiment>
Next, a third embodiment of the display device according to the present invention will be described with reference to the drawings.
FIG. 10 is a main part configuration diagram illustrating a liquid crystal display device according to the third embodiment, and FIG. 11 is a schematic configuration diagram illustrating an example of a control signal generation unit applied to the liquid crystal display device according to the present embodiment. It is. FIG. 12 is a timing chart showing a signal generation operation in the control signal generation unit according to this embodiment. Here, about the structure equivalent to 1st or 2nd embodiment mentioned above, the same or equivalent code | symbol is attached | subjected and the description is simplified or abbreviate | omitted.

  The liquid crystal display device according to this embodiment generally has a configuration equivalent to that of the first embodiment described above (see FIGS. 1 and 2), and in particular, a multiplexer and transfer switch circuit 140 provided in the source driver 130. Multiplexer control signals CNmx0, CNmx1 and switch reset signal SDRES for controlling the operation state are generated based on existing vertical control signals and horizontal control signals supplied to the gate driver 120 and the source driver 130. .

  That is, as shown in FIG. 10, the main configuration of the liquid crystal display device according to the present embodiment is a plurality of components arranged in the liquid crystal display panel 110 (pixel area PXA) as in the first embodiment described above. A gate driver 120 that sequentially applies scanning signals to the scanning lines SL, a source driver 130 that simultaneously applies display signal voltages based on display data to a plurality of data lines DL, a source driver 130, and a liquid crystal display panel 110, the transfer switch circuit 140 directly connected to the plurality of data lines DL, and the switch switching signals SD1 to SD3 provided in the gate driver 120 and controlling the operation state of the transfer switch circuit 140 are generated. And a switch drive unit SWD that performs the following. Based on the vertical control signal and the horizontal control signal supplied from the CD controller 150, the switch drive signals SW1 to SD3 are generated in the switch driver SWD, and the display data is serially converted in the source driver 130. A control signal generation unit (control signal generation means) CSG for generating multiplexer control signals CNmx0 and CNmx1 and a switch reset signal SDRES is provided, and the transfer switch circuit 140 is integrally provided in the source driver 130. ing.

  Here, in the present embodiment, at least each component shown in FIG. 10 (the liquid crystal display panel 110 (pixel area PXA), the gate driver 120, the source driver 130, and the control signal generation unit CSG) is on the same insulating substrate SUB. Are integrally formed. The gate driver 120 (configuration including the switch driver SWD) and the source driver 130 (configuration including the transfer switch circuit 140) according to the present embodiment are the same as those in the first embodiment (FIGS. 3 and 4). Therefore, the detailed description thereof is omitted.

  As shown in FIG. 11, the control signal generation unit CSG applied to this embodiment is generally an existing vertical control signal (gate start signal GSRT, gate clock signal GPCK) supplied from the LCD controller 150 to the gate driver 120. Based on a vertical counter 141 that counts the number of clocks of the gate clock signal GPCK and an existing horizontal control signal (horizontal period start signal STH, horizontal shift clock signal SCK) supplied from the LCD controller 150 to the source driver 130. The horizontal counter 142 that counts the horizontal shift clock signal SCK, and the multiplexer supplied to the switch driver SWD and the transfer switch circuit 140 based on the count values from the counters 141 and 142 and the horizontal shift clock signal SCK. It has a decoder 143 for generating a service control signals CNmx0, CNmx1 and switches the reset signal SDRES, a configuration with a.

  Thereby, as shown in FIG. 12A, the vertical counter 141 takes one vertical period (1V = 321H) as one cycle, and the count value G-count of the gate clock signal GPCK counted within the one vertical period. As shown in FIG. 12 (b), the horizontal counter 142 takes one horizontal period (1H = 240SCK) as one cycle, and the horizontal counter 142 counts the horizontal shift clock signal SCK counted within the one horizontal period. The count value S-count is output to the decoder 143. Here, in FIG. 12, similarly to the above-described embodiment, the liquid crystal display panel 110 includes 320 scanning lines SL and 240 data lines (that is, a case where the number of pixels is 320 × 240 in width). ) Is a timing chart. Also, the decoder 143 generates multiplexer control signals CNmx0 and CNmx1 and a switch reset signal SDRES having predetermined timings as shown in FIG. 5 based on the count values G-count and S-count.

  In the present embodiment, the case where the source driver 130 is provided with a configuration including a three-input multiplexer (see FIG. 4) as shown in the first embodiment has been described. However, the present invention is not limited thereto. However, the present invention is not limited, and as shown in the second embodiment, a configuration including a three-input multiplexer (see FIG. 7) may be applied. In this case, a single multiplexer control signal CNmx and a switch reset signal SDRES having a predetermined timing as shown in FIG. 8 are generated by the control signal generation unit CSG and supplied to the switch driver SWD and the source driver 130. Is done.

  Therefore, in the liquid crystal display device having such a configuration, the liquid crystal display panel 110 (pixel area PXA) is formed using only the existing vertical control signal and horizontal control signal supplied to the gate driver 120 and the source driver 130. The multiplexer control signals CNmx0 and CNmx1 and the switch reset signal SDRES are generated in the insulated substrate SUB, and the switch driver SWD provided in the gate driver 120 and the transfer switch circuit provided in the source driver 130 140, the number of control signals supplied from outside the insulating substrate SUB can be reduced to further reduce the number of connection terminals, and a display drive operation equivalent to the configuration in the prior art can be realized.

  In addition to the gate driver (including the switch driver SWD) 120, the source driver (including the transfer switch circuit 140) 130 is also integrated on the insulating substrate SUB on which the pixel area PXA constituting the liquid crystal display panel 110 is formed. As a result, the mounting area of peripheral circuits (especially driver ICs) can be greatly reduced, and the manufacturing process can be simplified by reducing the number of terminals as described above. Product cost can be reduced.

It is a schematic block diagram which shows the whole structure of the display apparatus which concerns on this invention. It is a principal part block diagram which shows 1st Embodiment of the display apparatus which concerns on this invention. It is a schematic block diagram which shows one structural example of the gate driver applied to the liquid crystal display device which concerns on this embodiment, and a switch drive part. It is a schematic block diagram which shows the example of 1 structure of the source driver applied to the liquid crystal display device which concerns on this embodiment, and a transfer switch circuit. 4 is a timing chart illustrating a drive control operation of the liquid crystal display device according to the present embodiment. It is a schematic block diagram which shows the example of 1 structure of the gate driver applied to the liquid crystal display device which concerns on 2nd Embodiment, and a switch drive part. It is a schematic block diagram which shows the example of 1 structure of the source driver applied to the liquid crystal display device which concerns on this embodiment, and a transfer switch circuit. 4 is a timing chart illustrating a drive braking operation of the liquid crystal display device according to the present embodiment. It is a schematic block diagram which shows the other example of a structure of the source driver applied to the liquid crystal display device which concerns on this embodiment, and a transfer switch circuit. It is a principal part block diagram which shows the liquid crystal display device which concerns on 3rd Embodiment. It is a schematic block diagram which shows an example of the control signal generation part applied to the liquid crystal display device which concerns on this embodiment. It is a timing chart which shows signal generation operation in the control signal generation part concerning this embodiment. It is a block diagram which shows schematic structure of the liquid crystal display device provided with the thin film transistor (TFT) type display pixel in a prior art. It is an equivalent circuit diagram which shows an example of the principal part structure of the liquid crystal display panel in a prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Liquid crystal display device 110 Liquid crystal display panel 120 Gate driver 130 Source driver 140 Transfer switch circuit 150 LCD controller SWD Switch drive part CSG Control signal generation part

Claims (14)

A display panel in which a plurality of signal lines and a plurality of scanning lines are arranged so as to be orthogonal to each other, and a plurality of display pixels are arranged two-dimensionally in the vicinity of the intersection of the signal lines and the scanning lines, is desired. In a display device that displays image information,
at least,
Scan driving means for sequentially applying scanning signals to the scanning lines of each row at a predetermined timing to set the display pixels of the row to a selected state;
A data holding unit that takes in the display data supplied from outside and holds the display data in parallel, and the display data held in parallel in the data holding unit is divided in a time-sharing manner for each predetermined number of display data. A data conversion unit that converts the pixel data arranged in the pixel data,
The signal driving means is interposed between the display panel and the signal driving means, directly connected to the plurality of signal lines, and connected in common to the predetermined number of the signal lines. A plurality of switches for sequentially applying the display signal voltage based on the pixel data supplied from the plurality of the signal lines to the plurality of display pixels in the row set in the selected state. Data distribution means for individually applying display signal voltages based on display data;
A display device comprising: The display device according to claim 1, wherein the data holding unit takes in the display data of a plurality of systems in parallel and holds them in parallel. The display device according to claim 1, wherein the data holding unit sequentially takes in the display data of one system and holds them in parallel. The plurality of switches are individually provided for each of the signal lines, and are selectively set to a conductive state in synchronization with a time division timing used for conversion of the display data in the data conversion unit. The display device according to claim 1. The display device further includes switch drive control means for generating a switch switching signal for controlling the conduction state of the plurality of switches in the data distribution means based on a predetermined timing signal. The display device according to claim 1. The display device according to claim 5, wherein the switch drive control unit is configured integrally with the scan drive unit. The display device further includes control signal generation means for generating the timing signal based on a vertical control signal supplied to the scanning drive means and a horizontal control signal supplied to the signal drive means. The display device according to claim 5 or 6. 8. The display device according to claim 1, wherein the data distribution unit is configured integrally with the signal driving unit. The display device according to claim 1, wherein at least the display panel, the scanning drive unit, and the data distribution unit are integrally formed on a single insulating substrate. . Each of the plurality of display pixels includes a pixel transistor having a gate electrode connected to the scan line, a drain electrode connected to the signal line, and a source electrode connected to the pixel electrode, and the pixel electrode and the pixel electrode. A pixel capacitor formed by filling liquid crystal molecules between common electrodes that are commonly provided opposite to each other, and an auxiliary capacitor connected in parallel to the pixel capacitor,
10. The display according to claim 1, wherein an orientation state of the liquid crystal molecules filled in the display pixel is controlled by applying the display signal voltage corresponding to the display data. apparatus. A display panel in which a plurality of signal lines and a plurality of scanning lines are arranged so as to be orthogonal to each other, and a plurality of display pixels are arranged two-dimensionally in the vicinity of the intersection of the signal lines and the scanning lines, is desired. In a drive control method for a display device that displays image information,
at least,
Capturing the display data and holding it in parallel;
Converting the display data held in parallel into pixel data arranged in a time-sharing manner for each predetermined number of the display data;
Supplying the pixel data via a connection terminal provided in common for the predetermined number of the signal lines;
The display signal voltage based on the pixel data is selectively applied sequentially to the predetermined number of the signal lines in synchronization with the time division timing used for the conversion of the display data, and the row of the row set in the selected state is selected. Individually applying the display signal voltages to the plurality of display pixels;
A drive control method for a display device, comprising: The display device drive control method according to claim 11, wherein the step of capturing and holding the display data includes capturing the display data of a plurality of systems in a lump in parallel and holding the display data in parallel. 12. The drive control method for a display device according to claim 11, wherein the step of capturing and holding the display data sequentially fetches and holds the display data of one system in parallel. The step of converting the display data into pixel data and the step of selectively applying the display signal voltage to the predetermined number of the signal lines sequentially set the timing for sequentially setting the display pixels in each row to the selected state. The display device drive control method according to claim 11, wherein the display device drive control method is executed based on a vertical control signal to be defined and a horizontal control signal to define a timing for capturing and holding the display data.

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