JPH05241536A - Horizontal scanning circuit - Google Patents

Abstract

PURPOSE:To make a driving pulse line in non-overlap which is outputted successively from a horizontal scanning circuit incorporated in an active matrix type liquid crystal display device, etc. CONSTITUTION:The active matrix type liquid crystal display device is constituted of a display part 1, a vertical scanning part 2 and a horizontal scanning part 3. The horizontal scanning part 3 is provided with a shift register S/R generating successively a horizontal shift pulse signal PHI. The shift pulse Dn of an Nth stage generated from the shift register and a delayed pulse DDn+1 delaying the shift pulse Dn+1 of a (N+1)th stage by a delay element DLYn are processed by an AND element AND. and the horizontal switch driving pulse PHIn of the Nth stage is generated. A transmission gate element S is conducted corresponding to each driving pulse PHI and a video signal is sampled.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a horizontal scanning circuit incorporated in a two-dimensional addressing device such as an active matrix type liquid crystal display device. More specifically, the present invention relates to a circuit configuration for making the horizontal switch drive pulses sequentially output from the horizontal scanning circuit non-overlapping.

[0002]

2. Description of the Related Art To clarify the background of the present invention, a conventional horizontal scanning circuit will be briefly described with reference to FIG. 4 by taking an active matrix type liquid crystal display device as an example. As shown in the figure, the active matrix type liquid crystal display device has a plurality of gate lines X ₁ , X ₂ , ... Arranged in parallel with the X-axis direction.
And a plurality of data lines Y ₁ arranged in parallel to the Y-axis direction,
Y ₂ , ... And. Active elements such as thin film transistors (TFTs) T ₁₁ , T ₁₂ , T ₂₁ , and T ₂₁ ,
T ₂₂ , ... Are formed. Further, liquid crystal cells L ₁₁ , L ₁₂ , L ₂₁ , L ₂₂ , ... Are provided corresponding to the respective TFTs. Each liquid crystal cell is composed of a liquid crystal layer sandwiched between a common electrode COM and individual pixel electrodes. The gate electrode of each TFT is connected to the corresponding gate line, the source electrode is connected to the corresponding data line, and the drain electrode is connected to the pixel electrode of the corresponding liquid crystal cell.

The gate line group is connected to a vertical scanning circuit (not shown) and outputs a gate signal line-sequentially to provide TFTs for each row.
Select. On the other hand, the data line groups Y ₁ , Y ₂ , ... Are connected to the common signal line SIG via the corresponding switching transistors S ₁ , S ₂ ,. The gate electrode of each switching transistor is connected to the horizontal scanning circuit. The horizontal scanning circuit operates in synchronization with a clock signal HCK supplied from the outside, and sequentially outputs horizontal switch driving pulses Φ ₁ , Φ ₂ ,. The switching transistor groups S ₁ , S ₂ , ... Sequentially conduct in response to the corresponding horizontal switch driving pulse, sample the video signal supplied from the outside through the signal line SIG, and corresponding data lines Y ₁ , Y ₂ , Distribute to. The TFT selected for each row sequentially takes in the sampled video signal through the corresponding data line, and transfers and writes it to the liquid crystal cell. In this way, dot-sequential driving of the active matrix type liquid crystal display device is performed.

[0004]

Next, the problem of the prior art to be solved by the present invention will be briefly described with reference to FIG. The horizontal scanning circuit shown in FIG. 4 is composed of a shift register and the like, and the horizontal switch drive pulse Φ ₁ ,
Φ ₂ , ... Is output. Each drive pulse has a pulse width corresponding to the video signal sampling time, that is, the data transfer time, assigned to one data line. Since the shift register is a kind of logic circuit, the horizontal scanning circuit configured by the shift register is set so that the subsequent drive pulse rises when the previous drive pulse falls. However, the devices included in each stage constituting the shift register have variations in electrical characteristics, and jitter occurs in each pulse. Depending on the amount of jitter, the leading pulse and the trailing pulse may overlap each other. Since this jitter is caused by variations in device parameters in each stage of the shift register, there is a fixed tendency for each stage.

If the overlap amount is large, the signal line SIG
Potential fluctuation occurs in the. For example, as shown in the figure, when the leading pulse Φ ₁ contains a considerable amount of jitter, the subsequent pulse rises before the leading pulse falls. In other words, the sampling by the subsequent pulse is performed before the sampling of the video signal by the preceding pulse is completed. Therefore, when the impedance of the signal line SIG is high or when the output impedance of the video driver connected to the signal line is high, the above-mentioned potential fluctuation occurs due to the influence of the overlapping sampling. Since this potential fluctuation occurs during the output period of the advance pulse Φ ₁ , the potential fluctuation is sampled on the corresponding data line Y ₁ , and an error occurs from the original video signal data amount. Since this error tends to be fixed corresponding to each data line, there is a problem that so-called vertical stripes occur in the display image and cause deterioration in image quality.

[0006]

SUMMARY OF THE INVENTION In view of the above-mentioned problems or problems of the prior art, it is an object of the present invention to make the horizontal switch drive pulses output from the horizontal scanning circuit non-overlapped. The following measures have been taken in order to achieve this object. That is, in the horizontal scanning circuit including the shift register that sequentially generates the horizontal shift pulse signal from the output section, the delay pulse generated by delaying the shift pulse of the Nth stage and the shift pulse of the (N + 1) th stage generated from this shift register It is characterized in that a means for generating a horizontal switch drive pulse of the Nth stage is provided.

The horizontal scanning circuit having such a configuration is generally incorporated in a two-dimensional addressing device. This two-dimensional address device includes a plurality of gate lines arranged in parallel in the X-axis direction, a plurality of data lines arranged in parallel in the Y-axis direction, and a first signal for sequentially supplying a gate signal to the gate lines. A scanning unit or a vertical scanning unit, a second scanning unit or a horizontal scanning unit for sequentially supplying a data signal to the data line, and a data signal from the data line when selected by a gate signal supplied from the gate line. It is composed of active elements provided at the intersections of the gate lines and the data lines for capturing. In this two-dimensional address device, the horizontal scanning unit sequentially outputs a horizontal shift pulse signal from an output unit to a shift register, an N-th shift pulse and a (N + 1) -th shift pulse generated from the shift register. It is composed of a means for generating a horizontal switch drive pulse of the Nth stage by the delayed delay pulse and a switch means for sampling a data signal on the data line in response to the horizontal switch drive pulse.

An active matrix type liquid crystal display device is an example of a two-dimensional address device having such a configuration.
This liquid crystal display device includes a plurality of pixel electrodes arranged in a matrix, an active element connected to the pixel electrode, a gate line connected to a first electrode of the active element, and a first electrode of the active element. It is composed of one substrate having a data line connected to the two electrodes, the other substrate opposed to the one substrate, and a liquid crystal layer sandwiched between the two substrates. The liquid crystal display device having such a configuration is provided with a horizontal scanning circuit that generates a horizontal switch drive pulse at the Nth stage by a delay pulse obtained by delaying the shift pulse at the Nth stage and the shift pulse at the (N + 1) th stage. The sampling time of the video signal supplied to the data line is non-overlap so that the Nth stage and the (N + 1) th stage do not overlap.

[0009]

In the present invention, the N-th stage horizontal switch drive pulse is generated by ANDing the N-th stage shift pulse generated from the shift register and the (N + 1) -th stage shift pulse delayed with each other, for example. I am trying to generate it. According to this delay amount, an interval is provided between the first drive pulse and the second drive pulse, so that the drive pulse train is output without overlapping. When the horizontal scanning circuit having such a configuration is applied to an active matrix type liquid crystal display device of dot-sequential driving, the potential fluctuation of the video signal line can be prevented, so that the fixed vertical stripe pattern of the display image, which has been a problem in the past, is prevented. Can be removed.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a circuit diagram showing an example of an active matrix type liquid crystal display device including a horizontal scanning circuit or a horizontal scanning unit to which the present invention is applied. The horizontal scanning circuit according to the present invention can be widely applied not only to a display device but also to a general two-dimensional address device.

As shown, the present liquid crystal display device has a display unit 1.
And a vertical scanning unit 2 and a horizontal scanning unit 3.
To facilitate understanding, the display unit 1 will be described first. display
Part 1 is a plurality of gate lines arranged parallel to the X-axis direction
X₁, X₂,, and a plurality of elements arranged in parallel to the Y-axis direction.
Data line Y_n, Y_{n + 1}, Y_{n + 2}, And have. Na
For convenience, the data line is Y_nShows only 3 from
However, the data line is actually Y₁It started from. Ge
The data line group and the data line group intersect each other in a matrix.
And active elements are provided at the respective intersections.
In this example, each active element is a thin film transistor (TFT)
T_{1, n}, T_{1, n + 1}, T_{1, n + 2}, T_{2, n}, T_{2, n + 1}, T
_{2, n + 2},,. Liquid crystal corresponding to each TFT
Cell L_{1, n}, L_{1, n + 1}, L_{1, n + 2}, L_{2, n}, L_{2, n + 1}，
L_{2, n + 2}, ... are arranged. Each liquid crystal cell is an individual screen
It is composed of a liquid crystal layer sandwiched between a unit electrode and a common electrode.
Has been. The gate electrode of each TFT is connected to the corresponding gate line.
Connected and the source electrode is connected to the corresponding data line
The drain electrode is connected to the corresponding pixel electrode.
Has been. Gate line group X₁, X₂, ... on the vertical scanning unit 2
It is connected and outputs the gate signal in line sequence.
Then, the TFT is selected for each row. On the other hand, data line group Y_n，
Y_{n + 1}, Y_{n + 2}, ... are connected to the horizontal scanning unit 3,
A sequentially sampled video signal is supplied. Selected
The TFT captures the video signal from the corresponding data line
The image is displayed by transferring it to the corresponding liquid crystal cell. Like this
Then, the dot-sequential drive of the active matrix liquid crystal display device
Movement is performed. In addition, gate line group, data line group, TF
The T group and the pixel electrode group are formed on one substrate,
The through electrode is formed on the other substrate. These pairs of groups
The plates are placed facing each other with a predetermined gap, and within the gap between both substrates.
Active matrix liquid crystal display with liquid crystal layer filled in
Configure the device.

Next, the horizontal scanning section 3 which is a main part of the present invention will be described. The horizontal scanning unit 3 includes a shift register S / R. This shift register is formed by connecting D-type flip-flops (D-FF) in multiple stages. To simplify the illustration, N corresponding to the data lines Y _n , Y _{n + 1} , Y _{n + 2}
Only the stages, (N + 1) stages, and (N + 2) stages are shown. Each of these stages sequentially outputs shift pulses D _n , D _{n + 1} and D _{n + 2} . Hereinafter, similar suffixes will be used when indicating corresponding stage numbers for various pulse signals and components. However, the suffix is not used unless it is necessary to specify the column number.

A two-input AND element is connected to each stage output terminal of the shift register S / R. The shift pulse of the stage is supplied to one input terminal of the AND element. The shift pulse from the next stage is supplied to the other input terminal via the delay element DLY. In this example, the delay element is composed of two inverters connected in series.

A corresponding transmission gate element S is connected to the output terminal of each AND element, and the horizontal switch drive pulse Φ and its inversion pulse are applied to the pair of gate terminals. For example, the AND _n of the Nth stage performs the AND process of the delay pulse DD _{n + 1} obtained by delaying the shift pulse D _n of the stage and the shift pulse D _{n + 1} of the next stage, and the horizontal switch of the stage. The drive pulse Φ _n is output.
The input terminal of each transmission gate element is connected to the common signal line SIG, and the output terminal is connected to the corresponding data line. Each transmission gate element sequentially samples a data signal, that is, a video signal from the signal line SIG and transfers it to the corresponding data line in response to the horizontal switch driving pulse Φ. That is, these transmission gate element groups form horizontal switch means.

Next, the operation of the horizontal scanning section 3 shown in FIG. 1 will be described in detail with reference to the timing chart of FIG. The shift pulse D _n-1 from the previous stage is input to the N-th stage of the shift register S / R. Each stage of the shift register is driven by the horizontal clock pulse HCK1 and its inversion pulse HCK2. In this example, the width of the shift pulse is set to one cycle of the clock pulse signal. The N-th stage D-FF is provided with a pair of inverters, and shifts the shift pulse D _n-1 from the previous stage by a half cycle of the clock and inverts it to generate a pulse A _n . This pulse A _n is inverted by the output inverter and then the shift pulse D
Output as _n . As is clear by comparing the shift pulses D _n-1 and D _n , D _n is a pulse obtained by shifting D _n-1 by a half cycle of the clock. In this way, the shift register S / R sequentially shifts the pulses D _n , D _{n + 1} , D _{n + 2} ,
D _{n + 3} , ... Is output.

For example, the shift pulse D _n output from the Nth stage is supplied to one input terminal of AND _n . Further, the shift pulse D _{n + 1} introduced from the (N + 1) th stage is delayed by the corresponding delay element DLY _n and delayed pulse DD
It is applied to the other input terminal of AND _n as _{n + 1} . In the timing chart of FIG. 2, the delay amount between the shift pulse D _{n + 1} and the delay pulse DD _{n + 1} is shown as Delay.

The AND _n performs an AND process between the shift pulse D _n and the delay pulse DD _{n + 1} of the stage and outputs a horizontal switch drive pulse Φ _n . Similarly, AND _{n + 1} outputs the next horizontal switch drive pulse Φ _{n + 1} . As is clear from comparison between Φ _n and Φ _{n + 1} , there is an interval between the two, which corresponds to the delay amount Delay. In this way, the horizontal switch drive pulse train is non-overlapped. By sequentially driving the transmission gate element group with these pulse trains, it is possible to remove the fixed vertical stripe pattern of the display image, which has been a problem in the past.

When the jitter contained in the clock pulse HCK supplied from the outside exceeds the delay amount set by the delay element, it is necessary to further increase the delay amount. This adjustment can be dealt with, for example, by increasing the number of inverters included in the delay element.

FIG. 3 shows a modification of the delay element, and illustrates the N-th stage delay element DLY _n . When the delay amount is adjusted to be increased, if the number of inverters is used, the pattern area will increase accordingly. Therefore, in the modification shown in FIG. 3, a desired delay amount is obtained by adjusting the input resistance R of each inverter.

[0020]

As described above, according to the present invention, the N-th stage shift pulse generated from the shift register and the (N
Since the N-th stage horizontal switch drive pulse is generated by the delay pulse obtained by delaying the +1) -th stage shift pulse,
The drive pulse train can be non-overlapped. By sampling the video signal with this drive pulse train, the fixed vertical stripe pattern of the display screen can be removed, and the image quality can be improved. Further, by adjusting the delay amount, it is possible to deal with the jitter included in the clock pulse signal supplied from the outside. The present invention has an effect that the circuit configuration is simple because no special external pulse is required for non-overlap.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an example of an active matrix type liquid crystal display device including a horizontal scanning circuit according to the present invention.

FIG. 2 is a timing chart for explaining the operation of the horizontal scanning unit shown in FIG.

FIG. 3 is a circuit diagram showing a modified example of a delay element included in a horizontal scanning unit.

FIG. 4 is a circuit diagram showing an example of a conventional horizontal scanning circuit.

FIG. 5 is a timing chart for explaining a problem of the conventional horizontal scanning circuit.

[Explanation of symbols]

 1 display part 2 vertical scanning part 3 horizontal scanning part S / R shift register DLY delay element AND AND element S transmission gate (switch means) X gate line Y data line SIG signal line T thin film transistor L liquid crystal cell

Claims (3)

[Claims] 1. A shift register for sequentially generating a horizontal shift pulse signal from an output section, an N-th shift pulse generated from this shift register, and a delay pulse delayed from the (N + 1) -th shift pulse And a means for generating a horizontal switch driving pulse of the horizontal scanning circuit. 2. A first scanning unit that sequentially supplies gate signals to the gate lines, a plurality of gate lines arranged in parallel with the X-axis direction, a plurality of data lines arranged in parallel with the Y-axis direction. And a second signal for sequentially supplying a data signal to the data line
And a two-dimensional address having an active element provided at each intersection of the gate line and the data line for fetching a data signal from the data line when selected by a gate signal supplied from the gate line. In the apparatus, the second scanning unit delays a shift register that sequentially generates a horizontal shift pulse signal from an output unit, an N-th stage shift pulse and a (N + 1) -th stage shift pulse that are generated from this shift register. It is comprised of a means for generating a horizontal switch drive pulse of the Nth stage by a delay pulse and a switch means for respectively sampling a data signal on the data line in response to the horizontal switch drive pulse. Dimensional address device. 3. A plurality of pixel electrodes arranged in a matrix, an active element connected to the pixel electrode, a gate line connected to a first electrode of the active element, and a second line of the active element. A liquid crystal display device comprising: one substrate having a data line connected to the electrode of the other substrate; the other substrate opposed to the one substrate; and a liquid crystal layer sandwiched between the two substrates. A circuit for generating a horizontal switch drive pulse for the Nth stage by a delay pulse obtained by delaying the shift pulse for the stage and the shift pulse for the (N + 1) th stage is provided, and the sampling time of the video signal supplied to the data line is N. Step and (N + 1)
A liquid crystal display device characterized in that it does not overlap at the step.