JP3436255B2 - Horizontal scanning circuit device with fixed overlapping pattern removal function - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [0001] [0001] The present invention relates to a matrix arrangement.
Formed at the intersection of the gate line and the data line
Active elements such as thin-film transistors and corresponding pixel electrodes
Active matrix type liquid crystal display device composed of
About. More specifically, video signals are line-sequentially
The present invention relates to a horizontal scanning circuit for distributing and supplying signals to an input terminal. [0002] BACKGROUND OF THE INVENTION To facilitate understanding of the present invention,
FIG. 8 shows an active matrix type liquid crystal display device.
A general equivalent circuit is shown. As shown, this type of liquid crystal display
The display device has a plurality of gate lines arranged in parallel in the X-axis direction.
Or gate line X₁, X_Two, ..., parallel to the Y-axis direction
Data lines or data lines arranged in
Y₁, Y_Two, ... Each gate line and data line
At the intersection with the active element, for example, a thin film transistor (TF
T) T₁₁, T₁₂, T_{twenty one}, T_{twenty two}, ... are formed. or
Correspondingly, the liquid crystal cell L₁₁, L₁₂, L_{twenty one}, L_{twenty two}, ... also formed
Have been. The gate electrode of each TFT is connected to the gate line.
And the source electrode is connected to the data line,
The rain electrode is connected to the pixel electrode of the corresponding liquid crystal cell.
I have. Each liquid crystal cell has a pixel electrode and an opposing common electrode.
Composed of a liquid crystal sandwiched by through electrodes COM.
You. Each data line Y₁, Y_Two, ... correspond respectively
Switching transistor S₁, S _TwoCommon through…
Is connected to the signal line SIG. To this signal line SIG
Is supplied with a video signal from the outside. Each switching tiger
A horizontal scanning circuit is connected to the gate electrode of the transistor.
You. This horizontal scanning circuit uses a horizontal clock input from the outside.
Horizontal switch driving pulse in synchronization with the clock signal HCLK
Φ₁, Φ_Two, ... are the gate voltages of the switching transistors
Apply to pole. On the other hand, the gate line X₁, X_Two, ... are shown
Not connected to a vertical scanning circuit. Next, the operation of the circuit shown in FIG. 8 will be briefly described.
I do. When a vertical scanning circuit (not shown) is driven, the gate line
The TFTs are excited line-sequentially and a TFT is selected for each row. At this time,
Drives horizontal scanning circuit and switches transistors in line order
When operated next, the video signal supplied to the signal line SIG
Are sequentially sampled on each data line. sampling
Video signals are sequentially passed through the TFTs selected for each row.
The data is written to the corresponding liquid crystal cell. In this way, the video
Signal sampling data is applied to individual liquid crystal cells in dot-sequential
It will be written. [0005] Next, referring to FIG.
The problem to be solved by the invention will be briefly described. In FIG.
The horizontal scanning circuit shown comprises a shift register and the like.
And horizontal switch drive pulse Φ₁, Φ_Two,… Output
I do. Considering the logical level, the starting pulse Φ₁When
Late pulse Φ_TwoIt is designed not to overlap with.
However, in fact, the rise and fall of the pulse
Jitter occurs due to dripping, etc.
May occur. That is, adjacent pulses interfere with each other.
You. The amount of this jitter is
It depends on the electrical characteristics of each device and is unique.
You. Therefore, the overlapping pattern between pulse trains is fixed.
Therefore, a particular amount of jig is always in a particular stage of the shift register.
Tta tend to appear. As described above, the starting pulse Φ₁In response to
Corresponding switching transistor S₁Are conductive and common
Data line Y corresponding to video signal from signal line SIG₁Nisa
Sampled. Next, the subsequent pulse Φ_TwoIn response to
Corresponding switching transistor S_TwoAnd the common signal
Data line Y corresponding to the video signal from signal line SIG_TwoTo sun
Is pulled. At this time, if there is jitter, the starting pulse Φ
₁Pulse Φ before falling_TwoStand up
The potential of the signal line SIG is changed by the charging / discharging current during that time.
Shaking occurs. This potential fluctuation is caused by the fall of the first pulse.
Data line Y₁Is sampled to
As a result, the data line Y₁Sampling data
Error occurs. This error depends on the amount of jitter
So that jitter always appears at a particular stage
Will be. This is a so-called vertical streak when viewed as a whole screen
There is a problem that image quality is significantly impaired.
Generally, a video driver that outputs a video signal to a signal line SIG is provided.
Output impedance is high and signal line impedance is high.
High dance, the jitter of the horizontal switch drive pulse
Strongly affected by vertical streaks or fixed overlapping patterns
Notable. Furthermore, the clock frequency of the horizontal scanning circuit
In order to reduce power consumption, so-called RGB simultaneous drive is performed.
The vertical streak defect is reduced because the apparent number of pixel columns decreases.
There is a problem that the layer becomes noticeable. In view of the above-mentioned problems of the conventional technology, the present invention
Akira is built into an active matrix liquid crystal display
The fixed scanning pattern removal function is added to the horizontal scanning circuit to
The purpose is to improve longitudinal streak defects. [0008] SUMMARY OF THE INVENTION The above-mentioned prior art sections are described.
Was taken to solve the problem and to achieve the object of the present invention.
The means are as follows. That is,Supply video signalBoth
Signal lines and a plurality of sets of switches connected to the signal lines
Transistor andloadConsisting ofSwitching
The transistor has an input terminal connected to the signal line and a load.
It has an output terminal to connect and a gate terminal.Horizontal scanning times
Circuit device, corresponding to the switching transistor
A shift register for sequentially supplying a primary pulse, and
Between the switching transistor and the shift register.
Logic gate to shape primary pulse into secondary pulse
With steps andThe shift register sequentially outputs a primary pulse.
Nth output stage and Mth output stage (N <
M), wherein said logic gate means comprises:
A plurality of shift registers are provided corresponding to a plurality of output stages of the shift register.
Each logic gate means has two input terminals and one
An output terminal, and the Nth logic gate means includes
Nth output from the Nth output terminal of the register
Shape the next pulse into the Nth secondary pulse and the Mth logic
The gate means has one input terminal connected to M of the shift register.
And the other input terminal is connected to the N-th output terminal.
Connect to the output terminal of the logic gate means, and
Connected to the gate terminal of the Mth switching transistor
Followed by the MthThe logic gate meansNth logic gate
Nth output from the meansSecondary pulse and the shift register
StarMth output stage ofSupplied byMthPrimary pal
And its inputsNthThe secondary pulse falls
After standing upM-thOutput secondary pulse
And the M-th switching transistor is the M-th switching transistor.
The next pulse is received by the gate terminal and turned on.
Sampling the video signal supplied from theTo do
It is characterized by. According to the present invention, the horizontal scanning circuit device has a primary scanning circuit.
Output stage of shift register for sequentially generating pulse signals
Connected to a logic gate means for outputting a secondary pulse.
You. This logic gate means generates the Nth stage
Accept the secondary pulse as a control signal and
M stage having a rising edge in phase with the falling edge of the pulse
It controls the output timing of the secondary pulse of the second eye.
In other words, during the output of the first pulse, the output of the second pulse
Is prohibited, and after the first pulse falls,
To get up. As a result, the shift register
Advance sampling corresponding to the Nth stage and Mth stage
Since the subsequent sampling will not always overlap,
Longitudinal streaks or fixed overlapping patterns can be removed. In this invention
In order to control the output timing of the subsequent pulse,
The starting pulse is used. Therefore, they have particularly complex configurations.
No additional circuit or clock source is required. [0010] BRIEF DESCRIPTION OF THE DRAWINGS FIG.
Examples will be described in detail. FIG. 1 activates the invention
Schematic showing an example applied to a matrix type liquid crystal display device
FIG. In addition, the present invention relates to such a two-dimensional
Not only display devices, but also generally two-dimensional address devices
It is applicable to. As shown in the figure, the apparatus is parallel to the X-axis direction.
Gate lines X arranged in₁, X_Two, ..., Y axis direction
Data lines Y arranged in parallel in the direction_n, Y_{n + 1}, Y
_{n + 2},... In addition, these gate lines
A first scanning unit or a vertical scanning unit that supplies gate signals line-sequential
A video signal is supplied line-sequentially to the scanning unit and these data lines.
A second scanning unit or a horizontal scanning unit. At each intersection of the gate line group and the data line group, a husband
Each active element such as a thin film transistor (TFT) T_{1, n},
T_{1, n + 1}, T_{1, n + 2}, T_{2, n}, T_{2, n + 1}, T_{2, n + 2}Is set
Have been killed. Each TFT has a corresponding liquid crystal cell L
_{1, n}, L_{1, n + 1}, L_{1, n + 2}, L _{2, n}, L_{2, n + 1}, L
_{2, n + 2}, ... are connected. Each liquid crystal cell has a pixel
Electrode, common electrode facing, and liquid sandwiched between both electrodes
And a crystal layer. The drain electrode of each TFT is
Connected to the pixel electrode, and the gate electrode is
The source electrode is connected to the corresponding data line
It is connected to the. Each TFT is supplied from a gate line
Selected for each row by gate signal and from data line
The supplied video signal is accessed dot-sequentially and the corresponding liquid
Write to crystal cell. Although not shown, they are arranged in a matrix.
A plurality of pixel electrodes, a TFT group, a gate line group,
The data line group, the vertical scanning unit, and the horizontal scanning unit
It is formed on a plate using a semiconductor process. Also,
The through electrodes are formed on the other substrate. Both boards are
By sandwiching the superposed liquid crystal layer through a gap,
The active matrix type liquid crystal display device can be obtained. With continued reference to FIG.
The circuit configuration of the horizontal scanning unit will be described in detail. Horizontal scan
The unit includes a shift register S / R. This shift
The registers are D-type flip-flops (D-FF) connected in multiple stages
Nth or N + 2nd for simplicity
Only the cut is shown. Each stage of shift register
A NAND element is connected to the force section. In particular, shift
Reference symbol NAN when indicating the correspondence with each stage of the register
We will add a suffix to D. For example, the N-th stage
The NAND element connected to the input terminal is NAND_nIn table
I forgot. Hereinafter, other types of elements and signal pulses
Indicates the correspondence with the shift register stage by the same rule.
If necessary, use a suffix.
A horizontal switch drive pulse B is sequentially output from each NAND element.
Is output. This pulse contains jitter and has a fixed weight.
Since the double pattern has not been removed, it is hereinafter referred to as primary pulse B.
I do. A NOR element is provided at the output terminal of the NAND element.
It is connected. This NOR element group is a logic gate means.
As a fixed pattern removal circuit. Each NOR element
Is connected to a delay element DLY. this
The delay element group forms a delay circuit. Output terminal of delay circuit
The child has been de-jittered and subjected to predetermined delay processing.
A horizontal switch drive pulse Φ is output. Below
The processed pulse is referred to as a secondary pulse Φ. actually
Means that the output of the delay element DLY is the secondary pulse Φ and its inverted pulse.
Ruth. A transmitter is connected to a pair of output terminals of the delay element.
The connection gate element S is connected. These tran
The group of the transmission gate elements constitutes the switch means.
The input terminal of each transmission gate element is a video signal
And is commonly connected to the signal line SIG that supplies
The output terminal is connected to the corresponding data line Y.
Only when the secondary pulse Φ is applied
The conduction gate element becomes conductive, and the video signal sequentially corresponds to the corresponding data.
Is transferred to the data line Y. The individual NOs constituting the fixed pattern removing circuit
One of the input terminals of the R element has the primary pulse B as described above.
And a second pulse is applied to the other input terminal.
Φ is input. This NOR element is a secondary pulse Φ
Is accepted as a control signal, and the rising
Late primary pulse with rising edge in phase with falling edge
B is to control the output timing. In this example
Of the next stage based on the secondary pulse Φ corresponding to the previous stage.
The rising timing of the primary pulse B
You. For example, NOR corresponding to the Nth stage_nIs Φ_n-1Based on
B_nIs gate controlled. The individual delay elements D constituting the delay circuit
LY is, in this example, from an inverter connected in series.
Become. By setting the number of connected inverters appropriately,
The desired amount of delay is obtained. The NOR element also has a predetermined delay.
Rolling occurs. Therefore, the delay amount of the entire circuit is NOR.
This is the sum of the element and the delay element DLY. Next, referring to FIGS. 2 and 3, the water shown in FIG.
The operation of the flat scanning unit will be described in detail. First, the tie in Figure 2
Primary by shift register S / R based on Mining chart
The output of the pulse B will be described. Shift register S /
The data pulse D from the previous stage is applied to the N-th D-FF of R._n-1
Is transferred. Each stage of the shift register is horizontal
Clock signal HCK1 and its inverted signal HCK2 are supplied
Have been. In this example, the width of the data pulse D is
It is set for one cycle of the lock signal. Shift register
Data pulse D from the previous stage input to the Nth stage_n-1Ha
Is delayed by a half cycle of the clock by the inverter pair and
Are inverted. The waveform of the pulse that has undergone this processing is denoted by A_nWhen
Shown. This pulse A_nBy another inverter
And the data pulse D of the Nth stage_nIs obtained. Thailand
As is clear from the timing chart, the data pulse D_nIs
Data pulse D at the previous stage_n-1Half cycle of the clock compared to
Is only shifting. Thus, the shift register S / R
Is the data pulse shifted by half the clock cycle
D_n, D_{n + 1}, D_{n + 2}, ... are sequentially output. The output terminal of each stage of the shift register is NAN.
The D element is connected. For example, connected to the Nth stage
NAND_nIs the data pulse D of this stage_nAnd next data
Pulse D_{n + 1}Primary pulse B with NAND processing_nTo
Output. Similarly, it is connected to the (N + 1) th stage output terminal.
NAND_{n + 1}Is the next primary pulse B_{n + 1}Is output. this
Thus, the sequentially output primary pulse B is half of the clock.
It has a width equivalent to the period, and its pulse width
One shift. In other words, the primary pulse at the previous stage is output.
Immediately after the input, the primary pulse of the next stage is output. logic
Primary pulses output sequentially at different levels do not overlap
However, in practice, dripping occurs at the rising and falling edges of the pulse.
Because of this, jitter occurs and sometimes overlaps each other. Next, refer to the timing chart of FIG.
Next, the operation of generating the secondary pulse Φ will be described. Nth stage
NAND_nHas a fixed pattern removal circuit as described above.
NOR to be formed_nIs connected. This NOR_nIs N-stage
Primary pulse B of the eye_nAnd the secondary pulse Φ at the previous stage_n-1Noah with
Processing is performed and pulse C_nIs output. The timing of Fig. 3
As is clear from the chart, this pulse C_nIs the former
Secondary pulse Φ_n-1Rises in synchronization with the fall of.
Therefore, the primary pulse B of the N-th stage_nContains jitter
Even the corresponding pulse C_nRemoves this jitter
You. This pulse C_nIs the delay element DLY_nVia a predetermined quantity
Is delayed by the final secondary pulse Φ_nIs output. This
The fixed pattern elimination circuit controls the secondary pulse
Accept as control signal and fall of this advanced secondary pulse
Outgoing secondary pulse with rising in phase with beam
Control the force timing and remove fixed overlapping patterns. this
Secondary pulse Φ sequentially processed and subjected to similar processing_n-1,
Φ_n, Φ_{n + 1}, ... are conventional problems because they do not overlap each other
The vertical streak defect of the display image which has been described can be removed. FIG. 4 shows a modification of the circuit shown in FIG.
In order to facilitate understanding, especially the N-th stage of the horizontal scanning unit
Only the cut is shown. Same as the components shown in FIG.
Parts are given the same reference numerals. different
The point is that the fixed pattern removal circuit uses the inverter I and the NAND element.
It is composed of a combination with a child. Take
The fixed pattern removing circuit having the configuration shown in FIG.
Elimination circuit (NOR_n). Referring to FIG. 5, horizontal scanning according to the present invention
Another embodiment of the unit will be described. Figure for ease of understanding
The same components as those in the horizontal scanning unit shown in FIG.
Reference numerals are attached. Differences from the embodiment shown in FIG.
Is connected to each stage output terminal of the shift register S / R.
That is, the removed NAND element has been removed. Follow
In this example, the output from each stage of the shift register is
Data pulse D is directly input to the corresponding NOR element.
ing. In connection with this, other input terminals of each NOR element
Is not the secondary pulse Φ from the previous stage, but the secondary
The pulse Φ is input as a control signal. Next, the horizontal scanning shown in FIG. 5 with reference to FIG.
The operation of the circuit will be described. As mentioned earlier, shift registers
S / R has a width corresponding to one cycle of the clock signal HCK.
The data pulses D are sequentially output directly. Each data path
Are shifted by half a cycle of the clock signal.
You. In this example, the data pulses are divided into two groups
It is. One group is an even-numbered data pulse D_n,
D_{n + 2}, D_{n + 4}, ..., the other group is odd
Data pulse D_{n + 1}, D_{n + 3}, D_{n + 5}, ... included
You. Data pulse of even-numbered group and odd-numbered group
Data pulses are supplied from different signal lines.
Used to sample the signal. Same group
There is a possibility that pulse interference may occur due to jitter in
You. For this reason, in this embodiment, the secondary pulse of the immediately preceding stage is not used.
The secondary pulse of the current stage is used as the control signal
Regulates the pulse rise timing. Like this
In addition, the present invention generally employs a preceding pulse as a control signal as a pulse.
Output timing of certain late pulses with potential interference
The specific late pulse is shown in FIG.
It is not limited to the next pulse as described above. As described above, the pulse generation timing
The situation in which the power is controlled appears, for example, in the case shown in FIG.
You. In this example, the data transferred in the shift register
The width of the pulse D is set long, and the clock signal HC
This corresponds to two cycles of K. Even in this case, the shift
The registers are shifted from each other by half the period of the clock signal.
Data pulse D_n, D_{n + 1}, D_{n + 2}, D_{n + 3},
D_{n + 4}, D_{n + 5}, ... are sequentially output. Timing of FIG.
As can be seen from the chart, pulse interference or bit
Interference occurs every third stage. For example, the starting data pulse D
_nFalling timing and subsequent data pulse D_{n + 4}of
Since the rise timing is in phase,
Bit interference may occur. Therefore, in this case
The horizontal switch drive pulse four steps before is used as a control signal.
The timing of the horizontal switch drive pulse
It will be. [0025] As described above, according to the present invention, water
By providing a fixed pattern removal circuit in the flat scanning circuit,
This has the effect that vertical streak defects in the displayed image can be removed.
You. In addition, the fixed pattern removal circuit uses the first pulse
The circuit configuration is controlled by controlling the pulse output timing.
It is relatively simple and the electrical characteristics of each device
The structure is strong against variations. Such fixed
Horizontal scanning circuit with overlap pattern removal function is especially RGB simultaneous
Active matrix type liquid crystal display device adopting drive system
When applied to a device, a remarkable effect can be achieved.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing an example of an active matrix liquid crystal display device to which a horizontal scanning circuit according to the present invention is applied. FIG. 2 is a timing chart for explaining the operation of the horizontal scanning circuit shown in FIG. FIG. 3 is a timing chart for explaining the operation of the horizontal scanning circuit. FIG. 4 is a circuit diagram showing a modification of the fixed pattern removal circuit included in the horizontal scanning circuit shown in FIG. FIG. 5 is a circuit diagram showing another embodiment of the horizontal scanning circuit. 6 is a timing chart for explaining the operation of the horizontal scanning circuit shown in FIG. FIG. 7 is a timing chart for explaining an operation of a modification of the horizontal scanning circuit shown in FIG. FIG. 8 is a circuit diagram showing a conventional active matrix type liquid crystal display device. 9 is a timing chart for explaining the problem of the conventional example shown in FIG. [Description of Signs] S / R shift register NOR NOR gate element (fixed pattern removal circuit) DLY delay element S transmission gate element (switch means) T thin film transistor (active element) L liquid crystal cell

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-4-28097 (JP, A) JP-A-61-212113 (JP, A) JP-A-61-94300 (JP, A) JP-A-62 214783 (JP, A) JP-A-62-135812 (JP, A) JP-A-64-73391 (JP, A) JP-A-5-166393 (JP, A) JP-A-4-179996 (JP, A) JP-A-5-119741 (JP, A) JP-A-5-165427 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G09G 3/00-3/38 G02F 1/133 505-580 G11C 19/00

Claims (1)

(57) Patent Claims 1. A common signal line for supplying a video signal, Ri and a plurality of sets of switching transistors and a load connected to the signal line, the switching transistor
An input terminal connected to the signal line and an output terminal connected to the load
And children, a horizontal scanning circuit device Ru and a gate terminal, and sequentially shift register for supplying a primary pulse in response to the switching transistor, interposed by primary pulses between said switching transistor and said shift register To a secondary pulse, and the shift register sequentially outputs a primary pulse.
A plurality including the Nth output stage and the Mth output stage (N <M)
Comprising the output stage, said logic gate means includes a plurality of output stages of the shift register
Are provided in correspondence with each other.
N input terminals and one output terminal, and the Nth logic gate means is the Nth logic gate means of the shift register.
Nth primary pulse output from the output terminal
And the M-th logic gate means that one input terminal is
Connect to the Mth output terminal of the register and the other input terminal
Is connected to the output terminal of the Nth logic gate means,
The terminal of the Mth switching transistor corresponding to the terminal
The Mth logic gate means is connected to the Nth logic gate means.
Nth secondary pulse output from the
And M-th primary pulse supplied from the M-th output stage as its input, after the fall of the N-th secondary pulses, and outputs the M-th secondary pulses as rising, M-th switching transistors Is the Mth secondary
Received by the gate terminal, conducts, and is supplied from the signal line.
A horizontal scanning circuit device , wherein a supplied video signal is sampled to the load .