JP3551600B2 - Horizontal scanning circuit and liquid crystal display - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a horizontal scanning circuit for selectively supplying a video signal to a signal line of a matrix type liquid crystal display device, and a liquid crystal display device including such a horizontal scanning circuit.
[0002]
[Prior art]
An active matrix type liquid crystal display device can realize a high contrast ratio and high image quality even in a liquid crystal display device having a small duty ratio, that is, a multi-line liquid crystal display device by incorporating a switching transistor in a liquid crystal display panel. Also, an active matrix liquid crystal display device with a built-in driver (hereinafter, abbreviated as a liquid crystal display device with a built-in driver) in which a horizontal scanning circuit and a vertical scanning circuit are built on the same substrate as the liquid crystal display device is extremely compact while having high image quality. It has a configuration and is put into practical use as a light valve for a computer-compatible projector.
[0003]
FIG. 6 is an equivalent circuit diagram of the liquid crystal display device with a built-in driver. In the figure, reference numeral 1 denotes an input terminal to which a video signal is supplied. The signal from the input terminal 1 is vertically (Y-axis) through signal line selection switches S ₁ , S ₂ ,... , And Xm are supplied to the signal lines X ₁ , X ₂ ,. Note that m is a number corresponding to the number of pixels in the horizontal (X-axis) direction. Further, an m-stage horizontal scanning circuit 2 is provided, a horizontal shift clock CLX and shift data DX are supplied to the horizontal scanning circuit 2, and a signal line selection switch driving pulse SX from each output terminal of the horizontal scanning circuit 2 is provided. _{1, SX} 2, ···, SXm said signal line select switches _{S 1, S 2, ···,} is supplied to the control terminals of the Sm. Also, the signal lines _{X 1, X 2, ···,} the switching element _T 11 consisting TFT respectively _{Xm, T 21, ···, Tm} 1, T 12, T 22, ···, Tn 2, ··・ One end of Tnm is connected. Note that n is a number corresponding to the number of horizontal scanning lines. The other ends of the switching elements T ₁₁ ,..., Tnm are commonly connected to the counter electrode 3 via the liquid crystal cells C ₁₁ ,.
[0004]
Further, an n-stage vertical scanning circuit 4 is provided, a vertical shift clock CLY and shift data DY are supplied to the vertical scanning circuit 4, and gate drive pulses SY ₁ , SY ₂ ,. · ·, SYn each row in the X-axis direction of the switching element _{(T 11, ···, T 1} m), (T 21, ···, T 2 m), ···, (Tn 1, ·· ., Tnm).
[0005]
As a result, the video signal from the writing terminal 1 is selectively applied to the liquid crystal cells C ₁₁ ,..., Cnm to obtain a pixel display.
[0006]
FIG. 7 is an equivalent circuit diagram of a conventional horizontal scanning circuit. 5 is a shift register in FIG mainly clocked inverter circuit _{C I1, CI 2, ···,} CIm +1 and _{CIF 1, CIF 2, ···,} CIFm +1 inverter circuit _{I 1, I} 2, · · , Im _{+ 1} . The shift register 5 transfers the shift data DX according to the horizontal shift clock CLX and its inverted clock CLX. NAND circuit according to transferred data input the second output adjacent _{(NAND 1, NAND 2, ···} , NANDm) and the inverter circuit _{INV 1, INV 2, ···,} the signal line selection switch driving through INVm The pulses are output as pulses SX ₁ , SX ₂ ,..., SXm.
[0007]
FIG. 8 is an operation timing chart of the conventional horizontal scanning circuit of FIG. In the figure, I ₁ , I ₂ , INV ₁ , and INV ₂ indicate outputs of the inverter circuits I ₁ , I ₂ , INV ₁ , and INV ₂ , respectively. The video signal is an input video signal to the input terminal 1 and is obtained by sampling a video signal from a computer or the like with a sampling clock SCLK and passing through a hold circuit and a buffer circuit.
[0008]
[Problems to be solved by the invention]
However, in the related art, since the time during which the video signal changes is included in the selection period of the signal line after or before the corresponding signal line, a ghost appears on the display screen of the liquid crystal display device. Was. In FIG. 8, since the time during which the video signal changes is included in the selection period of the (next) signal line after the corresponding signal line, the shift direction of the video signal on the display screen is from left to right. Then, a ghost will occur on the right side of the image.
[0013]
[Means for Solving the Problems]
SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems in the prior art, and according to the invention described in claim 1, a horizontal scanning switchable in either a forward or reverse scanning direction by setting a control terminal. A first delay circuit that inputs a first signal that is an output of an N-th stage of the shift register in the horizontal scanning circuit and outputs a second signal obtained by delaying the first signal; A first control circuit that inputs the first signal and the second signal and outputs a third signal that starts at a start timing of the second signal and ends at an end timing of the first signal; A second delay circuit that inputs a fourth signal from the first signal, which is an output from the subsequent stage of the N-th stage of the shift register, and outputs a fifth signal obtained by delaying the fourth signal And the fourth signal and the fifth signal A second control circuit for outputting a sixth signal that starts at the start timing of the fifth signal and ends at the end timing of the fourth signal; the third signal and the sixth signal And a third control circuit for outputting a pulse starting at the start timing of the sixth signal and ending at the end timing of the third signal.
[0014]
According to the first aspect of the present invention, the horizontal scanning circuit capable of scanning in both forward and reverse directions by setting a control terminal includes the above-described circuit group, so that the horizontal scanning circuit can perform scanning in both forward and reverse directions. Only the start timing of the signal line selection switch drive pulse can be delayed. As a result, the period during which the signal line selection switch drive pulse is output can be made discontinuous, and ghost on the display screen can be prevented.
[0015]
According to the second aspect of the present invention, the delay circuit includes one or more stages of inverter circuits.
[0016]
According to the third aspect of the present invention, the delay circuit includes one or more resistance elements and one or more capacitance elements.
[0017]
According to the fourth aspect of the present invention, the delay circuit includes one or more stages of inverter circuits, one or more resistance elements, and one or more capacitance elements.
[0018]
According to the second, third, and fourth aspects of the present invention, the delay circuit can be constituted by relatively simple and small-scale circuit elements, and the output period of the signal line selection switch driving panel can be discontinuous. Ghosts can be prevented.
[0019]
According to the invention described in claim 5, the matrix display device is an active matrix type liquid crystal display device, and the signal line selection switch, the horizontal scanning circuit, the delay circuit, and the control circuit are the active matrix type liquid crystal display device. It is formed on one of the transparent substrates of the liquid crystal display device.
[0021]
Since the liquid crystal display device according to the sixth aspect includes the horizontal scanning circuit as described above, a clear image without ghost can be realized.
[0022]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the present invention will be described with reference to the drawings.
[0023]
[Example 1]
FIG. 1 is an equivalent circuit diagram showing an example of the horizontal scanning circuit according to the first aspect of the present invention.
[0024]
First, the configuration is invented. The shift register 5 is clocked inverter circuit _{CI 1, CI 2, ···,} CIm +1 (m is the number of pixels in the horizontal direction) and _{CIF 1, CIF 2, ···,} CIFm +1 and the inverter circuit _I 1, _{I 2} ,..., Im _{+ 1} . The shift register 5 transfers the shift data DX according to the horizontal shift clock CLX and its inverted clock CLX. NAND circuits transferred data is a control circuit which receives the second output adjacent the shift register _{5 (NAND 1, NAND 2,} ···, NANDm) and the inverter circuit INVA _{1, INV} 2, ···, The signal line selection switch drive pulses SX ₁ , SX ₂ ,..., SXm are output via INVm. Here, a delay circuit 6 indicated by Delay is inserted between the output of the subsequent stage of the two adjacent outputs of the shift register 5 and the input of the NAND circuit serving as the control circuit. Delays the output of the NAND circuit as the control circuit and the start timing of the signal line selection switch drive pulse in order to delay the output of the subsequent stage.
[0025]
FIG. 2 is a timing chart for explaining the operation of the horizontal scanning circuit shown in FIG. 1 for explaining this relationship. In the figure, I ₁ , I ₂ , INV ₁ , and INV ₂ indicate outputs of the inverter circuits I ₁ , I ₂ , INV ₁ , and INV ₂ , respectively. The video signal is an input video signal to the input terminal 1 and is obtained by sampling a video signal from a computer or the like with a sampling clock SCLK and passing through a hold circuit and a buffer circuit. As can be seen from the figure, the output start timing of INV ₁ and INV _{2, that is} , the output start timing of the signal line selection switch drive pulses SX ₁ and SX ₂ is delayed, and INV ₁ and INV ₂ (SX ₁ and SX ₂ ) are delayed. A pause period occurs between output periods. By allocating this pause period to the time during which the video signal is changing, it is possible to prevent an unnecessary signal from being applied to the signal line of the display device, and to obtain a clear image without ghost. The delay circuit 6 in this embodiment includes: a circuit in which even-numbered inverter circuits are connected in series; a resistor element inserted between the output of the subsequent stage and the input of the NAND circuit serving as the control circuit. A circuit in which one end of a capacitive element is connected between the input of a NAND circuit as a control circuit and a resistive element and the other end is grounded, a circuit combining the above-described circuits, or the like can be used.
[0026]
Further, by forming the circuit element constituting the present invention on one of the transparent substrates of the active matrix type liquid crystal display device, it is possible to easily realize a high quality display device without cost increase and without ghost.
[0027]
[Example 2]
FIG. 3 is an equivalent circuit diagram showing an example of the horizontal scanning circuit according to the second aspect of the present invention.
[0028]
The configuration will be described. From each stage of the horizontal scanning circuit 2 in the figure, an ON period is a half cycle of the shift clock CLX (not shown), and a signal whose phase is shifted by a half cycle of the shift clock CLX is continuously output. I have. And enter the adjacent second output of the output of each stage, one is a negative active in a control circuit _{(NAND 1, NAND 2, ···} , NANDm) and the inverter circuit _INV 1, _INV 2, · · ·, The signals are output as signal line selection switch driving panels SX ₁ , SX ₂ ,..., SXm via INVm. Here, a delay circuit 6 indicated by Delay is inserted between the output of the previous stage of the two adjacent outputs of the horizontal scanning circuit 2 and the negative active input terminal of the control circuit. Delays the output of the preceding stage, the output of the control circuit and the start timing of the signal line selection switch drive pulse are delayed.
[0029]
As a result, a pause period is generated between the adjacent signal line selection switch drive pulses, and this pause period is allocated to the time during which the video signal is changing in the same manner as in the first embodiment. Thus, a clear image without ghost can be obtained.
[0030]
[Example 3]
FIG. 4 is an equivalent circuit diagram showing an example of the horizontal scanning circuit according to the third aspect of the present invention.
[0031]
First, the configuration will be described. The shift register 5 in the figure has a configuration in which the shift direction can be switched between forward and reverse by setting control terminals Φ and Φ.
[0032]
When Φ is active and Φ is inactive. _{CIΦ 1, CIΦ 2, ···,} CIΦn, ···, CIΦm +2 becomes _{conductive, CIΦ 1, ···, CIΦ 2} , ···, CIΦn, ···, CIΦm +2 is a non-conductive state Become. The shift register DX (not shown) shifts through the shift register 5 from left to right. This is referred to as forward scanning. In the figure, the output of a clocked inverter circuit CIΦn is a first control circuit which receives the output itself and the output via a delay circuit 6 composed of two inverters connected in series to delay the output. It becomes an inverted output whose start timing is delayed by a certain NDn- ₁ . The output of CIΦn _{+ 1} delayed by half a CLX cycle from the output of the clocked inverter circuit CIΦn has its start timing delayed by NDn, which is a second control circuit that receives the output itself and the output from the delay circuit as inputs. The inverted output is made. The output of the first control circuit NDn- _{1 and} the output of the second control circuit NDn are input to a third control circuit NORn- ₁ . As a result, the output starts at the start timing of the second control circuit NDn. A signal line selection switch drive pulse SXn- ₁ ending at the end timing of one control circuit NDn _{- 1} is output.
[0033]
FIG. 5 is a timing chart for explaining the operation of the horizontal scanning circuit shown in FIG. In the figure, NORn- ₁ is the output of the control circuit NORn- ₁ of FIG. 4 and is the signal line selection switch drive pulse SXn- ₁ . Similarly, NORn is an output of the control circuit NORn and is the signal line selection switch drive pulse SXn. NORn- ₁ starts at the start timing of NDn and ends at the end timing of NDn- ₁ . NORn starts at the start timing of NDn _{+ 1} and ends at the end timing of NDn. As a result, a pause period occurs between NORn- ₁ and NORn, that is, between SXn- ₁ and SXn, and this pause period is allocated to the time during which the video signal is changing, so that unnecessary signals on the signal lines of the display device are generated. Is prevented from being applied, and a clear image without ghost can be obtained.
[0034]
Next, when Φ is active and Φ is inactive. CIΦ _1, CIΦ _2, becomes ···, CIΦn, ···, and CIfaiemu ₊₂ conductive _{state, CIΦ 1, CIΦ 2, ···} , CIΦn, ···, CIΦm +2 becomes non-conductive. The shift data DX shifts in the shift register 5 from right to left. This is referred to as reverse scanning. In this case, CIΦn _{+ 1} is the former stage and CIΦn is the latter stage delayed by half the CLX cycle. In the reverse scan, the same circuit operation as in the above-described forward scan allows an idle period to be provided between NORn and NORn- _{1, that} is, between successive signal line selection switch drive pulses. It is possible to prevent application of unnecessary signals to the lines and obtain a high-quality image free from ghost.
[0035]
【The invention's effect】
As described above, the horizontal scanning circuit according to the present invention is a horizontal scanning circuit that sequentially generates a signal line selection switch driving pulse for a matrix display device, and includes a pause period between adjacent signal line selection switch driving pulses. Is provided with a delay circuit and a control circuit so that
[0036]
By allocating this pause period to the time when the video signal sampled and held by the sampling clock is changing, unnecessary signals are prevented from being applied to the signal lines of the display device, and as a result, a clear image without ghost is obtained. realizable.
[Brief description of the drawings]
FIG. 1 is an equivalent circuit diagram of a first embodiment of the present invention.
FIG. 2 is a timing chart for explaining scanning by the horizontal scanning circuit shown in FIG. 1;
FIG. 3 is an equivalent circuit diagram of a second embodiment of the present description.
FIG. 4 is an equivalent circuit diagram of a third embodiment of the present description.
FIG. 5 is a timing chart for explaining the operation of the horizontal scanning circuit shown in FIG. 4;
FIG. 6 is an equivalent circuit diagram of a liquid crystal display device with a built-in driver.
FIG. 7 is an operation timing chart of a conventional horizontal scanning circuit.
FIG. 8 is an operation timing chart of the conventional horizontal scanning circuit.
[Explanation of symbols]
1. Input terminal 2. 2. horizontal scanning circuit 3. Counter electrode Vertical scanning circuit5. Shift register 6. Delay circuit

Claims (5)

In a horizontal scanning circuit that can be switched between forward and reverse scanning directions by setting a control terminal,
A first delay circuit that receives a first signal output from the Nth stage of the shift register in the horizontal scanning circuit and outputs a second signal obtained by delaying the first signal;
A first control circuit that inputs the first signal and the second signal and outputs a third signal that starts at a start timing of the second signal and ends at an end timing of the first signal; ,
A second delay circuit that inputs a fourth signal, which is an output from the subsequent stage of the N-th stage of the shift register, from the first signal, and outputs a fifth signal obtained by delaying the fourth signal; ,
A second control circuit that inputs the fourth signal and the fifth signal, and outputs a sixth signal that starts at the start timing of the fifth signal and ends at the end timing of the fourth signal; ,
A third control circuit that inputs the third signal and the sixth signal, and outputs a pulse that starts at the start timing of the sixth signal and ends at the end timing of the third signal;
A horizontal scanning circuit, comprising: The horizontal scanning circuit according to claim 1,
The horizontal scanning circuit, wherein the delay circuit is configured by one or more inverter circuits. The horizontal scanning circuit according to claim 1,
The horizontal scanning circuit, wherein the delay circuit includes one or more resistance elements and one or more capacitance elements. The horizontal scanning circuit according to claim 1,
The horizontal scanning circuit, wherein the delay circuit includes one or more stages of inverter circuits, one or more resistance elements, and one or more capacitance elements. A liquid crystal display device comprising the horizontal scanning circuit according to claim 1.

Images