KR101533221B1 - Active matrix type display device - Google Patents

Active matrix type display device Download PDF

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KR101533221B1
KR101533221B1 KR1020097009767A KR20097009767A KR101533221B1 KR 101533221 B1 KR101533221 B1 KR 101533221B1 KR 1020097009767 A KR1020097009767 A KR 1020097009767A KR 20097009767 A KR20097009767 A KR 20097009767A KR 101533221 B1 KR101533221 B1 KR 101533221B1
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connected
flip
video signal
input
period
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KR1020097009767A
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KR20090068366A (en
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미쓰아키 오사메
아야 미야자키
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가부시키가이샤 한도오따이 에네루기 켄큐쇼
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Priority to JPJP-P-2006-280535 priority Critical
Priority to JP2006280535 priority
Application filed by 가부시키가이샤 한도오따이 에네루기 켄큐쇼 filed Critical 가부시키가이샤 한도오따이 에네루기 켄큐쇼
Priority to PCT/JP2007/069640 priority patent/WO2008044666A1/en
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    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611Control of matrices with row and column drivers
    • G09G3/3685Details of drivers for data electrodes
    • G09G3/3688Details of drivers for data electrodes suitable for active matrices only
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275Details of drivers for data electrodes
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00Command of the display device
    • G09G2310/02Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0235Field-sequential colour display

Abstract

When the frequency of the clock signal is made high, the pulse width of the sampling pulse is shortened, and the time for recording the video signal on the source line is short. The sampling pulse Sam sequentially rises in synchronization with the rise of the start pulse SP. As the start pulse SP rises, the sampling pulse Sam is sequentially delayed by one-half of the period of the clock signals CK and CKB in synchronization with the rise of the clock signals CK and CKB. Therefore, a sampling pulse Sam having a pulse width longer than one period of the clock signals CK and CKB is generated. In the period Ta, the desired video signal VIDEO is written to the corresponding source line. Thus, it is possible to secure the time of half a period of the clock signal for writing to the source line.
Figure R1020097009767
Source line driver circuit, sampling pulse, clock signal, video signal.

Description

[0001] ACTIVE MATRIX TYPE DISPLAY DEVICE [0002]

(Technical field)

The present invention relates to an active matrix display device and a driving method thereof. More particularly, the present invention relates to a method of generating a sampling pulse and a source line driver circuit for generating a sampling pulse.

(Background Art)

One of the driving methods of the active matrix type display device is the point sequential method. In the point-sequential driving method, the source lines are sequentially selected in a period in which one scanning line is selected, and a video signal is recorded in the pixels. More specifically, the switches connected to the respective source lines are turned on in turn by the sampling pulse generated by the source line driver circuit including the shift register, buffer, and the like. The sampling pulse has two potentials of "High" and "Low ".

A switch for conducting the video line and the source line is turned on when the sampling pulse is "High" and is turned off when the sampling pulse is "Low". When the sampling pulse rises and becomes the "High" level, the switch is turned on, and the video signal is written to the source line. Then, when the sampling pulse falls and becomes the "Low" level, the switch is turned off, and the potential of the source line is determined. In this way, the switches corresponding to the plurality of source lines arranged in the pixels sequentially turn on and off, thereby fixing the potentials of the respective source lines.

(The recording start period and the rising period) in which the sampling pulse changes from "Low" to "High" (the recording start period and the rising period) (Typically, on-current characteristics) of the transistor to be constituted. However, when the transistor is a thin film transistor formed of polycrystalline silicon, it is about 10 ns to 50 ns. When the potential of the source line changes due to the influence of noise or the like in a period in which the potential of the source line is fixed, this causes a display failure such as crosstalk (ghost). Particularly, in the case of a display device having a structure in which a video signal is divided and a video signal is inputted to a source line through a plurality of video signal lines, since a video signal is simultaneously written to a plurality of source lines, And display defects become more conspicuous.

20, which is considered to be one of the factors causing noise in the source line, overlaps with the rising period of the sampling pulse for selecting the source line in the next step. 20 is a timing chart of input and output signals of a conventional source line driver circuit. CK is a clock signal, SP is a start pulse, and VIDEO is a video signal input to a video signal line. Numbers 1, 2, and 3 of the video signal VIDEO indicate signals to be written to the source lines X_1, X_2, and X_3. Reference numerals sam_1, sam_2 and sam_3 denote sampling pulses for sampling three adjacent source lines, and T denotes a period for recording a video signal on a source line. As shown by the broken line 80 in Fig. 20, since the falling period of the sampling pulse sam_2 overlaps the rising period of the sampling pulse sam_3, noise is generated in the source line.

Therefore, the amount of noise is reduced by preventing the sampling pulses from overlapping with time in the adjacent sampling pulses (see Patent Documents 1 and 2). In addition, as shown in Fig. 21, a method of making the width of the sampling pulse shorter than half of the clock signal by using the pulse width controller (PWC) or the like is used. In this method, the writing-in period T becomes shorter than the writing-in period T in Fig.

Patent Document 1: Japanese Laid-Open Patent Application No. 2001-265289

Patent Document 2: Japanese Laid-Open Patent Application No. 2003-337320

(Disclosure of the Invention)

The timing of the sampling pulse or the video signal is determined by the variation of the delay time of the sampling pulse due to the characteristics of the transistor constituting the source line driving circuit (typically, the on-current characteristic) It is necessary to consider the time to reach As a method used for improving the display quality, there are a method of increasing the resolution by increasing the number of pixels and a method of increasing the frame frequency such as driving the double speed frame. However, when any one of these methods is used, Lt; / RTI > increases. As shown in Fig. 21, in order to prevent the falling period of the sampling pulse from overlapping with the rising period of the next sampling pulse, it is necessary to decrease the pulse width of the sampling pulse. However, Causing the problem that it is not enough.

In addition, the field sequential driving method is one of the means for increasing the resolution. However, when the image is displayed by the field sequential method, if the pulse width of the sampling pulse is made small as shown in Fig. 21, It may not be long enough. This is because, in the field sequential method, a color image is displayed by displaying the R, G, and B images in a temporally mutually interchangeable manner in one pixel, so that the length of the recording time of the video signal is expressed by a general color display method , G, and B, and spatially mixing the light from the three pixels).

Further, if the pulse width of the sampling pulse is made small, the length of the recording time of the source line is not long, and it is difficult to generate the sampling pulse. Particularly, when a thin film transistor formed of a non-single crystal semiconductor is used for a transistor of a source line driver circuit, this problem becomes present.

SUMMARY OF THE INVENTION In view of the problems associated with the improvement in display quality described above, it is an object of the present invention to provide a source line driver circuit suitable for ensuring the length of a recording time of a source line and achieving high resolution of a display device. It is also an object of the present invention to provide a method of driving a display device for reducing the number of display defects caused by overlapping of adjacent sampling pulses.

First, the recording start period and the recording end period of the sampling pulse will be described with reference to Fig. In the present invention, the sampling pulse is a pulse whose pulse width (writing period T) is determined in a period in which the potential is at the "High" level and a pulse whose potential is "Low" (Writing period T) is determined in the period of the level. If the pulse (A), the recording start time period T s is a period during which the potential at the "Low""High" is the period, i.e., "Low", and the rising period, the recording end time period T f has potential from "High" it is from , I.e., a falling period. In the case of the pulse B, the recording start period T s is a period during which the potential changes from "High" to "Low", that is, a falling period, and the recording end period T f is a period during which the potential changes from " , I.e., a rise period.

A source line driver circuit of an active matrix display device having a plurality of scanning lines, a plurality of source lines intersecting the scanning lines, and a plurality of pixels connected to the scanning lines and the source lines, to be. The source line driving circuit includes a circuit for generating a plurality of sampling pulses, at least one video signal line to which a video signal is input, and a plurality of switches connected to the source line and for connecting the source line to the video signal line in accordance with the sampling pulse .

In order to solve the shortage of the length of the writing time to the source line, the source line driving circuit of the present invention is characterized in that the writing end period of one sampling pulse is an adjacent And generates a sampling pulse.

Specifically, the source line driver circuit of the present invention is a circuit in which the sampling period of the sampling pulse is started before the video signal is switched to the video signal to be recorded by the sampling pulse, and the video signal is supplied to the next sampling pulse The sampling pulse is generated so as to be terminated before it is switched to a video signal to be recorded.

Another source line driver circuit of the present invention is characterized in that the writing period of the sampling pulse is started before the video signal to be written by the first-stage sampling pulse is inputted to the video signal line, The sampling pulse is generated so as to be terminated before it is switched to a video signal to be recorded.

Another source line driver circuit of the present invention is characterized in that the sampling period of the sampling pulse is started in a period in which the video signal is switched to a video signal to be recorded by the sampling pulse of the previous stage, The sampling pulse is generated so as to be terminated before it is switched to a video signal to be recorded.

According to another aspect of the present invention, there is provided a liquid crystal display device including a plurality of scanning lines, a plurality of source lines intersecting the scanning lines, a pixel portion having a plurality of pixels connected to the scanning lines and the source lines, And a driving method of the active matrix type display device.

A driving method of an active matrix display device according to the present invention is a driving method of an active matrix type display device that generates a plurality of sampling pulses based on a start pulse signal and a clock signal, records a video signal inputted to the video signal line, A method of driving comprising the steps of: maintaining a potential of a source line on which a video signal is recorded, inputting a video signal to a pixel connected to the selected scanning line via a source line, and determining a video signal to be displayed on the pixel;

In order to solve the display failure caused by the noise generated at the source line described above, the driving method of the present invention is characterized in that a plurality of sampling pulses are provided so that the recording end period of one sampling pulse ends after the start of the recording start period of the next sampling pulse Thereby generating a sampling pulse. Further, during the period in which the video signal is input to the pixel, the pixel portion is set to the non-display state and the pixel portion is changed from the non-display state to the display state after the video signal of all the pixels is determined. The recording period of the sampling pulse is started before the video signal inputted to the video signal line is changed to the video signal to be recorded by the corresponding sampling pulse and the video signal inputted to the video signal line is sampled by the next sampling pulse It ends before it changes to the video signal to be recorded.

In another driving method of the present invention, the writing period of one sampling pulse is started before the video signal to be written by the first-stage sampling pulse is input to the video signal line, and the video signal Is terminated before the video signal to be recorded is changed to the video signal to be recorded by the next-stage sampling pulse.

In another driving method of the present invention, the writing period of one sampling pulse starts during a period in which the video signal to be written by the sampling pulse of the previous stage is inputted to the video signal line, and the video signal inputted to the video signal line , And a plurality of sampling pulses are generated so as to be terminated before the video signal to be recorded is changed to the video signal to be recorded by the next-stage sampling pulse.

By generating the overlapping adjacent sampling pulses by the source line driver circuit of the present invention, almost all of the period in which the video signal to be recorded is input can be used for the source line recording. In this manner, since the maximum amount of time can be used for recording the source line, the video signal can be surely recorded on the source line.

In addition, when the source line driver circuit and the driving method of the present invention are employed, there is no need to generate sampling pulses shorter than the half cycle of the clock. The source line driver circuit of the present invention can generate a sampling pulse corresponding to the frequency of the clock signal without using a transistor that operates at high speed without degrading display quality. Thus, the source line driver circuit and the driving method of the present invention are very suitable for increasing the resolution of the display device.

In addition, by generating the sampling pulse with the source line driver circuit of the present invention, since the recording end period of one sampling pulse does not overlap with the recording start period of the next stage, generation of noise at the source line can be avoided .

Further, even when a video signal corresponding to source lines of different stages is recorded in the source line of the current stage during the recording period of the sampling pulse, the driving method of the active matrix type display device according to the present invention is not limited to the video Since the display period is started after the signal is determined, display failure such as crosstalk (ghost) does not occur.

1 is a timing chart of an input signal and an output signal of the source line driver circuit of the first embodiment.

2 is a block diagram of the source line driver circuit of the first embodiment.

3 is a circuit diagram of the flip-flop of Fig.

4 is a block diagram of a source line driver circuit having a buffer according to the first embodiment.

5 is a circuit diagram of the buffer of Fig.

6 is a timing chart of input signals and output signals of the source line driver circuit of the second embodiment.

7 is a block diagram of the source line driver circuit of the second embodiment.

8 is a circuit diagram of the flip-flop of Fig.

9 is a circuit diagram of the buffer of Fig.

10 is a circuit diagram of the switch of Fig.

11 is a timing chart of the input signal and the output signal of the source line driver circuit of the third embodiment.

12 is a block diagram of the source line driver circuit of the third embodiment.

13 is a timing chart of input signals and output signals of the source line driver circuit of the third embodiment.

14 is a block diagram of the source line driver circuit of the fourth embodiment.

15 is a block diagram showing a configuration example of the active matrix type display device of the present invention.

16 is a circuit diagram showing a configuration example of a pixel when the present invention is applied to an active matrix type liquid crystal display device.

17 is a circuit diagram showing a configuration example of a pixel when the present invention is applied to an active matrix type electroluminescence display device.

18A is a diagram for explaining a driving method of an active matrix display device of the present invention, and FIG. 18B is a view for explaining a driving method when the present invention is applied to a field sequential method.

19 is a view for explaining a recording start period, a recording end period, and a recording period of a sampling pulse according to the present invention.

20 is a timing chart of the input signal and the output signal of the source line driver circuit of the conventional example.

21 is a timing chart of the input signal and the output signal of the source line driver circuit of the conventional example.

22A to 22E are external views of electronic devices each having an active matrix type display device according to the present invention.

23 is an exploded perspective view of a cellular phone equipped with the active matrix type display device of the present invention.

(Best Mode for Carrying Out the Invention)

Hereinafter, a method of generating a sampling pulse according to the present invention will be described. In the present invention, as shown in Figs. 1 and 6, by generating an adjacent sampling pulse overlapping such that the recording end period of one sampling pulse ends after the start of the recording start period of the next sampling pulse, Lengthen the period.

1 and 6 are timing charts of an input signal and an output signal of the source line driver circuit of the present invention. The source line driver circuit will be described in detail in the embodiment. Reference numerals such as "CK" in Figs. 1 and 6 are commonly used with those in Figs. 20 and 21, and therefore, explanations of Figs. 20 and 21 are used.

In Fig. 1 and Fig. 6, the present invention will be described by focusing on the second sampling pulse sam_2. The writing period T_2 of the sampling pulse sam_2 ends after the writing period T_3 of the next sampling pulse sam_3 starts. By setting the recording period as described above, the adjacent sampling pulse sam_2 overlaps with the sampling pulse sam_3.

The writing period T_2 of the sampling pulse sam_2 starts before the video signal VIDEO changes from the video signal VIDEO_1 to the video signal VIDEO_2 and the video signal VIDEO starts from the video signal VIDEO_2 to the video signal VIDEO_2. (VIDEO_3).

In this way, the sampling pulse sam_2 is superimposed on the sampling pulse sam_2 for almost all of the periods in which the video signal VIDEO_2 to be written into the video signal line is input by overlapping the sampling pulse sam_2 with the adjacent sampling pulse sam_l and the sampling pulse sam_3 The video signal VIDEO_2 can be written to the source line. That is, according to the present invention, it is possible to maximize the length of the recording period to be recorded on the source line.

1 is a timing chart of the write period T of all the sampling pulses sam_1, sam_2 and sam_3 until the video signal VIDEO_1 to be written by the first-stage sampling pulse sam_1 is input to the video signal line A set example is shown.

6 shows an example in which the recording period T_2 of the sampling pulse sam_2 is started in a period in which the video signal VIDEO_1 to be written by the sampling pulse sam_1 of the previous stage is inputted to the video signal line.

By generating the sampling pulse by the method of the present invention, the video signal VIDEO_1 to be written to the different source lines by the sampling pulse sam_1 of the previous stage, before the potential of the source line is determined by the sampling pulse sam_2, Is written in the source line. Therefore, when the sampling pulse is generated by the method of the present invention, in order to drive the active matrix display device, the pixel portion is set to the non-display state during the period of inputting the video signal to the pixel portion, Thereafter, the pixel portion is switched from the non-display state to the display state. Thus, even if there is a period during which the video signal that is not to be written to the source line is written by the sampling pulse sam in the writing period T, there is no adverse effect on the display.

Hereinafter, with reference to the drawings, the specific configuration of the source line driver circuit and the driving method of the active matrix display device for increasing the pulse width of the sampling pulse and lengthening the writing period in each embodiment will be described.

However, it should be understood by those skilled in the art that the present invention may be embodied with many other embodiments, and that various changes in form and details may be made without departing from the spirit and scope of the present invention. Therefore, the present invention is not construed as being limited to the description of the embodiment described herein. Here, reference numerals used between different drawings are used to denote the same elements, and repetitive description thereof will be omitted.

[Example 1]

First, the configuration of the active matrix display device of the present invention will be described using the drawings.

Fig. 15 is a block diagram showing a configuration example of an active matrix display device of the present invention. An active matrix display device of the present invention includes a pixel portion 10, a source line driver circuit 11, a scanning line driver circuit 12, a plurality of source lines 13 connected to a source line driver circuit 11, And a plurality of scanning lines (14) connected to the scanning line driving circuit (12). The configuration of the active matrix type display device is the same as that of the other embodiments.

The plurality of source lines 13 are arranged in the column direction and the plurality of scanning lines 14 are arranged in the row direction so as to cross the source lines 13. [ In the pixel portion 10, a plurality of pixels 15 corresponding to the matrix formed by the source line 13 and the scanning line 14 are arranged in a matrix form. The pixel 15 is connected to the source line 13 and the scanning line 14. The pixel 15 includes a switching element and a display element. The switching element controls the selection or non-selection of the pixel based on the signal input to the scanning line 14. [ The display element controls the gradation based on the signals input from the source line 13. [

An example of the configuration of the pixel 15 will be described with reference to Figs. 16 and 17. Fig. Fig. 16 shows a configuration example of the pixel 15 when the present invention is applied to an active matrix type liquid crystal display device. The pixel 15 has a switching transistor 21 as a switching element and a liquid crystal element 22 as a display element. The gate of the switching transistor 21 is connected to the scanning line 14 and one of the source and the drain is connected to the source line 13 and the other is connected to the liquid crystal element 22.

The liquid crystal element 22 has a pixel electrode, a counter electrode, and a liquid crystal. The orientation of the liquid crystal is controlled by the electric field generated in the pixel electrode and the opposite electrode. The liquid crystal is injected between two substrates of an active matrix liquid crystal display device. The capacitor 23 is an element for holding the potential of the pixel electrode of the liquid crystal element 22 and is connected to the pixel electrode of the liquid crystal element 22. [

Fig. 17 shows a configuration example of the pixel 15 when the present invention is applied to an active matrix type electroluminescence display device. The pixel 15 has a switching transistor 31 as a switching element and a light emitting element 32 as a display element. The pixel 15 also has a driving transistor 33 connected to the gate of the switching transistor 31. [ The light emitting element 32 has a pair of electrodes and a light emitting material sandwiched between the pair of electrodes.

Hereinafter, with reference to Fig. 2, a specific configuration of the source line driver circuit of the present invention will be described. 2 is a block diagram of a source line driver circuit of this embodiment. Fig. 2 shows a source line driver circuit having n source lines. The first, second, third, ..., n-th source lines are shown as X_1, X_2, X_3, ..., X_n, respectively. In this specification and the drawings, the order 1, 2, 3, .., and n is indicated by attaching _1, _2, _3, ..., _ n to wiring, circuit, .

The source line driving circuit includes a shift register 201 to which a plurality of stages of flip-flops (FF) 200 are connected, n switches (SW) 203, a clock signal line 204 to which a clock signal (CK) An inverted clock signal line 205 to which the inverted clock signal CKB is input, and a video signal line 206 to which the video signal VIDEO is inputted. The clock signal CKB is an inverted clock signal obtained by inverting the clock signal CK.

In this embodiment, the shift register 201 has flip-flop (FF) 200 of n stages (n is an integer of 2 or more). The flip-flop 200 of each stage is connected to the clock signal line 204 and the inverted clock signal line 205 so that the input thereof alternates back and forth between the clock signal CK and the inverted clock signal CKB.

The switch 203 is a circuit for conducting the source lines X_1, X_2, X_3, ..., X_n and the video signal line 206, and is provided for each source line. The n flip-flops 200 generate and output sampling pulses sam, respectively. Each sampling pulse (sam) is input to one of the switches (203). The switch 203 is controlled to be turned on and off in accordance with the sampling pulse sam. When the switch 203 is turned on, the source line and the video signal line 206 are electrically connected, and the video signal VIDEO is input to the source line.

FIG. 3 is a circuit diagram of the flip-flop 200. FIG. Reference character "in" is an input of the flip-flop 200, and "out" The output "out" of one flip-flop 200 is input to the input "in" of the flip-flop 200 in the next step, and the start pulse SP is input to the input "in" . The reference characters "clkl" and "clk2" One of the clock inputs "clkl" and "clk2" is connected to the clock signal line 204 and the other is connected to the inverted clock signal line 205. 2, the clock input clkl in the odd-numbered stage is connected to the clock signal line 204, and the clock input clk2 in the even-numbered stage is connected to the inverted clock signal line 205 .

The flip flop 200 includes a p-type transistor 250 connected in series, a first n-type transistor 251 and a second n-type transistor 252, an inverter 253 and a clocked inverter 254, Lt; / RTI >

The source of the p-type transistor 250 is connected to the high voltage power source potential V dd and the source of the second n-type transistor 252 is connected to the low voltage power source potential V ss . The gate of the p-type transistor 250 and the first n-type transistor 251 are connected to the input "in" of the flip flop 200 and the gate of the second n-type transistor 252 is connected to the clock input "clkl Quot; That is, a circuit composed of these three transistors 250 to 252 corresponds to a circuit of a clocked inverter formed of two p-type transistors and two n-type transistors, and is connected to Vdd, Except for the p-type transistor to be controlled.

The inverter 253 has its input connected to the drain of the p-type transistor 250 and the drain of the first n-type transistor 251 and its output connected to the output out of the flip-flop 200. The clocked inverter 254 has an input connected to the output of the inverter 253 and an output connected to the input of the inverter 253 and to the drain of the p-type transistor 250 and the drain of the first n-type transistor 251 Respectively.

The clocked inverter 254 is a means for maintaining the potential of the node S 3 . The clocked inverter 254 is connected to the clock inputs "clkl" and "clk2 " and functions as an inverter in synchronization with the clock signal input from the clock input" clk2 ". Instead of the clocked inverter 254, a storage capacitor may be connected to the node Sa to maintain the potential of the node Sa.

In the source line driver circuit shown in FIG. 2, the sampling pulse sam is outputted from the node S 3 or the node Sb of the flip flop 200. The output of the node, Sb is a reversal of the output node S 3 relationship.

1 is a timing chart of an input signal and an output signal of the source line driver circuit shown in Fig. 1 shows a state in which the sampling pulse sam is output from the node Sa of the flip flop 200 and the switch 203 turns on the source line and the video signal line 206 when the sampling pulse Sam is at the &Quot; low "level), and sets them to non-conducting when they are at the" Low " level.

When the start pulse SP changes from "High" to "Low", the p-type transistor 250 of the first-stage flip-flop 200_1 is turned on while the start pulse SP is "Low"Quot; Low "level signal is transmitted to the input " in " Further, the node Sa of the flip-flop 200 at each stage becomes "High" from "Low", and the sampling pulses sam_1, sam_2, sam_3, ..., sam_n are generated and output. That is, the recording start period T s of the sampling pulses sam_1, sam_2, sam_3, ..., sam_n is synchronized with the start pulse SP.

That is, the sampling pulse sam is generated so that the writing period T of the sampling pulse sam is set to start before the video signal is switched to the video signal to be written. In the example of Fig. 1, the recording period T of each sampling pulse (sam) starts before the video signal is changed to the video signal (VIDEO_1).

When the start pulse SP changes from "Low" to "High", the potential of the node Sa of the flip-flop 200_1 in the first stage is maintained at "High" during the half period of the clock signal CK. When the clock signal CK rises, the potential of the node Sa of the flip-flop 200_1 in the first stage becomes "Low ", and the potential of the node Sb becomes" High ".

Therefore, in the flip-flop 200 in the second and subsequent stages, the potential of the node Sa sequentially goes from "High" to "Low" due to a delay of half a cycle of the clock signals CK and CKB, To "High ".

1, the writing periods T_1, T_2, T_3, ..., T_n of the sampling pulses sam_1, sam_2, sam_3, ..., sam_n are divided into half periods of the clock signals CK and CKB And ends with a delay. As a result, the writing period T (pulse width) of the sampling pulse sam becomes longer than one cycle of the clock signals CK and CKB by the source line driving circuit of Fig.

In the video signal line 206, a video signal VIDEO is inputted corresponding to the arrangement of the source lines. It is seen that the numbers 1, 2, and 3 of the video signal VIDEO in Fig. 1 are signals to be written in the source lines X_1, X_2, X_3, ..., X_n. The start period and the end period of the sampling pulse sam are delayed from the clock signals CK and CKB due to the internal delay of the flip-flop 200 or the like. The video signal VIDEO is input to the video signal line 206 in consideration of the delay of the sampling pulse sam.

When the sampling pulses sam_1, sam_2, sam_3, ..., sam_n are inputted to the respective switches 203_1, 203_2, 203_3 ... 203_n, the switches 203_1, 203_2, 203_3, And recording of the video signal VIDEO starts on the source lines X_1, X_2, X_3, ..., X_n.

Since the write periods T_1, T_2, T_3, ..., T_n of the sampling pulses sam_1, sam_2, sam_3, ..., sam_n are delayed by half a period of the clock signals CK, CKB, The switches 203_1, 203_2, 203_3, ..., 203_n are sequentially turned off, and the potentials of the source lines X_1, X_2, X_3, ..., X_n are determined. A video signal VIDEO is written to the pixels connected to the selected scanning line in this period via the source lines X_1, X_2, X_3, ..., X_n.

For example, when the writing to the source line X_2 is started by the sampling pulse sam_2, the video signal VIDEO_1 is written first, the video signal VIDEO_2 is written in the period T_2, and the potential of the source line X_2 is And is determined as the potential of the video signal VIDEO_2. That is, the period Ta means a period in which the video signal VIDEO to be written to the source line is written by the sampling pulse sam.

The minimum length of the period for switching the video signal VIDEO is a half period of the clock signals CK and CKB. The period Ta_2 during which the video signal VIDEO_2 is written to the source line X_2 is set to the period Ta_2 during which the video signal VIDEO_2 is input by setting the recording end period Tf of the sampling pulse sam to be immediately before the switching of the video signal VIDEO It can be almost the same length. In other words, the length of the period Ta_2 can be made substantially equal to the half period of the clock signals CK and CKB. Thus, in this embodiment, since the maximum time, which is the half cycle of the clock signals CK and CKB, can be used for recording the video signal VIDEO, it is possible to record the video signal VIDEO very reliably on the source line have.

Further, since the width of the sampling pulse (writing period T) is longer than one cycle of the clock signals CK and CKB, the frequency range of the video signal capable of generating sampling pulses is wide in the source line driver circuit of this embodiment.

Further, in the adjacent sampling pulse (sam), since the write start period Ts and the write end period Tf do not overlap, generation of noise at the source line can be eliminated.

1, the length of the recording period T of the sampling pulse (sam) is longer than the period Ta in which the video signal to be recorded is recorded, and the length of the video signal to be recorded in the previous row A signal is also recorded. Therefore, when a display device having the source line driver circuit of Fig. 2 is operated, a writing period (hereinafter also referred to as an "address accumulation period") for writing a video signal to the pixels of the pixel portion, Display state; After the address accumulation period is over, the display unit 10 is set to the display state, and gradation is displayed on each pixel according to the recorded video signal data.

A driving method of the active matrix type display device of the present invention will be described with reference to Fig. 18A is a diagram showing the relationship between the scanning of the scanning line, the display period of the pixel portion 10, and the address accumulation period. As shown in Fig. 18A, the address accumulation period? Is included in the non-display period Tnd. In the non-display period Tnd, the m scanning lines Y_1 to Ym are sequentially selected and the video signal VIDEO is written to the pixel 15 via the source lines X_1, X_2, X_3, ..., X_n. After the lapse of the address accumulation period?, The display period Tdis starts.

18B is a diagram showing the relationship between the scanning of the scanning line in the case of performing display in the field sequential manner, the display period of the pixel portion 10, and the address accumulation period. In one frame period, the display period is divided into three periods: a display period Tdis_R for displaying a red image, a display period Tdis_G for displaying a green image, and a display period Tdis_B for displaying a blue image. Data is accumulated in the pixel 15 in the non-display period Tnd preceding the display periods Tdis_R, Tdis_G, and Tdis_B. In the field sequential method, the frequency of the video signal VIDEO increases. However, by using the source line driving circuit of Fig. 2, the sampling pulse sam can be generated by following the frequency of the video signal VIDEO The writing period Ta to the source line can be secured.

In order to have the non-display period Tnd and the display period Tdis in one frame as shown in Figs. 18A and 18B, in the case of the liquid crystal display, when the backlight is made non-lighting in the non-display period Tnd and the backlight is turned on in the display period Tdis good. In the case of the electroluminescence display device, the light emitting element 32 (see FIG. 17) may be set in the non-lighting state in the non-display period Tnd and turned on in the display period Tdis. The non-lighting state and the lighting state of the light emitting element 32 can be controlled by, for example, controlling the voltage of both electrodes of the light emitting pixel 32. [

In the source line driver circuit of the present invention, video signals corresponding to source lines at different stages in the address accumulation period? Are recorded in the source line, but as shown in Figs. 18A and 18B, After the determination, the display period Tdis is started, so that display defects such as crosstalk (ghost) do not occur.

2, the output from the flip-flop 200 is connected to the switch 203, but the output of the flip-flop 200 is connected to the buffer (Buff) 209 And the sampling pulse sam may be input to the switch 203 via the buffer 209. [ An equivalent circuit diagram of the buffer 209 in this case is shown in Fig. For example, the buffer 209 may be composed of an even number of inverters 210 connected in series. 5 shows an example in which two inverters 210 are connected in series.

Although the example of outputting the sampling pulse sam from the node Sa of the flip-flop 200 is described in the timing chart of Fig. 1, the sampling pulse sam may also be output from the node Sb of the flip- In this case, in the source line driver circuit of FIG. 2 or FIG. 4, the switch 203 may be turned on when the sampling pulse sam is "Low" and off when the sampling pulse "sam" is "High". Alternatively, when the switch 203 is turned on when the sampling pulse "sam" is "High" and turned off when it is "Low", a buffer 209 is provided as shown in FIG. The output from the node Sb of the flip-flop 200 in the buffer 209 may be inverted and input to the switch 203. [ In this case, the buffer 209 may be constituted by an odd number of serially connected inverters.

2, the sampling pulse sam can be output from the node Sa or the node Sb of the flip-flop 200, and the switch 203 can be controlled according to the output of the flip- And buffers 209, or alternatively, other logic circuits or other logic circuits may be added.

[Example 2]

The present embodiment describes a source line driver circuit having a structure different from that of the first embodiment. In this embodiment, a configuration of a source line driver circuit that generates a sampling pulse whose pulse width is longer than a half cycle of a clock signal and shorter than one cycle of a clock is described.

7 is a block diagram of the source line driver circuit of this embodiment. The source line driving circuit includes two-phase shift registers 401 and 402, n switches SW3 and 403, n buffers 404 connected to the switch 403, And n logic circuits 405 for performing logical operations of pulses output from the shift register 402 or pulses outputted from the shift register 402. [ The source line driver circuit also includes a clock signal line 406 to which the clock signal CKl is input, an inverted clock signal line 407 to which the inverted clock signal CKBl is input, a clock signal CK2 to which the clock signal CK2 is input, An inverted clock signal line 409 to which the inverted clock signal CKB2 is input and a video signal line 410 to which the video signal VIDEO is input. The clock signal CKBl is an inverted clock signal obtained by inverting the clock signal CKl and the clock signal CKB2 is an inverted clock signal obtained by inverting the clock signal CK2.

The shift registers 401 and 402 have a plurality of flip-flops 400. The flip-flops 400 of the shift registers 401 and 402 are all of the same configuration. In the shift register 401, the flip-flop 400 of each stage is connected to the clock signal line 406 and the inverted clock signal line 407 so that the inputs of the clock signal CKl and the inverted clock signal CKBl are changed back and forth. Respectively. In the shift register 402, the flip-flop 400 of each stage is connected to the clock signal line 408 and the inverted clock signal line 409 so that the inputs of the clock signal CK2 and the inverted clock signal CKB2 are changed back and forth. Respectively.

Each of the switches 403 is a circuit used for conducting the source line and the video signal line 410 to each other, and one of the switches 403 is provided for each source line. The input of the sampling pulse of each switch 403 is connected to one of the buffers 404, and each switch 403 is controlled on and off in accordance with the sampling pulse sam. When the switch 203 is turned on, the source line and the video signal line 410 are electrically connected to each other, and the video signal VIDEO is input to the source line. The start pulse SP is common between the shift registers 401 and 402.

Fig. 8 is a circuit diagram of the flip-flop 400. Fig. The flip-flop 400 is a circuit having the same configuration as the flip-flop 200 of Fig. In Fig. 8, reference numeral 450 denotes a p-type transistor, 451 denotes a first n-type transistor, 452 denotes a second n-type transistor, 453 denotes an inverter, and 454 denotes a clocked inverter. Of course, instead of the clocked inverter 454 as in the flip-flop 200, it is also possible to connect the storage capacitor to the node Sa and maintain the potential of the node Sa. The output "out" of each of the shift registers 401 and 402 is connected to the input "in" of the flip-flop 400 of the next stage and the input "in" of the flip- SP) is input.

The clock signal CKl is input to the clock input "clkl" of the flip-flop 400 in the odd-numbered stage and the clock input "clkl" The signal CKBl is input. The clock signal CK2 is input to the clock input "clkl" of the flip-flop 400 in the odd-numbered stage and the clock input "clkl" The signal CKB2 is input.

The outputs of the flip-flops 400 of two adjacent stages are connected to the logic circuit 405. In the logic circuit 405, logical operations of the two input pulses are performed. The pulse input to the logic circuit 405 is extracted from either the node Sa of the flip-flop 400 or the node Sb. The operation result of the logic circuit 405 is inputted to the switch 403 through the buffer 404 as a sampling pulse sam.

In the shift register 401, the flip-flop 400 is connected to the same logic circuit 405 two-step-by-two from the first stage, and the shift register 402 receives the flip-flop 400 ) Are connected to the same logic circuit 405. That is, the output of the flip-flop 400 of the (2k-1) th stage and the (2k) th stage of the shift register 401 is connected to the logic circuit 405 of the (2k- The output of the flip-flop 400 of the (2k + 1) -th stage of the shift register 402 is connected to the logic circuit 405 of the (2k) -th stage.

The logic circuit 405 connected to the shift register 401 is connected to the switch 403 at the odd-numbered stage and the logic circuit 405 connected to the shift register 402 is connected to the switch 403 at the even- .

6 is a timing chart of the input signal and the output signal of the source line driver circuit of FIG. 6 uses a NAND circuit in the logic circuit 405 and uses a buffer for inverting and outputting the signal input to the buffer 404. When the sampling pulse sam is "High" Quot; is a timing chart in the case of a source line driver circuit using a switch that is turned on when the source line driver circuit is turned on. A circuit diagram of the buffer 404 in this case is shown in Fig. 9, and a circuit diagram of the switch 403 in this case is shown in Fig.

As shown in Fig. 9, the buffer 404 is formed of an odd number of inverters 455 connected in series. 9 shows an example in which the inverter 455 is connected in three stages in series. As shown in Fig. 10, the switch 403 is constituted by an inverter 458 and an analog switch 459.

The operations of the shift registers 401 and 402 are the same as those of the shift register 201 of the first embodiment. That is, the change of the potential of the node Sa of the flip-flop 400 is the same as that of the sampling pulse sam shown in Fig. 1 of the first embodiment.

The output of the flip-flops of two adjacent stages is connected to the logic circuit 405 of each stage. In the timing chart of Fig. 6, a pulse is extracted from the node Sb of the flip-flop 400 of the previous stage, And a case where a pulse is extracted from the node Sa of the flip-flop 400 is shown. The NAND of the input two pulses is acquired in the logic circuit 405 and input to the buffer 404 as a sampling pulse sam and then inverted in the buffer 404 and then input to the switch 403 .

In the present embodiment, unlike the first embodiment, the duty ratio of the clock signal CKl is not 50%, and the duty ratio of the clock signal CKl and the clock signal CK2 is "High" (Hereinafter referred to as "Low" period) longer than the half period. In addition, the clock signal CKI and the clock signal CK2 are input with one of the two clock signals delayed from the remaining phases.

The clock signals CKl, CKBl, CK2, and CKB2 can be generated by modulating a reference clock signal having a duty ratio of 50% (half-period of the pulse width). 6 and supplies them to the source line driver circuit. The logic circuit 405 modulates the NANDs of the pulses output from the flip-flop 400 in the logic circuit 405. The logic circuit 405 modulates the " High "period or the" Low "period of each of the clock signals CKl and CK2, It is possible to extract the sampling pulse sam having the same pulse width as the longer side (longer pulse width) of the "Low" period or "High" period of the clock signals CKl and CK2. As a result, the writing period T of the sampling pulse sam is longer than the half period of the clock signals CKl and CK2 and becomes shorter than one period.

Therefore, in the logic circuit 405 at the odd-numbered stage, a pulse having the same pulse width as the "Low" period of the first clock signal in synchronism with the clock signal CKl is generated as the odd-numbered sampling pulse sam do. In the logic circuit 405 at the even-numbered stage, a pulse having the same pulse width as the "High" period of the second clock signal is generated as the sampling pulse sam at the even-numbered stage in synchronization with the clock signal CK2 do.

At this time, since the NAND circuit is used in the logic circuit 405, the sampling pulse sam is inverted in the buffer 404 so that the potential of the sampling pulse sam output from the logic circuit 405 becomes "Low & And inputs it to the switch 403. FIG. 6 shows a sampling pulse sam input to the switch 403.

The pulse width of the pulse output from the flip-flop 400 in each stage in the shift register 401 and the shift register 402 is longer than one period of the clock signal as in the case of the sampling pulse sam in the first embodiment, The termination period of each pulse is delayed by the length of the period equal to the long side of the " High "period or the " Low" period of the clock signals CKl and CK2. That is, the pulses output from the flip-flop 400 in the adjacent stage have periods in which the pulses do not overlap each other. In the source line driver circuit of the present embodiment, the logic circuit 405 performs logical operations on the pulses output from the two adjacent flip-flops 400, thereby extracting the portion where the two pulses do not overlap as the sampling pulses sam .

6, the start pulse SP and the clock signals CKl and CK2 are input to the source line driver circuit of the present embodiment to output the clock signal CKl from the output of the flip- The width of all the sampling pulses sam is longer than the half period of the clock signals CKl and CK2, It can be shorter than one cycle.

Needless to say, the width of the sampling pulse extracted from the logic circuit 405 is set to the "Low" period or the "High" level of the clock signal by the characteristics of the transistors of the shift registers 401 and 402 and the logic circuit 405, Since the width is the same as the longer side of the period, although a difference arises, the present invention also includes this kind of case. As described above, the logic circuit 405 can logically calculate the pulses output from the two adjacent flip-flops 400 to extract the portion where the two pulses do not overlap as the sampling pulses sam, The pulse width of the pulse can be set as a reference based on the longer side of the "Low" period or the "High" period of the clock signals (CKl, CK2).

In the source line driver circuit of the present embodiment, sampling pulses sam are alternately extracted from the shift register 401 and the shift register 402, so that the sampling period of the subsequent sampling period is shorter than that of the adjacent sampling period The pulses (sam) are overlapping each other. Therefore, it is possible to eliminate the occurrence of noise in the source line due to the overlapping of the sampling pulses sam.

In the video signal line 410, the video signal VIDEO is input in accordance with the arrangement of the source lines. The recording start period of the sampling pulse sam is delayed from the clock signals CKl and CK2 due to the internal delay of the flip-flop 400 or the like. The video signal VIDEO is input to the video signal line 410 in consideration of the delay of the sampling pulse sam.

Also in the source line driver circuit of this embodiment, the writing period of the sampling pulse (sam) in each stage starts before the video signal is switched to the video signal to be recorded. The minimum time for switching the video signal VIDEO is half the period of the clock signals CKI and CK2. Even in this embodiment, the period Ta during which the video signal to be written to the source line is a half period of the clock signals CKl and CK2 and the period during which the video signal VIDEO to be written is input to the video signal line 410 As shown in FIG. Therefore, since the maximum amount of time can be used for writing the video signal VIDEO to the source line, the video signal VIDEO can be reliably recorded on the source line.

Also in this embodiment, as in the first embodiment, the length of the recording period T of the sampling pulse (sam) is longer than the length of the recording period Ta for recording the video signal to be recorded, A signal is also recorded. Therefore, in the display device having the source line driver circuit of this embodiment, as shown in Fig. 18 as in the first embodiment, the address accumulation period? Is set to the non-display state of the pixel portion 10; After the address accumulation period? Ends, the display unit 10 is set to the display state, and gradation is displayed in each pixel according to the recorded data.

In the source line driver circuit of Fig. 7, the NAND circuit is used for the logic circuit 405, but an operation circuit other than the NAND circuit can be used. A logic circuit 405 may be a NOR circuit. When the logic circuit 405 is a NOR circuit, the output of the node Sa is input to the logic circuit 405 from the flip-flop 400 of the previous stage and the output of the node Sb is input from the flip- And input to the logic circuit 405. Since the potential of the sampling pulse sam outputted from the NOR circuit is "High ", the buffer 404 may be omitted or the buffer 404 may be constituted by an even number of inverters connected in series. It does not.

In the source line driver circuit of Fig. 7, the switch 403 may be turned on when the sampling pulse sam is "Low ". When the NAND circuit is used in the logic circuit 405, the buffer 404 may be omitted, or the buffer 404 may be formed of an even number of inverters connected in series, so that the input signal is outputted without being inverted. When the NOR circuit is used for the logic circuit 405, the buffer 404 may be constituted by an odd number of inverters connected in series, and the input signal is inverted and output.

7 determines the logic of the switch 403, the buffer 404 and the logic circuit 405 in accordance with the pulse input from the flip-flop 400 to the logic circuit 405 good.

[Example 3]

In the first embodiment, a source line driver circuit (see Fig. 2) in which the number of video signal lines is one line has been described. In this embodiment, an example in which the number of video signal lines is k lines (k is an integer of 2 or more) in the source line driver circuit of the first embodiment will be described.

12 shows a block circuit diagram of the source line driver circuit of this embodiment. In Fig. 12, an example in which a video signal is divided into two signals (k = 2) is posted. Fig. 11 shows a timing chart of the source line driver circuit of Fig. 12. Fig.

Changes from the first embodiment will be described below. 12, the source line driver circuit of this embodiment includes a video signal line 261 for inputting one video signal VIDEO_A divided into two lines, and a video signal line 261 for inputting the other video signal VIDEO_B. 262. The video signal VIDEO_A is composed of video signals VIDEO_1, VIDEO_B, and VIDEO_B arranged in two stages starting from the first stage and the video signal VIDEO_B is arranged in two stages from the second stage And video signals VIDEO_2, 4, 6,. Also, the forward and backward switching of the video signals VIDEO_A and VIDEO_B occurs in half a cycle of the clock signals CK and CKB.

Two switches 203 are connected to the output of one flip-flop 200. Two switches 203 connected to the output of the same flip-flop 200 are connected to different ones of the video signal lines 261 and 262, respectively.

As shown in FIG. 11, the sampling pulse sam generated in the shift register 201 is the same as in the first embodiment. In this embodiment, the writing of the two adjacent source lines X_1 and X_2 is controlled by the first-stage sampling pulse sam_1 and the writing of the two adjacent source lines X_3 and X_3 is controlled by the second- The writing of X_4 is controlled and the writing of the two adjacent source lines X_ (2n-1) and X_ (2n) is controlled by the n-th sampling pulse sam_n.

Therefore, when the video signal line is two lines, the writing period Ta to the source line is not shortened, and the number of source lines, that is, the number of pixels in the horizontal direction can be doubled.

In the case of dividing the video signal into k video signal lines (the number of video signal lines is k lines), the i-th (where i is an integer equal to or larger than 1) The video signal is input. For example, the video signal VIDEO_1, the video signal VIDEO_ (1 + k), and the video signal VIDEO_ (1 + 2k) are sequentially inputted to the first video signal line.

K switches 203 are connected to the output of one of the flip-flops 200. K switches 203 connected to the output of the same flip flop 200, in other words, k switches 203 controlled by the same sampling pulse sam are connected to different video signal lines, respectively. 12, the output of the flip-flop 200 is connected to a buffer (Buff) 209, and the sampling pulse is supplied to the buffer (209) via the buffer (209) (sam) may be input to the switch 203.

The number of source lines, that is, the number of pixels in the horizontal direction, can be increased by k times without shortening the writing period Ta to the source line by making the video signal lines into k lines.

[Example 4]

In the second embodiment, the source line driver circuit (see Fig. 7) has described an example in which the video signal line is one line. In the present embodiment, an example is described in which the number of video signal lines is k (k is an integer of 2 or more) in the source line driver circuit of the second embodiment.

14 shows a block circuit diagram of the source line driver circuit of this embodiment. In Fig. 14, an example in which a video signal is divided into two signals (k = 2) is posted. Fig. 13 shows a timing chart of the source line driver circuit of Fig.

Changes from the second embodiment will be described below. 14, two lines for dividing a video signal line have a video signal line 461 for inputting one video signal VIDEO_A and a video signal line 462 for inputting the other video signal VIDEO_B . The video signal VIDEO_A is composed of video signals VIDEO_1, VIDEO_B arranged at two stages from the first stage and the video signal VIDEO_B is composed of video signals VIDEO_B arranged in two stages from the second stage, (VIDEO_2, 4, 6). The forward and backward switching of the video signals VIDEO_A and VIDEO_B occurs in half a cycle of the clock signals CK and CKB as in the third embodiment.

The buffer 404 is connected to the output of the logic circuit 405. In this embodiment, two switches 403 are connected to the output of one logic circuit 405 (buffer 404). Two switches 403 connected to the output of the same logic circuit 405 (buffer 404) are connected to different video signal lines 461 and 462, respectively. 13 is a timing chart when a NAND circuit is used for the logic circuit 405 as in the second embodiment. Of course, in this embodiment, as in the second embodiment, any arithmetic circuit other than the NAND circuit can be used. A logic circuit 405 may be a NOR circuit. When the NOR circuit is used for the logic circuit 405, the output of the node Sa is input to the logic circuit 405 from the flip-flop 400 of the previous stage, and the output of the node Sb The output is input to the logic circuit 405. Since the potential of the sampling pulse sam output from the NOR circuit is "High ", the buffer 404 may be omitted or the buffer 404 may be formed of an even number of inverters connected in series so that the input signal is not inverted May be output.

The sampling pulse sam generated by the source line driver circuit of this embodiment is the same as that of the second embodiment. In this embodiment, the writing of the two adjacent source lines X_1 and X_2 is controlled by the first-stage sampling pulse sam_1 and the writing of the two adjacent source lines X_3 and X_3 is controlled by the second- The writing of X_4 is controlled and the writing of the two adjacent source lines X_ (2n-1) and X_ (2n) is controlled by the n-th sampling pulse sam_n.

Therefore, when the video signal line is two lines, the writing period Ta to the source line is not shortened, and the number of source lines, that is, the number of pixels in the horizontal direction can be doubled.

When the video signal is divided into k video signal lines (the number of video signal lines is divided into k lines), the i-th (i is an integer of 1 or more and k or less) And a video signal arranged to be input is inputted. For example, the video signal VIDEO_1, the video signal VIDEO_ (1 + k), and the video signal VIDEO_ (1 + 2k) are sequentially inputted to the first video signal line.

K switches 403 are connected to the output of one logic circuit 405 (buffer 404). K switches 403 connected to the same logic circuit 405 (buffer 404), in other words, k switches 403 controlled by the same sampling pulse sam are connected to different video signal lines, respectively. The number of source lines can be increased by k times, that is, the number of pixels in the horizontal direction can be increased to k times, by making the video signal lines into k lines, without shortening the writing period Ta to the source lines.

[Example 5]

In the source line driver circuits of the second and fourth embodiments, the logic circuit 405 performs logic operation on the pulses output from the two adjacent flip-flops 400, so that a portion where the two pulses do not overlap with each other is referred to as a sampling pulse sam The writing period T (pulse width) of the sampling pulse sam is set not only to the longer side of the "High" period or the "Low" period of the clock signals CKl and CK2 but also to the longer sides of the clock signals CKl and CK2 Quot; High "period or" Low " In the timing charts of Figs. 6 and 13, by changing the input waveform of the clock signals CKl and CK2, the "High" period or the "Low" period (the clock signals CKl, CK2 Quot; High "period or" Low "period)

Therefore, in the source line driver circuits of the second and fourth embodiments, by changing the "High" period or the "Low" period of the clock signals CKl and CK2, the writing period T of the sampling pulse sam is changed to the clock signal CK1, and CK2, respectively.

Since the length of the writing period T is shorter than the half cycle of the clock signal by setting the short side of the "High" period or the "Low" period of the clock signals CKl and CK2 as a reference and generating the sampling pulse sam, It is possible to generate sampling pulses without any overlap between them. In this case, like the driving method of the conventional active matrix display device, the address accumulation period? May overlap with the display period Tdis.

As described above, in the source line driver circuits of the second and fourth embodiments, sampling pulses are generated by overlapping (by overlapping) by changing the duty ratio of the reference clock signal without changing the configuration of the circuit, It is a very versatile circuit because it is possible to generate both (without generating overlap).

[Example 6]

In this embodiment, an electronic apparatus including the active matrix type display device of the present invention as display means will be described. An electronic apparatus using the display apparatus of the present invention, comprising: a television receiver; A camera such as a video camera or a digital camera; Goggle type display; Navigation system; Sound reproducing apparatuses (car audio components and the like); computer; Game devices; Portable information terminals (portable computers, cellular phones, portable game machines, electronic books, etc.); An apparatus having a display capable of reproducing audio data stored in a recording medium such as a DVD (Digital Versatile Disc) or the like and displaying the image data stored therein, And the like.

By using the active matrix type display device of the present invention for various kinds of electronic devices, a high-resolution image can be displayed. Hereinafter, with reference to Figs. 22A to 22E and Fig. 23, specific examples of electronic devices thereof will be described.

22A is a TV apparatus, which has a chassis 501, a support stand 502, a display unit 503, and the like. In this TV apparatus, an active matrix display device having the source line driver circuits of Embodiments 1 to 5 is used for the display portion 503. [

22B is a laptop computer and includes a main body 511, a chassis 512, a display portion 513, a keyboard 514, an external connection port 515, a pointing device 516, and the like. An active matrix display device having the source line driver circuits of Examples 1 to 5 is used for the display portion 513 of this notebook computer.

22C is a mobile computer and includes a main body 521, a display portion 522, a switch 523, an operation key 524, an infrared port 525, and the like. An active matrix type display device having the source line driver circuits of Examples 1 to 5 is used for the display portion 522 of the mobile computer.

22D is a portable game machine and includes a chassis 531, a display portion 532, a speaker 533, an operation key 534, a recording medium insertion slot 535, and the like. An active matrix display device having the source line driver circuits of the first to fifth embodiments is used for the display portion 532 of this portable game machine.

22E is a portable image reproducing apparatus (specifically, a DVD reproducing apparatus) having a recording medium and includes a main body 541, a chassis 542, a display portion 543, a display portion 544, a recording medium reader 545 An operation key 546, a speaker 547, and the like. The display unit 543 mainly displays image information, and the display unit 544 mainly displays character information. An active matrix display device having the source line driver circuits of the first to fifth embodiments is used for at least one of the display portion 543 and the display portion 544. [ Particularly, the present invention is suitable for the display section 543 for image information.

23 is an exploded perspective view of the mobile phone. In the display module 550, an active matrix display device having the source line driver circuits of the first to fifth embodiments is used. The display module 550 is detachably incorporated in the housing 551. The housing 551 can be adapted to the size of the display module 550, and the shape and dimensions can be appropriately changed. A printed circuit board 552 may be installed in the housing 551 to which the display module 550 is fixed.

The display module 550 is connected to the printed circuit board 552 via the FPC 553. [ A signal processing circuit 558 including a speaker 555, a microphone 556, a transmission / reception circuit 557, a CPU, and a controller is attached to the printed circuit board 552. The display module 550 and the like are combined with the input means 559, the battery 560 and the antenna 561 and housed in the chassis 562. The pixel portion of the display module 550 is disposed so as to be viewed from an opening window formed in the chassis 562.

The present application is based on Japanese Patent Application No. 2006-280535 filed on October 13, 2006 in the Japanese Patent Office, and the entire contents thereof are included as a certificate.

[0011]

A liquid crystal display device according to the present invention is a liquid crystal display device which includes a liquid crystal display device and a liquid crystal display device. The present invention relates to a video signal processing circuit and a video signal processing circuit and more particularly to a video signal processing circuit and a video signal processing circuit. A first n-type transistor; 252: a second n-type transistor; 253: an inverter; 254: a clocked inverter; 261: a video signal line; 262: a video signal line; (FF) 401: shift register 402: shift register 403: switch SW: buffer 405: logic circuit 406: clock signal line 407: inverted clock signal line 408: A video signal line, a video signal line, a video signal line, and an analog video signal line. A main body of the present invention includes a main body having a chassis and a display unit having a display unit and a display unit having the display unit. The present invention relates to an information recording and reproducing apparatus and method for controlling the operation of the information recording and reproducing apparatus of the present invention. The present invention is not limited to the above embodiments and various modifications may be made without departing from the scope of the present invention. , 558: signal processing circuit, 559: input means, 560: battery, 561: antenna, 562: chassis.

Claims (32)

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  6. A plurality of scanning lines,
    A plurality of source lines intersecting with the scanning lines,
    A pixel portion having a plurality of pixels connected to the scanning line and the source line,
    k video signal lines into which video signals divided into k (k is an integer of 2 or more)
    A shift register having a plurality of stages of flip-flops to which a start pulse signal and a clock signal are inputted and which generates and outputs a plurality of sampling pulses,
    And a plurality of switches connected to the source lines and receiving the same sampling pulses for every k switches and conducting the source lines and the video signal lines to each other in accordance with the sampling pulses,
    The k switches to which the sampling pulses are input are respectively connected to the different video signal lines,
    The flip-
    A p-type transistor and a first n-type transistor connected in series and connected to the input of the flip-flop,
    A second n-type transistor which is connected in series to the first n-type transistor and to which the clock signal is input to the gate of the second n-type transistor;
    And an inverter whose input is connected to the drain of the p-type transistor and the first n-type transistor and whose output is connected to the output of the flip-flop,
    The start pulse signal is input to the input of the flip-flop of the first stage,
    The output of the flip-flop inverter of the previous stage is input to the input of the flip-flop after the second stage,
    Wherein the sampling pulse is any one of an output of the inverter, an output of the drain of the p-type transistor, and an output of the drain of the first n-type transistor.
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  8. The method according to claim 6,
    Wherein the flip-flop has a storage capacitor for holding the potential of the drain of the p-type transistor and the potential of the drain of the first n-type transistor.
  9. The method according to claim 6,
    Further comprising a plurality of buffers connected to the switch, wherein the sampling pulse is inputted to the switch via the buffer.
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  13. A plurality of scanning lines,
    A plurality of source lines intersecting with the scanning lines,
    A pixel portion having a plurality of pixels connected to the scanning line and the source line,
    k video signal lines into which video signals divided into k (k is an integer of 2 or more)
    A first shift register to which a start pulse signal and a first clock signal are inputted and which has a plurality of flip-flops,
    A second shift register having a start pulse signal and a second clock signal whose period is the same as that of the first clock signal but whose phase is delayed,
    A plurality of logic circuits for outputting sampling pulses,
    And a plurality of switches connected to the source lines and electrically connected to the source lines and the video signal lines in accordance with the sampling pulses, the active matrix type display device comprising:
    Wherein the flip-flops of the first shift register and the second shift register each comprise:
    A p-type transistor and a first n-type transistor connected in series and connected to the input of the flip-flop,
    A second n-type transistor which is connected in series to the first n-type transistor and to which the clock signal is input to the gate of the second n-type transistor;
    And an inverter whose input is connected to the drain of the p-type transistor and the first n-type transistor and whose output is connected to the output of the flip-flop,
    In the first shift register and the second shift register, the start pulse signal is input to the input of the first-stage flip-flop, the output of the inverter of the flip-flop of the previous stage Is input,
    The output of the flip-flop is either the output of the inverter, the output of the drain of the p-type transistor, or the output of the drain of the first n-type transistor,
    The outputs of the two adjacent flip-flops of the first shift register are connected to the inputs of the logic circuits of odd-numbered stages,
    The outputs of the two adjacent flip-flops of the second shift register are connected to the inputs of the logic circuits of the even-numbered stages,
    K outputs are connected to the output of the logic circuit,
    And the k switches connected to the same logic circuit are respectively connected to the different video signal lines.
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  15. 14. The method of claim 13,
    And the flip-flop has a storage capacitor for holding a potential of an output of the drain of the p-type transistor and a drain of the first n-type transistor.
  16. 14. The method of claim 13,
    Further comprising a plurality of buffers, wherein the sampling pulse is input to the switch via the buffer.
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  19. 14. The method according to claim 6 or 13,
    Wherein the source line driver circuit is built in an active matrix type liquid crystal display device.
  20. 14. The method according to claim 6 or 13,
    Wherein the source line driver circuit is built in an active matrix type liquid crystal display device of a field sequential system.
  21. 14. The method according to claim 6 or 13,
    Wherein the active matrix type display device is built in an active matrix type electroluminescence display device.
  22. 14. The method according to claim 6 or 13,
    Wherein the active matrix type display device is embedded in one selected from the group consisting of a TV device, a laptop computer, a mobile computer, a game device, a picture reproducing device, and a mobile phone.
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KR1020097009767A 2006-10-13 2007-10-02 Active matrix type display device KR101533221B1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JPJP-P-2006-280535 2006-10-13
JP2006280535 2006-10-13
PCT/JP2007/069640 WO2008044666A1 (en) 2006-10-13 2007-10-02 Source line driver circuit and driving method

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US20120133839A1 (en) 2012-05-31
WO2008044666A1 (en) 2008-04-17
US20080094343A1 (en) 2008-04-24
US8134531B2 (en) 2012-03-13
US8576155B2 (en) 2013-11-05

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