JP3200311B2 - Liquid crystal display - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device,
In particular, the present invention relates to a liquid crystal display device capable of displaying an image in response to a plurality of types of television signals such as a high-vision system and an NTSC system.

[0002]

2. Description of the Related Art Conventionally, a liquid crystal display device for displaying an image based on a current television signal such as an NTSC system or a PAL system has pixels of 400 to 600 rows in accordance with the number of scanning lines of the signal system. Or half of it, 20
A matrix liquid crystal panel composed of pixels in rows 0 to 300 and composed of pixels in columns 400 to 800 has been used because of its signal band.

In recent years, high-definition televisions have become widespread, and there has been an increasing demand for liquid crystal displays capable of displaying high-definition television signals.

The number of scanning lines in the high vision system is 1125.
The number of effective scanning lines is 1,035. The signal band is 30 MHz, the aspect ratio is 16: 9,
As a liquid crystal panel for displaying a high-definition television signal, a matrix of 1000 rows × 1800 columns or more is desirable.

[0005] Under these circumstances, the liquid crystal display device for displaying the high-vision television signal as described above is currently in a transition period to the high-vision system.
It is desired that the current television signal can be switched and displayed.

A liquid crystal display device capable of displaying both the high definition television signal and the NTSC television signal is disclosed in Japanese Patent Application Laid-Open No. 5-83658. In the liquid crystal display device disclosed in Japanese Patent Application Laid-Open No. Hei 5-83658, the signals of the effective display period of the video signal of each scanning line for one field of the NTSC television signal are sequentially and simultaneously written to four lines of the liquid crystal display panel. Or
Or a row driver for sequentially writing the signals of the effective display period of each of the 525 scanning lines of the NTSC television signal which has been double-speed converted into two lines of the liquid crystal display panel simultaneously;
A column driver that writes a period before and after the effective display period of the video signal of each line so that the effective display portion of the video signal is displayed at the center of the screen using a clock having a frequency higher than that within the effective display period. It is a thing.

[0007]

SUMMARY OF THE INVENTION The above-mentioned JP-A-5-83
In the liquid crystal display device disclosed in US Pat.
When a TSC television signal is displayed, writing is performed simultaneously on four or two lines of the liquid crystal display panel. When the liquid crystal is driven by AC, the writing is applied to the four or two lines of pixels that are simultaneously written. All video signals had the same polarity. For this reason, the spatial frequency in the AC driving of the liquid crystal is reduced to 1/4 or 1/2 in the row direction, and since the polarity is not inverted at all in the column direction, line flicker occurs in the row direction. There was a technical problem to be solved that significantly deteriorated the resolution. The present invention solves the above-described problems, and can display a television signal of a system with a small number of scanning lines and a low signal band (for example, a current system such as NTSC) on a liquid crystal panel that displays a television signal of a high-vision system. Another object of the present invention is to provide a liquid crystal display device capable of displaying an image with reduced flicker.

[0008]

The liquid crystal display device of the present invention has the following configuration.

That is, the liquid crystal display device of the present invention includes a liquid crystal panel sandwiching liquid crystal between a substrate provided with a plurality of pixel electrodes and a counter substrate provided with a counter electrode facing the substrate. A liquid crystal display device which displays an image based on a television signal of the above, wherein the image is displayed based on a television signal of a system having a smaller number of scanning lines than the scanning lines of the liquid crystal panel which displays the image according to the high definition system. when it is the based on the television signal of the scanning line having a small number of scheme, as written in the pixel where the data of the pixels corresponding to the corresponding to the other pixel electrode to one of said plurality of pixel electrodes The analog video signal
First and second digital signals that are
A / D converter and one horizontal scan of the digital signal
First and second line memories for storing line segments;
Digital signal stored in memory is converted to analog video signal
And first and second DA converters for converting
Two sets of digital video signal storage devices and each
Digital signal storage device alternately selects the output signal.
A first analog switch and a second analog switch;
Data writing and reading are independent and unsynchronized.
Can be performed during the
The writing is alternately driven every horizontal period of the video signal.
Read data from the line memory with respect to the write
Driving twice with a half horizontal period delayed, the analog
Double-speed scan code that alternately selects and outputs with a switching switch
An inverter is provided .

The liquid crystal display device of the present invention digitally samples a video signal every one horizontal period, reads out and outputs it twice at twice or more the speed of sampling and writing, and an AC drive for driving the liquid crystal by AC. A video driver and an inverting amplifier for inverting an output signal of the video driver may be provided so that two AC-driven video signals of opposite polarities are input to the liquid crystal panel.

The video signals of the opposite polarity are input to sample holders connected to two shift registers for selecting the 2n-1 and 2n columns, respectively, or alternately select the video signals of the opposite polarity. Input can be made to a sample holder connected to one shift register.

The liquid crystal display device of the present invention has a 4 m-
Select 3, 4m-2, 4m-1, and 4m rows respectively 4
And two vertical shift registers are driven by a two-phase clock, and one of the clocks is H
The output terminal can be sequentially selected and scanned every time the state becomes the high state.

In the liquid crystal display device of the present invention, a liquid crystal display panel for displaying an image based on a high definition television signal is provided with a television signal of a system having a small number of scanning lines and a low signal band, for example, a television of a current system. An image based on the John signal can be displayed on the entire liquid crystal display panel by writing a video signal written to one pixel to a plurality of pixels.

In the case where video signals written in adjacent vertical and horizontal pixels are written in opposite polarities with respect to the potential of the counter substrate electrode, the spatial frequency of flicker (blinking) rises dramatically, and A display with a sense of image is obtained, and an image display that is easy to see and does not cause the observer to feel tired becomes possible.

In the case where two sets of digital sampling means of the double speed scan converter are provided and the output is alternately selected every horizontal period, a uniform no signal is displayed on the non-image portion. In addition, even in liquid crystal panels having different aspect ratios, an image can be displayed without changing the aspect ratio of the current image.

[0016]

Embodiments of the present invention will be described below with reference to the drawings.

Embodiment 1 FIG. 1 is a block diagram showing an example of a liquid crystal display device of the present invention.

In FIG. 1, 1 is a liquid crystal panel with a built-in shift register, 2 is a video signal input terminal, 3 is a synchronization separation circuit, and 4 is a double speed scan converter. 5 is a video driver, 6 is a timing generator, 7 is an inverting amplifier, and 8 and 9 are signal input terminals of the liquid crystal panel 1. 10
Is a synchronization signal separated from the video signal by the synchronization separation circuit 3, 11 is a polarity inversion pulse for AC driving the video signal, and 12 is a clock for controlling the double speed scan converter. Reference numeral 13 denotes a driving pulse of a shift register built in the liquid crystal panel 1, and 14 denotes a double-speed scan converter 4.
Is a video signal output that has been double-speed-converted.

The video signal input from the input terminal 2 is input to the sync separation circuit 3. Here, the synchronization signal 10 separated from the video signal is input to the timing generator 6. The timing generator 6 uses the synchronization signal as a reference to drive the driving pulse 13 of the shift register in the liquid crystal panel 1 and the control clock 1 of the double-speed scan converter 4.
2 and a polarity inversion pulse 11 to the video driver 5 are output.

The video signal 3a separated from the synchronization signal by the synchronization separation circuit 3 is sent to the double-speed scan converter 4. FIG. 2 shows the configuration of the double-speed scan converter. FIG.
, 15 is an AD converter, 16 is a line memory, and 17 is a DA converter. 18 is a write clock from the timing generator 6, 19 is a write reset, 20 is a read clock, 21 is a read reset, 22 is output data of the A / D converter 15, 2
Reference numeral 3 denotes output data of the line memory 16. FIG. 3 shows a timing chart.

The synchronously separated video signal 3a input to the double-speed scan converter 4 is converted into an A / D converter 15
Sampled at the frequency of the write clock 18,
A digital signal is written to the line memory 16. The line memory 16 reads the signal at the frequency of the read clock 20, and the DA converter 17 returns the signal to an analog signal. The write reset 19 is a signal for resetting the write address pointer of the line memory 16 to address 0, and the read reset 21 is a signal for resetting the read address pointer to address 0. Reference numeral 22 denotes output data of the A / D converter, and reference numeral 23 denotes output data of the line memory.

According to the timing chart shown in FIG. 3, by setting the read clock 20 and the read reset 21 at twice the frequency of the write clock 18 and the write reset 19, respectively, the input signal is delayed by 1 / 2H phase for one horizontal period. It is understood that an output signal such as 14a that outputs the same signal twice is obtained.

The output signal of the double speed scan converter 4 is input to the video driver 5. FIG. 4 shows the video driver 5
2 shows an operation timing chart. In the video driver 5, the polarity inversion pulse 1 from the timing generator 6 is output.
In synchronization with the liquid crystal panel 1, the liquid crystal panel 1 is converted so that the liquid crystal is AC-driven as shown by input terminal waveforms 8 and 9. The polarity inversion pulse 11 is a signal of one horizontal period, and inverts the polarity of the video signal doubled by the double speed scan converter 4.
The waveform 9 is always input to the liquid crystal panel 1 by the inverting amplifier with a polarity opposite to that of the waveform 8.

FIG. 5 is a schematic view of the liquid crystal panel 1. In the figure, reference numeral 24 denotes a first horizontal shift register that selects 2n-1 columns, 25 denotes a second horizontal shift register that selects 2n columns, and 26 samples and holds a video signal input from the video input terminal 8. First sample holder, 27
Is a second sample holder that samples and holds a video signal input from the video input terminal 9. 28 is 4m-
First vertical shift register for selecting 3 rows, 29 is 4m
-2nd vertical shift register for selecting row, 30 is 4
A second vertical shift register for selecting the (m-1) -th row, and a fourth vertical shift register 31 for selecting the 4m-th row are provided. 3
Reference numeral 2 denotes a signal line, 33 denotes a scanning line, and 34 denotes a pixel electrode. A plurality of pixel electrodes 34 are arranged in a matrix along the signal line and the scanning line. The liquid crystal is sandwiched between the substrate provided with the pixel electrode 34 and a not-shown counter substrate provided with a counter electrode facing the pixel electrode 34. 35 is a first horizontal shift register 2
4 start pulses HST1, 36 and 37 correspond to the clock pulses HCK1 and-
1 shows HCK1. 38 is a second horizontal shift register 25
Start pulses HST2, 39 and 40 are clock pulses HCK2 and -H of the second horizontal shift register 25.
CK2 is shown. 41 is a start pulse VST1 of the first vertical shift register 28, 42 and 43 are clock pulses VCK1 and -VC of the first vertical shift register 28.
K1 is shown. 44 is a start pulse VST2 of the second vertical shift register 29, and 45 and 46 are clock pulses VCK2 and -VCK of the second vertical shift register 29.
2 is shown. 47 is a start pulse VST3 of the third vertical shift register 30, and 48 and 49 are clock pulses VCK3 and -VCK3 of the third vertical shift register 30.
Is shown. Reference numeral 50 denotes a start pulse VST4 of the fourth vertical shift register 31, and reference numerals 51 and 52 denote clock pulses VCK4 and -VCK4 of the fourth vertical shift register 31.

Hereinafter, a first driving method using the circuit configuration of this embodiment will be described. The timing charts are shown in FIGS. 6 and 7 and will be described below with reference to them.

The video signals input from the video signal input terminals 8 and 9 are input to sample holders 26 and 27, respectively. In the sample holder 26, the video signal is sampled in synchronization with the start pulse 35 and the clock pulses 36 and 37 of the horizontal shift register 24.
In the sampling holder 27, the start pulse 38 of the horizontal shift register 25 receives the clock pulses 39, 4
The video signal is sampled in synchronization with 0. The sampled video signal is sent to a signal line 32 connected to each sampling holder. Since the signal lines are alternately connected to the sample holders 26 and 27, the same video data having opposite polarities is sent to the adjacent 2n-1 and 2n signal lines.

The vertical shift registers 28, 29, 30 and 31 are provided with start pulses 41, 44, 47 and 5 respectively.
0, the clock pulses 42, 45, 4
The scanning lines 33 are sequentially selected when 8 and 51 are in the High state. When the scanning lines 33 are sequentially selected, a sampled video signal is written to a pixel electrode connected to the selected scanning line 33. FIG. 8 shows an equivalent circuit diagram of the pixel portion of this example. 53 is a TFT (thin film transistor), 54 is a liquid crystal, 55 is a storage capacitor, and 56 is a counter substrate electrode. The scanning line 33 is connected to the gate of the TFT, and the signal line 32 is connected to the source of the TFT. The drain of the TFT is connected to a liquid crystal 54 via a pixel electrode (not shown), and is further grounded via a storage capacitor 55.

In this embodiment, an active matrix type liquid crystal display panel using TFTs will be described as an example. However, the liquid crystal display device of the present invention is applied to a panel using other nonlinear elements or a simple matrix type panel. It goes without saying that it is possible.

The first vertical shift register 28 and the third vertical shift register 30 are doubled in speed by the double-speed scan converter 4 and are one of the video signals output twice shown in FIG.
The scanning lines 33 of 4m-3 and 4m-1 rows are selected in the third effective video period. Then, the second vertical shift register 29
The fourth vertical shift register 31 is doubled in speed by the double speed scan converter 4, and selects the scanning lines 33 of 4m-2 and 4m rows in the second effective video period of the video signal output twice. Since the doubled video signals are AC-driven with opposite polarities, the adjacent 4m-3, 4m-2, 4m-3
The same pixel data of opposite polarities is written to the pixels connected to the m-1 and 4m rows.

The start pulse 47 of the third vertical shift register 30 and the start pulse 50 of the fourth vertical shift register 31 are the same as the start pulse 4 of the first vertical shift register 28 in the odd field.
The reset is performed at the same timing as the start pulse 44 of the first and second vertical shift registers 29. In contrast,
In even fields, start pulses 47, 50
Are shifted by 1H period as compared with the start pulses 41 and 44, respectively, thereby shifting the row in which the same data is written. Thereby, the vertical resolution can be improved.

According to this driving method, the same data is written in a pixel block of 2 columns × 4 rows, and pixels adjacent in the vertical and horizontal directions have opposite polarities.

Further, on the entire screen of the liquid crystal panel 1,
Pixels adjacent in the vertical and horizontal directions have opposite polarities.

FIG. 9 shows the state of the signal polarity written on the panel.

In FIG. 9, reference numeral 57 denotes a pixel written with a positive polarity, 58 denotes a pixel written with a negative polarity, and 59a denotes an area where the same data is written. As a result, the spatial frequency of the AC inversion of the liquid crystal is the highest in both the vertical and horizontal directions, and no flicker occurs. Therefore, it is possible to suppress the fatigue of the eyes of the observer, to obtain an image with good display quality and a sense of resolution.

Next, a second driving method using the circuit configuration of this embodiment will be described with reference to FIG.

In the driving method, the start pulse 35 and the clock pulse 3 of the first horizontal shift register 24 are used.
6, the start pulse and the clock pulse 38b, 39b, 40b of the second horizontal shift register are delayed in phase by 1/4 period as shown in FIG.

In this way, the sampling timing is shifted between the first horizontal shift register 24 and the second horizontal shift register, so that the horizontal resolution can be doubled.

FIG. 10 shows the state of signal polarity when this driving method is used. In FIG. 10, reference numeral 57 denotes a pixel written with a positive polarity, and 58 denotes a pixel written with a negative polarity.

As understood from FIG. 10, the area where the same data is written is a pixel block of 1 column × 4 rows indicated by 59b.

In the present driving method, the horizontal resolution is doubled as compared with the above-mentioned driving method, and an image with a sense of resolution can be obtained.

A third driving method using the circuit configuration of this example will be described below with reference to FIG.

As shown in FIG. 11, in an odd field, a start pulse 41 and a clock pulse 4
2 and 43 are activated to drive the first vertical shift register 28, and the start pulse 44 and the clock pulses 45 and 46 are activated to activate the second vertical shift register 29.
Drive.

In the even-numbered field, the start pulse 47 and the clock pulses 48 and 49 are operated to set the third pulse.
And the fourth vertical shift register 31 is driven by activating the start pulse 50 and the clock pulses 51 and 52. That is, here, the interlaced (interlaced scanning) drive is performed. FIG. 12 shows the state of the signal polarity in this case. Here, 57 is a pixel written with a positive polarity, and 58 is a pixel written with a negative polarity.

The driving of the horizontal shift register is performed in the first manner described above.
In the case of the same phase as in the driving method described above, the same data is written in the pixel block 59c of 2 columns × 2 rows shown in FIG.

The driving of the horizontal shift register is performed in the second
When the phase is shifted by 1/4 as in the driving method of FIG.
The same data is written in the pixel block 59d of 1 column × 2 rows shown in FIG.

When this driving method is employed, the amount of image information in each field becomes twice as large in the horizontal direction as compared with the case where data is written in the four rows described above, so that the horizontal resolution can be improved.

Embodiment 2 An example of a liquid crystal display using the liquid crystal panel 1 having the structure shown in FIG. 13 will be described. The liquid crystal panel having the configuration shown in FIG. 13 generally has the horizontal shift register 25 and the sample holder 27 removed from the liquid crystal panel shown in FIG. The holder 61 is provided. Here, the horizontal shift register 60 is configured to select all signal lines.

The description of the same components as those of the liquid crystal panel shown in FIG. 5 is omitted here. FIG. 14 shows an equivalent circuit diagram of the sample holder 61. In FIG. 14, reference numeral 62 denotes a switching transistor. The horizontal shift register 60 is driven at twice the frequency of the horizontal shift registers 24 and 25 shown in FIG. 5 to select all signal lines. The switching transistors 62 are alternately connected to the video signal input terminals 8 and 9 of the liquid crystal panel. Therefore, by driving the horizontal shift register 60, the switching transistors 62 are sequentially selected, the video signal of the video signal input terminal 8 is sent to the signal lines of the 2n-1 columns, and the video signal is sent to the signal lines of the 2n columns. Signal input terminal 9
Is sent. Thus, signals of opposite polarities are written to pixels connected to adjacent signal lines.

Also in this embodiment, it goes without saying that the vertical shift register can be driven by both the method of writing in the four rows shown in FIG. 7 and the interlaced scanning shown in FIG. 11 in the first embodiment. The signal polarity states on the panel in each case are the same as those shown in FIG. 10B and FIG.

In the liquid crystal display device of this embodiment, since the number of the horizontal shift register and the number of the sample holders are each one, the circuit scale is reduced, and the liquid crystal panel can be downsized, the yield can be improved, and the cost can be reduced. is there.

Embodiment 3 An example of a liquid crystal display using the liquid crystal panel 1 having the structure shown in FIG. 15 will be described. In the liquid crystal panel having the configuration shown in FIG. 15, the vertical shift register 30 and the vertical shift register 31 are generally removed from the liquid crystal panel shown in FIG. 5, and vertical shift registers 63 and 64 are provided instead of the vertical shift registers 28 and 29. It is configured.

The vertical shift register 63 is a first vertical shift register for selecting 2m-1 rows, and the vertical shift register 64 is a second vertical shift register for selecting 2m rows. 65 is a start pulse VST1, 66 and 67 of the first vertical shift register 63 are clock pulses VCK1 and -VCK1 of the first vertical shift register 63.
It is. Reference numeral 68 denotes a start pulse VST2 of the second vertical shift register 64, and reference numerals 69 and 70 denote clock pulses VCK2 and -VCK2 of the second vertical shift register 64.

The vertical shift registers 63 and 64 correspond to the vertical shift registers 28 and 2 in the first and second embodiments.
Unlike the states 9, 30, and 31, the states of the respective clock pulses 66, 67, 69, and 70 are High / Low.
It is configured to scan sequentially each time it switches.

FIG. 16 is a timing chart. Here, the first vertical shift register 63 and the second vertical shift register 64 are driven in the same phase. That is, the first
The start pulse 65 of the vertical shift register 63 and the start pulse 68 of the second vertical shift register 64 are generated at the same timing and can be shared. Further, the clock pulses 66 and 67 of the first vertical shift register 63 and the clock pulses 69 and 70 of the second vertical shift register 64 are generated at the same timing, and these can be shared. .

In the even field, all clocks are driven with a half cycle phase delayed from the odd field.

That is, in this case, the signals written to the pixels are shifted down by one stage. Thereby, the vertical resolution can be improved.

When this driving method is used, the same data is written in a pixel block of 2 columns × 4 rows, and pixels adjacent in the horizontal direction have opposite polarities. The vertical direction has a reverse polarity every two pixels.

FIG. 17 shows the state of the signal polarity written on the panel. In FIG. 17, 57 indicates a pixel written with a positive polarity, and 58 indicates a pixel written with a negative polarity. 59e is an area where the same data is written. In this example, similarly to the second driving method shown in the first embodiment, the start pulse 35 and the clock pulses 36 and 37 of the first horizontal shift register 24 correspond to the start pulse and the second pulse of the second horizontal shift register. As shown in FIGS. 38b, 39b and 49b, the clock pulse
By delaying the / 4 cycle phase, the horizontal resolution can be doubled. FIG. 18 shows the state of the signal polarity written on the panel at this time. The area in which the same data is written is a pixel block of 1 column × 4 rows indicated by 59f, and a video with a higher resolution can be obtained.
57 indicates a pixel written with a positive polarity, and 58 indicates a pixel written with a negative polarity.

In this example, the vertical shift register is 4
By changing from two to two, the circuit scale is reduced. For this reason, there are the effects that the size of the liquid crystal panel can be reduced, the yield can be improved, and the manufacturing cost can be reduced.

Embodiment 4 An example of a liquid crystal display device using the liquid crystal panel 1 having the structure shown in FIG. 19 will be described. The liquid crystal panel shown in FIG. 19 is configured by combining the liquid crystal panel shown in the second embodiment and the liquid crystal panel shown in the third embodiment. That is, the liquid crystal panel shown in FIG. 19 uses the horizontal shift register 60 and the sample holder 61 shown in FIG. 13 as the horizontal shift register and the sample holder, and uses the vertical shift register 6 shown in FIG.
3 and 64.

The state of the signal polarity written on the panel of this embodiment is the same as that shown in FIG.

The liquid crystal panel of this embodiment has one horizontal shift register and one sample holder, and has four or two vertical shift registers, so that the circuit scale is the smallest in the embodiment of the present invention. . That is, there is an effect that the size of the liquid crystal panel can be reduced, the yield can be improved, and the cost can be reduced at a high level.

Fifth Embodiment In the first to fourth embodiments described above, in order to display the effective video signal period on the entire screen as shown in FIG. 3, for example, an NTSC signal is displayed on a high-vision liquid crystal panel. In the case shown in FIG.
As shown in the figure, the image extends in the horizontal direction.

In this example, a liquid crystal display device in which such an image does not expand in the horizontal direction will be described.

In this embodiment, the double-speed scan converter 4 shown in FIG. 1 is configured as shown in FIG.

In FIG. 21, reference numeral 71 denotes a first A / D converter, 72 denotes a second A / D converter, 73 denotes a first line memory, and 74 denotes a second line memory. 75
Is a first DA converter, 76 is a second DA converter, and 77 and 78 are analog switches. 79 and 80 are write clocks from the timing generator 6, 81 and 82 are similarly write resets, 83 and 8
4 is a read clock. 85 and 86 are read resets, 87 is an analog switch control pulse, 88 and 8
Reference numeral 9 denotes output data of the AD converters 71 and 72. 90 and 91 are output data of the line memories 73 and 74.

FIG. 22 shows a timing chart. First
Is driven by the write clock 79 during the nH period, and sequentially transfers data to the first line memory 73. On the other hand, the second AD converter 72 has been reset by the write reset 82 during the nH period, and the second line memory 74 has a reset level (Lo).
w level) signal is input. First line memory 73
The read clock 83 of the first embodiment is delayed by a half phase, as shown in the timing charts of FIGS.
Although the data is read out, for example, when a 4: 3 NTSC signal is displayed on a 16: 9 Hi-Vision panel for aspect ratio conversion, it is compressed to 3/4 in the horizontal direction as shown in FIG. The frequency of the read clock 83 must be 8/3 times that of the write clock 79 in order to display the image with the aspect ratio kept at 1: 1. The read reset 85 is in a reset state except during the period in which the write clock 79 is driven, and a reset level (Low level) signal is input to the first DA converter 75.

The second A / D converter 72 has a function of (n +
1) Driven by the write clock 80 in the same manner as described above during the H period, sequentially transfers data to the second line memory 74, and is delayed by a 1/2 phase with a read clock 84 having a frequency 8/3 times the frequency of the write clock 80. Read the data twice. The read reset 86 is in a reset state except during a period in which the write clock 80 is being driven, and a reset level (Low level) signal is input to the second DA converter 76.

The video signals converted into analog signals from the DA converters 75 and 76 in this manner are output alternately. The analog switches 77 and 78 are alternately turned ON / OFF by a control pulse 87 and output as the output signal 14c of the double-speed scan converter 4. The output signal is compressed to 3/4 in the horizontal direction for aspect ratio conversion, and a non-image portion 92 occurs during the effective video period. Therefore, by setting the start pulse of the horizontal shift register of the liquid crystal panel 1 to the center of the non-image portion 92 as shown in FIG. 22, a display having non-image portions at both left and right ends of the screen as shown in FIG. can do.

[0070]

As described above, according to the liquid crystal display device of the present invention, a liquid crystal display panel for displaying an image based on a high definition television signal has a small number of scanning lines and a low signal band television. An image based on a television signal, for example, a television signal of the current system, can be displayed on the entire surface of the liquid crystal display panel by writing a video signal written to one pixel to a plurality of pixels.

When the video signals written to the adjacent pixels in the vertical and horizontal directions are written in opposite polarities with respect to the potential of the counter substrate electrode, the spatial frequency of flicker (blinking) rises dramatically, A display with a sense of resolution is provided, and an image display that is easy to see and does not cause the observer to feel tired is possible.

When two sets of digital sampling means of the double-speed scan converter are provided and the output is alternately selected every one horizontal period, a uniform non-signal is displayed on the non-image portion. In addition, even in liquid crystal panels having different aspect ratios, an image can be displayed without changing the aspect ratio of the current image.

[Brief description of the drawings]

FIG. 1 is a block diagram schematically showing one example of a liquid crystal display device of the present invention.

FIG. 2 is a block diagram showing an example of a double-speed scan converter applicable to the liquid crystal display device of the present invention.

FIG. 3 is a timing chart according to a double-speed scan converter.

FIG. 4 is a timing chart related to a double-speed scan converter and a video driver.

FIG. 5 is a schematic diagram showing one example of a liquid crystal panel constituting the liquid crystal display device of the present invention.

FIG. 6 is a timing chart of a horizontal shift register according to the liquid crystal panel.

FIG. 7 is a timing chart of a vertical shift register according to the liquid crystal panel.

FIG. 8 is an equivalent circuit diagram of a pixel portion of a liquid crystal panel.

FIG. 9 shows a signal polarity 1 written to a pixel of a liquid crystal panel.
It is a schematic diagram which shows an example.

FIG. 10 is a schematic diagram illustrating an example of signal polarities written to pixels of a liquid crystal panel.

FIG. 11 is a timing chart of a vertical shift register according to a liquid crystal panel.

FIG. 12 is a schematic diagram illustrating an example of a signal polarity written to a pixel of a liquid crystal panel.

FIG. 13 is a schematic view illustrating an example of a liquid crystal panel.

FIG. 14 is an equivalent circuit diagram of a sample holder according to the liquid crystal panel.

FIG. 15 is a schematic diagram illustrating an example of a liquid crystal panel.

FIG. 16 is a timing chart of the vertical shift register according to the liquid crystal panel.

FIG. 17 is a schematic diagram illustrating an example of signal polarities written to pixels of a liquid crystal panel.

FIG. 18 is a schematic diagram illustrating an example of a signal polarity written to a pixel of a liquid crystal panel.

FIG. 19 is a schematic view showing one example of a liquid crystal panel.

FIG. 20 is a schematic diagram showing a screen example when displaying an image on liquid crystal panels having different aspect ratios.

FIG. 21 is a schematic diagram illustrating an example of a double-speed scan converter.

FIG. 22 is a timing chart according to a double-speed scan converter.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Liquid crystal panel 2 Video signal input terminal 3 Synchronization separation circuit 3a Synchronized and separated video signal 4 Double speed scan converter 5 Video driver 6 Timing generator 7 Inverting amplifier 8 Liquid crystal panel signal input terminal 9 Liquid crystal panel signal input terminal 10 Synchronization signal 11 Polarity inversion Pulse 12 Control clock 13 Liquid crystal panel drive pulse 14a-c Double-speed converted video signal 15 A / D converter 16 Line memory 17 DA converter 18 Write clock 19 Write reset 20 Read clock 21 Read reset 22 A / D converter output data 23 line memory output data 24 first horizontal shift register 25 second horizontal shift register 26 first sample holder 27 second sample holder 28 first vertical shift register 29 second vertical Shift register 30 third vertical shift register 31 fourth vertical shift register 32 signal line 33 scanning line 34 pixel electrode 35 start pulse HST1 36 clock pulse HCK1 37 clock pulse-HCK1 38a-b start pulse HST2 39a-b clock pulse HCK2 40a-b Clock pulse -HCK2 41 Start pulse VST1 42 Clock pulse VCK1 43 Clock pulse -VCK1 44 Start pulse VST2 45 Clock pulse VCK2 46 Clock pulse -VCK2 47 Start pulse VST3 48 Clock pulse VCK3 49 Clock pulse -VCK350 Start pulse 51 clock pulse VCK4 52 clock pulse-VCK4 53 TFT 54 liquid crystal 55 storage capacitance 5 Opposite base electrode 57 Pixel written with positive polarity 58 Pixel written with negative polarity 59a-f Area where same data is written 60 Horizontal shift register 61 Sample holder 62 Switching transistor 63 First vertical shift register 64 Second Vertical shift register 65 Start pulse VST1 66 Clock pulse VCK1 67 Clock pulse-VCK1 68 Start pulse VST2 69 Clock pulse VCK2 69 Clock pulse VCK2 70 Clock pulse-VCK2 71 First A / D converter 72 Second A / D converter 73 1st line memory 74 2nd line memory 75 1st DA converter 76 2nd DA converter 77 1st analog switch 78 2nd analog switch 79 1st line Clock 80 second write clock 81 first write reset 82 second write reset 83 first read clock 84 second read clock 85 first read reset 86 first read reset 87 analog switch control pulse 88 1st A / D converter output data 89 1st A / D converter output data 90 1st line memory output data 91 2nd line memory output data 92 No picture part 93 Horizontal shift register start pulse

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-5-341733 (JP, A) JP-A-5-83658 (JP, A) JP-A-5-1558437 (JP, A) JP-A-2- 308686 (JP, A) JP-A-4-260286 (JP, A) JP-A-3-98392 (JP, A) JP-A-3-43697 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) G09G 3/00-3/38 G02F 1/133 505-580 H04N 5/66-5/74

Claims (3)

(57) [Claims] 1. A liquid crystal panel sandwiching liquid crystal between a substrate provided with a plurality of pixel electrodes and a counter substrate provided with a counter electrode facing the substrate, wherein an image is formed based on a high definition television signal. A liquid crystal display device that displays an image based on a television signal having a smaller number of scanning lines than the number of scanning lines of the liquid crystal panel that displays an image according to the high-vision method. based on the television signal of a small number of scheme has to be written to pixels corresponding to data of the pixels corresponding to one of said plurality of pixel electrodes on the other pixel electrode, a
Samples analog video signals and converts them to digital signals.
First and second A / D converters for switching,
The first and second lines for storing the horizontal signal for one horizontal scanning line
Memory and the digital signal stored in the line memory.
First and second DAs for converting a signal into an analog video signal
Sets of digital video signal storage having a converter
And the output signal of each digital video signal storage device.
First and second analog switches that alternately select
Wherein the line memory is adapted to write and read data.
Can be performed independently and asynchronously,
Write data to line memory for one horizontal period of video signal
Driving alternately every time, reading data from the line memory
Is delayed by a half horizontal period with respect to the writing to 2
Drive, and alternately select and output by the analog switch.
A liquid crystal display device comprising: a double-speed scan converter for driving . 2. The polarity of data of a pixel corresponding to one of the plurality of pixel electrodes and data written to a pixel located in a vertical direction or a horizontal direction adjacent to the pixel is applied to the counter electrode. the liquid crystal display device according to claim 1 which is opposite polarities about the voltage. 3. The liquid crystal panel is 4m-3, 4m-2,
2. The liquid crystal display device according to claim 1, comprising four vertical shift registers for respectively selecting 4m-1 and 4m rows.