JPH075732Y2 - Liquid crystal display data processing circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention relates to a liquid crystal display data processing circuit for processing display data to a liquid crystal display unit.

[Prior Art and Problems to be Solved] Conventionally, in a liquid crystal television or other time-division drive type digital display device, an analog video signal is converted into digital data of several bits, for example, 3 to 4 bits, and based on this digital data. A gradation signal is created to drive the liquid crystal display panel for display. Although the number of gradations of a display image can be increased by increasing the number of bits of the digital data, there is a problem that the display driving circuit becomes complicated when the number of bits of the digital data is increased. Therefore, conventionally, as shown in FIG. 4, one display period is divided into two periods T1 and T2, and the effective sampling level of A / D conversion in each divided period T1 and T2 is made different,
The same number of gradations as when the digital data is apparently increased by 1 bit is obtained. FIG. 4 shows an example of converting an analog signal into 3-bit digital data. In the above method, when the periods T1 and T2 are switched, conventionally, it is performed in the vertical direction and the time axis direction of the display screen as shown in FIG. That is,
As shown in FIG. 5 (a), a field n having a display screen is displayed.
Then, the odd-numbered lines L1, L2, ... Of the horizontal scanning lines are display-driven with the data of the above period T1, and the even-numbered lines L2, L4 ,.
On the other hand, the display is driven by the data in the period T2. Then, in the next field n + 1, as shown in FIG. 5 (b), the display drive is performed for the odd lines L1, L2, ... With the data of the above period T2, and for the even lines L2, L4 ,. Display drive with the data of. Hereinafter, similar display control is repeated.

However, when the display screens are switched only in the vertical direction and the time axis direction as described above, a part that should have the same gradation depending on the contents of the screen has different gradations as the object moves. turn into. Further, there is a problem that the switching signal for switching the periods T1 and T2 is easily affected by noise. That is, since the switching between the T1 period and the T2 period is performed for each horizontal line, when the timing of the switching signal is shifted due to the influence of noise, the period T1 or the period
The display data processed in T2 will be continuous for two lines, and it is very likely to be perceived as noise.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a liquid crystal display data processing circuit which can improve reproducibility with respect to an image signal and is hardly affected by noise.

[Means and Actions for Solving the Problem] The present invention processes digital display data to a liquid crystal display unit and performs addition processing of the least significant bit and other bits in n-bit display data to obtain n-1. In a liquid crystal display data processing circuit that creates bit display data and obtains the same gradation signal as the n-bit display data, the above addition processing is performed every other pixel and the addition timing is inverted every horizontal line, Further, the inversion timing is configured to be inverted for each field.

With the above configuration, the display data creation timing of n-1 bits is switched for each pixel, for each horizontal line, and for each field to obtain averaged display data for the entire display screen. Even with 1-bit display data, gradation expression with higher reproducibility is possible.

[Embodiment] An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a liquid crystal display data processing drive circuit 10 according to the present invention. In the figure, reference numeral 11 denotes an A / D conversion circuit. The analog video signal a is input to the input terminal A _IN and the sampling clock φs is input to the clock terminal CK. The A / D conversion circuit 11 converts the analog video signal a input to the input terminal A _IN into 4-bit digital data D1 to D4 in synchronization with the sampling clock φs and inputs the data D1 to the AND circuit 12. And add the data D2 to D4
It is inputted to the input terminals A2 to A4 of 14 and also inputted to the AND circuit 12 through the NAND circuit 13.

The sampling clock φs is input to the clock terminal CK of the D flip-flop 15. In the flip-flop 15, the horizontal synchronizing signal H-Sy or the composite synchronizing signal C-Sy is input to the reset terminal, the Q-side output is input to its own input terminal D, and the Q-side output is the exclusive OR circuit. (Hereinafter abbreviated as EX OR circuit) 16 is input. This EX OR circuit 16 also has a horizontal timing signal CK.
H and the vertical timing signal CKV are input via the EX OR circuit 17. The horizontal timing signal CKH is a signal whose signal level alternates between a high level and a low level every horizontal period, and the vertical timing signal CKV has a signal level of a high level and a low level for each field (one screen). This signal alternates. And the above EX OR circuit 16
Is output to the AND circuit 12 as a data switching signal, and the output signal of the AND circuit 12 is input to the input terminal B2 of the adder 14. Further, a low-level (“0”) signal L is applied to the carry input terminal C0 and the data input terminals B1, B3, B4, A1 of the adder 14. This adder 14
The input signals of the input terminals A1 to A4 and the input signals of the output terminals B1 to B4 are added together and output from the output terminals Σ1 to Σ4. Of the output terminals Σ1 to Σ4, the signals output from Σ2 to Σ4 are sent to the liquid crystal display section (not shown) as digital data DA1 to DA3.

Next, the operation of the above embodiment will be described. The A / D conversion circuit 11
The analog video signal a supplied to the input terminal A _IN is sampled in synchronization with the sampling clock φs, converted into 4-bit digital data D1 to D4, and the data D2 to D3 are output to the adder 14. The data D2 to D4 are input to the AND circuit 12 via the NAND circuit 13, and the data D is directly input to the AND circuit 12. This AND circuit 12 is 1V
Gated by vertical timing signal CKV which inverts every period, horizontal timing signal CKH which inverts every 1H period, sampling clock φs, and A / D accordingly
The data D1 from the conversion circuit 11 is output to the adder 14. now,
For example, vertical timing signal CKV and horizontal timing signal C
If both KH are “0”, the output signal of the EX OR circuit 17 becomes “0” and is input to the EX OR circuit 16. Also this
The signal level of the Q-side output signal of the flip-flop 15 input to the EX OR circuit 16 is inverted every time the timing clock φs is applied. Therefore, when the output signal of the EX OR circuit 17 is "0", the Q side output signal of the flip-flop 15 becomes the output signal of the EX OR circuit 16 as it is and the AND circuit.
Entered in 12. The AND circuit 12 is gate-controlled by a signal sent from the flip-flop 15 via the EX OR circuit 16 and outputs the data D output from the A / D conversion circuit 11.
Add 1 to every 1 cycle of sampling clock φs 14
Transfer to. When the data D2 to D4 output from the A / D conversion circuit 11 are all “1”, the output of the NAND circuit 13 becomes “0” and the gate of the AND circuit 12 is closed, and the data D1 is It is prohibited to be sent to the adder 14. Above adder 14
When the data D1 is sent via the AND circuit 12, the data D1 is added to the lower bit D2 of the data D2 to D4,
When the input of data D1 is prohibited, adder 14
The data D2 to D4 from is output as it is as the data DA1 to DA3 from the output terminals Σ2 to Σ4.

FIG. 2 shows the data D1 output from the A / D conversion circuit 11 described above.
~ D4 and the data DA1 ~ DA3 output from the adder 14 is shown.

As a result of the gate control for the AND circuit 12, the horizontal line L1 is scanned (the horizontal timing signal CKH is "0") in a certain field n (the vertical timing signal CKV is "0") as shown in FIG. 0 "), for example, the data D1 is added to the odd-numbered bits indicated by diagonal lines, and the data D1 is not added to the other even-numbered bits.

Then, in the field n, when the horizontal scanning line moves to the next line L2 and the horizontal timing signal CKH becomes "1", the output signal of the EX OR circuit 17 becomes "1" and is input to the EX OR circuit 16. . As a result, the Q side output signal of the flip-flop 15 is inverted and output from the EX OR circuit 17, and input to the AND circuit 12 for gate control. Therefore, the transfer timing of the data D1 sent from the A / D conversion circuit 11 to the adder 14 is shifted by one pixel as compared with the case of the horizontal line L1, and the addition by the adder 14 is performed accordingly. That is, as shown in FIG. 3A, the addition timing of the data D2 to D4 and D1 in the horizontal lines L1 and L2 is shifted by one pixel, and the addition is performed in the horizontal line L2 when the horizontal line L1 is not added. The operation is performed.

Further, when the horizontal scanning line is moved to the next line L3, the horizontal timing signal CKH returns to the level of "0", so that the adder 14
The addition timing of is the same as that of the horizontal line L1. Thereafter, the same operation is alternately repeated for each horizontal line.

When the scan for the field n is completed and the scan for the next field n + 1 is started, the vertical timing signal
CKV switches to "1" level. Therefore, the EX OR circuit 17 inverts the horizontal timing signal CKH and outputs it.
Input to the OR circuit 16. As a result, this field n
At +1, the addition timing of the data D1 with respect to the data D2 to D4 of the adder 14 is the odd line L1, L3, ... And the even line L2, L4, ... With respect to the field n as shown in FIG. 3 (b). It is the timing to replace.

Similarly, for each field, the above-mentioned FIG. 3 (a),
The adding operation of the timing shown in (b) is alternately repeated.

Data D2 to D output from the A / D conversion circuit 11 as described above
The addition operation of 4 and the data D1 is performed every other pixel, the addition timing is inverted every horizontal line, and the addition timing is inverted every one field, that is, the time It is reversed in the axial direction. As a result, the addition switching frequency in the adder 14 becomes higher, and the addition processing is performed evenly on the entire screen, and the reproducibility for the video signal is improved.

[Advantages of the Invention] As described above in detail, according to the present invention, the digital display data to the liquid crystal display unit is processed, and the least significant bit and other bits in the n-bit display data are added to perform n processing. In a liquid crystal display data processing circuit that creates -1 bit display data and obtains the same gradation signal as the n bit display data, the above addition processing is performed every other pixel and the addition timing is inverted every horizontal line. Further, since the inversion timing is controlled to be inverted for each field, the entire display screen is divided in units of one pixel to switch the display data, and even n-1 bit display data can be displayed. It is possible to perform gradation expression with high reproducibility. Since the above-mentioned addition process is performed every other pixel, even if noise is mixed in the timing signal for switching the addition operation, the timing of the addition operation in the horizontal line in which the noise is mixed is shifted by one pixel. Is unlikely to be felt as.

[Brief description of drawings]

1 to 3 show an embodiment of the present invention.
FIG. 1 is a block diagram showing a circuit configuration, and FIG. 2 is a diagram showing a relationship between A / D-converted n-bit data and n-1 bit output data after addition processing, FIG. 3 (a). , (B) are views showing the division operation of the display data, and FIGS. 4 and 5 are views for explaining the division operation of the display data in the conventional circuit. 11 ... A / D conversion circuit, 14 ... Adder, 15 ... Flip-flop, 16, 17 ... Exclusive OR circuit (EX OR circuit).

Claims (1)

[Scope of utility model registration request] 1. A liquid crystal display data processing circuit for processing display data to a liquid crystal display unit, which converts an analog video signal into n-bit digital data in synchronization with a sampling clock, and the A / D conversion circuit. Adding means for adding the least significant bit and other bits in the output data of the D conversion circuit and outputting as n-1 bit digital data;
A gate circuit provided between the least significant output bit of the A / D conversion circuit and the adding means, a gate control means for alternately turning on / off the gate circuit in synchronization with the sampling clock, and the gate control First inversion control means for inverting the output signal of the means for each horizontal scanning line of the liquid crystal display section, and alternately controlling the output signal of the first inversion control means for each field of the liquid crystal display section. A second liquid crystal display data processing circuit, comprising: