JPH08160911A - Multigradation display pdp - Google Patents

Abstract

PURPOSE: To double the number of display gradations by a simple method without dropping luminance at the time of displaying videos having a halftone gradation on a PDP of a lighting pulse number modulation system. CONSTITUTION: The number of the display gradations is doubled by making combination use of a so-called area modulation system displaying the video for one pixel-component by using two pixels with the PDP 4. A display video signal S0 is formed as an NTSC signal and the PDP 4 is formed as the PDP of 640 pixels in a horizontal direction and 480 pixels in a perpendicular direction. The one pixel is displayed by using the two pixels of only the horizontal direction. The PDP 4 is used as 64 gradations display and 127 gradations are displayed by displaying the one pixel by using the two pixels in the horizontal direction. The video signals to be displayed are digitalized to 7-bit by an AD converter 1 and the upper 6-bit is converted into the one pixel and the 6-bit added with LSB 1-bit by an adder 2 is changed over to the pixel adjacent thereto and these pixels are displayed by a multiplexer 3. The one pixel is displayed by the two pixels, by which 127 gradations are obtd.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-gradation display PDP for displaying an image having a half tone such as an NTSC video signal on a PDP (plasma display panel) in multi-gradation.

[0002]

2. Description of the Related Art Generally, halftone display on a PDP employs a so-called lighting pulse number modulation method in which the number of times each pixel is turned on is modulated by a display video signal. In this method, there is a trade-off relationship between the number of display gradations and the brightness, and in the PDP currently put into practical use, the number of display gradations is 64 in order to secure the display brightness.
There was a lack of gradation. Although there is an error diffusion method or the like as a method for improving this, there is a problem such as a large increase in required hardware. The number of pixels in the horizontal direction is 640
When displaying the image of NTSC signal on the PDP of the pixel,
Since the video signal band is about 4 MHz, it was substantially oversampled.

[0003]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and provides a means for easily performing multi-gradation display without lowering the display brightness of a PDP.

[0004]

In a PDP (plasma display panel) of a lighting pulse number modulation method, a so-called area modulation method of displaying an image for one pixel by using two pixels is also used to display the number of display gradations. Double.

The video signal is an NTSC signal, the PDP is a PDP having 640 pixels in the horizontal direction and 480 pixels in the vertical direction, and one pixel is displayed by using two pixels only in the horizontal direction.

The PDP has a 64-gradation display, and 127 pixels are displayed by displaying one pixel by using two pixels in the horizontal direction.

The video signal to be displayed is digitized with an arbitrary number of bits N bits corresponding to the number of display gradations, and the upper N-1 bits are converted into one pixel and the LSB is converted into N-1 bits.
A pixel to which 1 bit is added is displayed on the pixel next to it, and one pixel is displayed by 2 pixels to display a gradation of N bits.

The video signal to be displayed is digitized into 7 bits, and the upper 6 bits are converted into one pixel.
A bit obtained by adding 1 bit of LSB to the adjacent pixel is displayed, and one pixel is displayed with two pixels to obtain 127 gradations.

When a video signal from a television or the like and a video signal from a personal computer are switched and displayed, when displaying a personal computer image, halftone is expressed only by the number of times of lighting, and when displaying a video signal, there are two An image for one pixel is displayed by using the pixel, and the number of display gradations is doubled. Each of these display modes is switched and displayed according to an input signal.

[0010]

By using the area modulation method together, the display gradation can be doubled without lowering the display brightness.
N in a PDP with 640 pixels in the horizontal direction and 480 pixels in the vertical direction
When a TSC video signal is displayed, the horizontal direction is oversampled. By displaying one pixel with only two pixels in the horizontal direction, there is almost no deterioration in resolution and the lack of gradation display is doubled. Can be Furthermore, 64 gradations with the lighting pulse number modulation method and 127 with the area modulation method
The gray scale display makes it possible to obtain a display device in which display brightness, resolution, and the number of gray scales are balanced in the NTSC system. In addition, the video signal to be displayed is digitized with 7 bits, and the upper bits 6 bits, that is, the input signal S0 / 2.
Display the signal obtained by adding the LSB 1 bit to the upper 6 bits, that is, the sum of the input signal S0 / 2 and the remaining integer (0 or 1) to the pixel next to it Thus, the brightness of the two pixels is S0 / 2 + S0 / 2 + residual = S0, and the maximum number of display gradations is 63 + 63 = 1.
26, that is, 127 gradations from 0 to 126 gradations can be displayed. When displaying an image from a personal computer, the number of display pixels of the personal computer can be secured by performing gradation display only with the lighting pulse number modulation method.

[0011]

Embodiments of the multi-gradation display PDP according to the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram of a main part of a multi-gradation display PDP according to the present invention. Here, 1 is a 7-bit AD (analog digital) converter, 2 is a 6-bit adder, 3 is a multiplexer, 4 is a PDP, and 5 is a 1/2 counter. The PDP 4 has 640 pixels in the horizontal direction, 480 pixels in the vertical direction, and a display gradation of 64 gradations in the lighting pulse number modulation method. Further, S0 is an input video signal, S1 is a high-order 6-bit signal of a digital video signal,
S2 is the LSB 1-bit signal of the same digital video signal, S
3 is a sum signal obtained by adding the 6-bit signal S1 and the LSB signal S2, and S4 is a clock signal C1 obtained by adding the 6-bit signals S1 and S3.
Is a 6-bit video signal for driving the PDP sequentially switched by the multiplexer 3, C0 is a display clock signal of the PDP, and C1 is a clock having a half frequency thereof. Figure 2
FIG. 4 is a timing diagram of the main signal. FIG. 3 is a schematic view of a pixel array of the PDP according to the present invention. 31, 32,
.. indicates one pixel in video display, and is composed of two pixels such as pixels 31a and 31b which are the original three RGB primary colors of the PDP.

The input video signal (analog) S0 is input to the AD converter 1, and a 7-bit digital video signal S1 is generated by a clock C1 having a frequency half that of the display clock C0.
(Upper 6 bits) and S2 (LSB 1 bit). The 6-bit video signal S1 and the LSB 1 bit are input to the adder 2 to obtain the sum signal S3. The 6-bit video signals S1 and S3 are input to the multiplexer 3 and the clock signal C is input.
The output signal S4, which is the drive signal for the PDP, is obtained by switching at 1. Switching by the multiplexer 3 is assumed that when the clock C1 is 1, the signal S1 is selected, and when the clock C1 is 0, the signal S3 is selected and output as the signal S4.
The signals at the timings 1a, 1b, 2a, 2b, ... Of 0 are pixels 31a, 31b, 32a, 32b ,.
If it is driven corresponding to each, C at time 1a
Since 1 is 1, the signal S1 is selected and displayed on the pixel 31a, and at the time point 1b, the signal S3 is selected and displayed on the pixel 31b. In this way, in the pixel 1 as a whole, the input signal S0
Accordingly, a display of 127 gradations is obtained. The above configuration is RG
A full color display PDP can be obtained by providing three sets as shown by RGB in FIG. 1 corresponding to the B3 primary colors.

FIG. 4 is a block diagram of a main part of another embodiment of the present invention. Here, 1 is a 7-bit AD (analog-digital) converter, 2 is a 6-bit adder, 3 is a multiplexer, 4 is a PDP, 5 is a 1/2 counter, W1 is a switcher between a video signal and a personal computer signal, W2 and W3. Is a switch for the clock for video signals and the clock for personal computer signals.
The PDP 4 has 640 pixels in the horizontal direction and 480 pixels in the vertical direction.
The display gradation in the lighting pulse number modulation method is 64 gradations.
Further, S5 is a video signal, S6 is a personal computer signal, S0 is a display video signal, S1 is the upper 6-bit signal of the digital video signal, S2 is the LSB 1-bit signal of the digital video signal, and S3 is the 6-bit signal S1 and LSB signal S2. The added sum signal, S4 is a 6-bit video signal that drives the PDP 4 with the output of the multiplexer 3, C5 is a video / PC switching signal, C0 is a display clock signal of the PDP, and C1
Is a clock signal for displaying a video signal having a frequency of 1/2 of C0, C2 is a clock signal for an AD converter, C3 is a multiplexer switching signal which is always 1 when displaying a personal computer, and C4 is a multiplexer switching signal. Is.

Using the switch 6, the input switching signal C5
Switching between video signal S5 and personal computer signal S6 with AD
While selecting the input video signal S0 of the converter, the switching device 7
Is used to switch the clock signal C1 of the AD converter to the same frequency as the PDP drive clock when the personal computer signal is selected, and to half the frequency when the video signal is selected. Further, the switching signal C4 of the multiplexer 3 using the switching device 8 uses the clock signal C1 when the video signal is selected and is always set to 1 when the personal computer signal is selected so that the upper 6 bits of the output of the AD converter 1 are always selected. To By doing so, when a video signal is selected, one pixel is displayed with two pixels as in the above case, and 127 gradations are displayed, and when a PC signal is selected, the previous pixel of 640 × 480 pixels is displayed. Display is obtained.

In the above embodiments, the number of pixels and the number of gradations are limited, but the present invention is not limited to this, and it goes without saying that any number of pixels and gradations can be applied.

[0016]

By using the area modulation method together, the display gradation can be doubled without lowering the display brightness. PD with horizontal 640 pixels and vertical 480 pixels
When an NTSC video signal is displayed in P, the horizontal direction is oversampled. By displaying one pixel with only two horizontal pixels, there is almost no deterioration in resolution and there is insufficient gradation display. It can be doubled. Further, by displaying 64 gradations by the lighting pulse number modulation method and 127 gradations by using the area modulation method together, it is possible to obtain a display device in which the display brightness, resolution, and the number of gradations are balanced in the NTSC method. In addition, the video signal to be displayed is digitized with N bits, and the upper N-1 bits and the sum signal of the LSB 1 bit in the N-1 bits are displayed on the adjacent pixels, respectively, which simplifies the configuration and the display gradation. It can be doubled. When switching between the PC signal and the video signal for display, the display is switched by the input switching signal, and when displaying the image from the PC, the gradation is displayed only by the lighting pulse number modulation method. You can secure the number.

[Brief description of drawings]

FIG. 1 is a block diagram of a main part of an embodiment according to the present invention.

FIG. 2 is a timing diagram of the main signals of one embodiment according to the present invention.

FIG. 3 is a schematic diagram of a pixel array of a PDP according to an embodiment of the present invention.

FIG. 4 is a block diagram of a main part of another embodiment according to the present invention.

[Explanation of symbols]

 1 AD (Analog Digital) Converter 2 Adder 3 Multiplexer 4 PDP (Plasma Display Panel) 5 1/2 Counter 6 Video Input Switching Device 7 AD Converter Clock Switching Device 8 Multiplexer Switching Signal Switching Device 31, 32, ... PDP Pixel S0 display video signal S1 digital video signal S4 digital video signal C0 PDP display clock signal C1 AD converter clock signal

Claims (6)

[Claims] 1. A PDP (plasma display panel) for displaying an image having a halftone according to the number of times of lighting.
A multi-gradation display PDP characterized by displaying an image for one pixel using two pixels and doubling the number of display gradations. 2. A video signal to be displayed is an NTSC signal,
2. The multi-gradation display PDP according to claim 1, wherein the PDP has 640 pixels in the horizontal direction and 480 pixels in the vertical direction, and an image for one pixel is displayed by using two pixels in the horizontal direction. 3. The halftone displayed by the number of times of lighting is 64 gradation display, and 127 gradations are displayed by displaying one pixel by using two pixels in the horizontal direction. Item 2. A multi-gradation display PDP according to item 2. 4. An analog (digital) converter for converting an analog video signal to be displayed into a digital signal, an adder for summing the digital video signals, and a multiplexer for switching and outputting two digital video signals are provided. N-1 of the converted arbitrary integer N-bit video signal excluding 1 bit of LSB (least significant bit)
Bit and its N-1 bit and LSB 1 bit are added by the adder to obtain an N-1 bit digital video signal,
2. The multi-gradation display PD according to claim 1, wherein one of two pixels is sequentially switched by the multiplexer and supplied to the PDP for display to double the number of display gradations.
P. 5. A 7-bit AD converter (analog-digital converter), an adder that adds a 6-bit signal and a 1-bit signal to obtain a 6-bit sum signal, and a 6-bit signal by switching between two 6-bit signals. , A video signal to be displayed is digitized by the AD converter, and the upper 6 bits, the upper 6 bits and L
A 6-bit signal obtained by adding 1 bit of SB (least significant bit) by the adder is sequentially switched and supplied by the multiplexer corresponding to 1 pixel of 2 pixels so that 127 gradations are displayed. 5. The multi-gradation display PDP according to claim 4, wherein: 6. A video signal to be displayed is displayed by switching between a video signal and a personal computer signal, and the personal computer signal expresses a halftone only by the number of times of lighting, and the video signal corresponds to one pixel by using two pixels. Image is displayed and the number of display gradations is 2
2. The multi-gradation display PDP according to claim 1, wherein the display is switched so as to be doubled.