JP2832962B2 - Halftone display circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a halftone display circuit for performing halftone display using a digital RGB signal that cannot originally display halftone.

[Related Art] Conventionally, a digital RGB signal has been used as a color video signal provided to, for example, a monitor device for a VTR and a display device of a personal computer. However, the digital RGB signals are R (red), G
Since the signal is a 3-bit signal corresponding to (green) and B (blue), only eight primary colors including black can be displayed. Therefore,
At the time of superimposing with a video or the like capable of displaying a halftone, an unnatural feeling was given.

[Problems to be Solved by the Invention] As described above, a display device using a conventional digital RGB signal has a drawback that halftone display cannot be performed.

The present invention has been made in view of such a problem, and has as its object to provide a halftone display circuit capable of performing halftone display using a digital RGB signal.

[Means for Solving the Problems] A halftone display circuit according to the present invention is a serial / parallel converter that converts digital RGB signals input in series by a predetermined number of bits into parallel data corresponding to an intermediate luminance value. And a decoder for decoding parallel data output from the serial / parallel conversion circuit and outputting data for displaying an intermediate luminance value.

[Operation] According to the present invention, a digital RGB signal is grouped into a predetermined number of bits by a serial / parallel conversion circuit, and the collected information is decoded by a decoder and converted into data for displaying an intermediate luminance value. Therefore, for example, if n-bit parallel data can be obtained by a serial / parallel conversion circuit, halftone display of 2 ⁿ gradations for each RGB becomes possible. In this case, the resolution is reduced to 1 / n, but the number of obtained gradations 2 ⁿ
The effect is small compared to.

Example Next, an example of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a configuration of a halftone display circuit according to an embodiment of the present invention.

FIG. 1 shows only the system of the R signal among the digital RGB signals, and the same circuit as that of FIG. 1 is additionally provided as a circuit of the G and B systems.

Digital RGB signals output from a personal computer (not shown) or a VTR or the like are input to 1H delay circuits 1, 2, and 3, respectively, and 1H, 2H, 3H,. Are sequentially delayed. The current input RGB signal and the outputs of these 1H delay circuits 1, 2, and 3 are input to serial / parallel conversion circuits (hereinafter, referred to as S / P conversion circuits) 4, 5, 6, and 7, respectively. The S / P conversion circuit used among the S / P conversion circuits 4 to 7 is selected by the frequency division counter 8. The frequency division counter 8 performs S / P conversion circuits 4 to 7 based on a preset mode control signal (a signal indicating how many digital RGB signals are combined).
Are selected, the frequency of the dot clock is further divided, the number of output bits of each selected S / P conversion circuit is determined, and an S / P conversion load pulse giving the output timing is output. The ROM 9 receives, as an address, a parallel output from the selected S / P conversion circuits 5, 6, ... output with the S / P conversion load pulse, and outputs an intermediate luminance value indicated by the parallel output. Convert to data for display. RO
M9 switches the internal table according to the mode control signal. The output of the ROM 9 is provided to the latch circuit 10. The latch circuit 10 latches data for displaying an intermediate luminance value from the ROM 9 by the divided clock from the frequency dividing counter 8. The D / A converter 11 performs D / A conversion on the data latched by the latch circuit 10 in synchronization with the frequency-divided clock, and outputs the converted output as an analog RGB signal.

In the halftone display circuit configured as described above, consider the case where halftone is expressed by a total of four dots, for example, two horizontal dots and two vertical lines. As shown in FIG. ₂ , if four dots a ₀ , a ₁ , a ₂ , and a ₃ are used, it is possible to digitally express halftones of 2 ⁴ = 16 values. At this time,
The reduction in resolution is halved both horizontally and vertically. First,
The 2 × 2 halftone expression is selected by the mode control signal. The digital RGB signal synchronized with the dot clock is 1 horizontal scanning line period (1H) by the 1H delay circuit 1.
Delay. For example, paying attention to a certain line L, L + 1
The line and the L line are input to the S / P conversion circuits 4 and 5 at the same time. The input signal is 2 at each load pulse timing.
It is output bit by bit, as shown in O _{1 to} O _{4 in} FIG.
It is converted into a 4-bit parallel signal. As shown in FIG. 4, the parallel signal is obtained by collectively extracting 2 × 2 pixels of 2 bits of L line and 2 bits of L + 1 line. In the example of FIG. 4, “0”, “1”, “6”, “9”
Each code is shown. This code is input to the ROM 9 and converted to an actual intermediate luminance value. This intermediate luminance value is
In this example, it is represented by 8 bits, and 255 is set to the full white level. The output of the ROM 9 is latched by the latch circuit 10 with the frequency-divided clock, and the D / A converter 11
Converted to GB signal.

As described above, the intermediate luminance values of R, G, and B are obtained. In this embodiment, 16 types of intermediate luminance values can be obtained for each of R, G, and B, so that 16 ³ = 4096 gradations (including hues) can be obtained, and a display almost close to full color can be performed. Become.

In order to change the number of dots used to 3 × 3, 4 × 4,..., The mode control signal may be set to another value.

[Effects of the Invention] As described above, according to the present invention, a digital RGB signal is collectively coded by a predetermined number of bits, and is decoded to obtain an intermediate luminance value. The number of gradations can be significantly increased.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a halftone display circuit according to an embodiment of the present invention, FIG. 2 is a diagram showing an expression example using 2 × 2 dots, FIG. 3 is a timing diagram for halftone display, FIG. 4 is a diagram showing an example of a pixel. 1,2,3; 1H delay circuit, 4,5,6,7; S / P conversion circuit, 8; Division counter, 9; ROM, 10; Latch circuit, 11; D / A converter

Claims (1)

(57) [Claims] 1. A serial / parallel conversion circuit for converting a serially input digital RGB signal into a predetermined number of bits and converting the data into parallel data corresponding to an intermediate luminance value.
A decoder for decoding parallel data output from the parallel conversion circuit and outputting data for displaying an intermediate luminance value.