JPH07154269A - Conversion circuit and scanning converter - Google Patents

Abstract

PURPOSE:To reduce the cost by providing a conversion circuit converting a 2-bit signal into an 8-bit signal to a scanning converter implementing 8-bit signal processing so as to facilitate the configuration of the scanning converter in common use for an analog CG signal and a 2-bit CG signal. CONSTITUTION:An analog CD signal (AN) is ADD-converted by an 8-bit A/D converter 1, a selector 6a selects the resulting digital signal or a digital signal obtained by converting a 2-bit CG signal (DM, DS) into an 8-bit signal by a conversion circuit 7a and the selected signal is written in a frame buffer 2. The digital signal read from the frame buffer 2 is subjected to D/A conversion by the use of an 8-bit D/A converter 3. A 1st timing signal generating circuit 4 gives an A/D conversion pulse to the A/D converter 1 and gives a write pulse to the frame buffer 2. A 2nd timing signal generating circuit 5 gives the read pulse to the frame buffer 2 and gives a D/A conversion pulse to the D/A converter 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a conversion circuit for converting an m-bit digital signal into an m.n-bit digital signal, and an analog / digital computer graphics signal as a video image on a monitor using the conversion circuit. The present invention relates to a scan conversion device for displaying.

[0002]

2. Description of the Related Art Computer graphics signals (hereinafter
The scanning line structure (called CG signal) (the number of scanning lines, interlaced / non-interlaced, and frequency of horizontal / vertical sync signals) is different from the scanning line structure of video signals in NTSC or HDTV. Therefore, the CG signal can be sent to NTSC or HDTV.
In order to display as an image on the monitor device, the scan conversion device that matches the scanning line structure is required.

FIG. 2 is a block diagram of a conventional scan conversion device. Computer not shown has 3 colors (R, G, B)
The analog CG signal which is generated by generating the CG signal and is D / A converted is input to the scan conversion device. AN in the figure is these three colors (R,
One of the CG signals of G, B), and the A / D converter 1
A / D converted by and written in the frame buffer 2.
The digital signal read from the frame buffer 2 is D /
It is D / A converted by the A converter 3 and input as a video signal to a monitor device (not shown) and displayed as a video.

The first timing signal generation circuit 4 generates an A / D conversion pulse based on the horizontal / vertical synchronization signal SYN included in the CG signal and supplies it to the A / D converter 1 to correspond to a pixel in the monitor device. A write pulse is generated and given to the frame buffer 2. The second timing generation circuit 5 also generates a read pulse based on the horizontal / vertical synchronizing signals of the monitor device and supplies the read pulse to the frame buffer 2 and a D / A conversion pulse to the D / A converter 3. Therefore analog
The CG signal AN is A / D converted based on the scanning line structure and written in the frame buffer 2, and is read out from the frame buffer 2 based on the scanning line structure of the monitor device to D / D.
A is converted.

FIG. 3 is a block diagram of a scan conversion device which incorporates a D / A converter in a conventional scan conversion device and can scan-convert a digital signal. 1 of 3 color (R, G, B) CG signals
One analog CG signal AN is input to the A / D converter 1 via the switch 6. A computer-generated not-illustrated 3-bit (R, G, B) 2-bit CG signal for each color is input to the scan conversion device. This CG signal is R _M , R _S , G _M ,
It is composed of G _S , B _M , and B _S bits. Here, R, G, and B represent red, green, and blue, respectively, and M and S represent upper and lower levels, respectively.

D _M and D _S in the figure are the three colors (R,
It is one of the 2-bit CG signals of G and B) and is input to the MSB side input terminals D ₇ and D _{6 of} the 8-bit D / A converter 7. Lower 6-bit input terminals D ₅ , D of D / A converter 7
₄ ... D ₀ is grounded. D / A converter 7 has 2 bits
Anything that can be D / A converted is acceptable. D / A converter 7
The A-converted output is amplified by the amplifier 8 and input to the A / D converter 1 via the switch 6.

The dynamic range of the output of the D / A converter 7 generally does not match the dynamic range of the analog CG signal AN. The amplifier 8 amplifies the output of the D / A converter 7 and adjusts its dynamic range to the dynamic range of the analog CG signal AN. Since other configurations are the same as those in FIG. 2, the same parts are designated by the same reference numerals and the description thereof will be omitted.

[0008]

[Problems to be Solved by the Invention]
In order to scan-convert a digital CG signal with a CG signal scan conversion device, a D / A converter that converts the digital CG signal into a D / A converter and an amplifier that matches the dynamic range are required separately, which increases the manufacturing cost. There was a problem. The present invention has been made to solve such a problem, and converts a digital CG signal into a digital signal having a predetermined number of bits in an internal processing circuit of the scan changing apparatus without using a special device. By doing so, it is an object of the present invention to provide a scan conversion device that also serves as an analog CG signal and a digital CG signal without increasing the cost.

[0009]

According to the conversion circuit of the present invention, one set of m-bit signals is arranged in parallel in a conversion circuit for converting the number of bits of an m-bit digital signal to be an integer multiple. And a circuit for generating an m · n bit signal. A scan conversion device according to the present invention selects either an analog type graphics signal or a digital type graphics signal, performs m · n bit digital processing, and determines the structure of the selected signal as a scan line of a display device. A scanning conversion device that performs conversion so as to match the structure and displays as an image is provided with a conversion circuit that arranges n sets of m-bit signals in parallel and converts them into m · n-bit signals.

[0010]

The conversion circuit of the present invention has a 1-bit structure composed of m bits.
Since n sets of digital signals are arranged in parallel and converted into digital signals composed of m · n bits, m ·
The value of the n-bit signal and the value of the m-bit signal before conversion are proportional. In the scan conversion device of the present invention, when the number of bits of the internal processing circuit is m · n bits and an analog type graphics signal is selected, m / n bit A /
The D converter converts it into a digital signal and performs appropriate digital processing to convert the structure of the selected analog signal so as to match the structure of the scanning line of the display device.

When a digital type m-bit graphics signal is selected, the conversion circuit of the present invention converts it into an m.n-bit digital signal and performs appropriate signal processing.
The selected digital signal structure is converted to match the scan line structure of the display. Therefore, the values of the graphics signal before and after conversion to m · n bits are proportional,
The converted graphics signal and the analog-type graphics signal have the same dynamic range.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described with reference to the drawings showing the embodiments thereof.
I will explain in detail. FIG. 1 is a scan conversion using the present invention.
It is a block diagram of an apparatus. AN in the figure has three colors (R,
G, B) One of the analog CG signals, 8 bits
Is A / D converted by the A / D converter 1 of the
It is written in the frame buffer 2. Also, three colors (R,
2 bits which is one of the 2-bit CG signals of G, B)
CG signal D _M, D_SIs 2 to 8 bits in the conversion circuit 7a
To the frame buffer 2 via the selector 6a.
Written. The data read from the frame buffer 2
The digital signal is D / A converted by the 8-bit D / A converter 3,
It is input to a monitor device (not shown).

The first timing signal generation circuit 4 generates an A / D conversion pulse based on the horizontal / vertical synchronization signal SYN included in the CG signal and supplies the A / D conversion pulse to the A / D converter 1 to generate a write pulse to generate a frame. Give to buffer 2. Further, the second timing signal generating circuit 5 has a built-in reference signal generating section,
Based on the horizontal / vertical synchronization of the monitor device, a read pulse is generated and applied to the frame buffer 2, and a D / A conversion pulse is generated and applied to the D / A converter 3.

The conversion circuit 7a is a conversion circuit for converting a 2-bit signal into an 8-bit signal and has eight output terminals D ₀ and D.
₁ ... D ₇ and has the lower bit D _{S of the} 2-bit signal
Is applied to terminals D ₀ , D ₂ , D ₄ and D ₆ , and the upper bit D _M is applied to terminals D ₁ , D ₃ , D ₅ and D ₇ . The signals passed through the eight output terminals D ₀ , D ₁ ... D ₇ are given to the selector 6a as 8-bit signals arranged in ascending order from the lower order to the higher order. Selector 6a receives analog CG signal AN
A / D converted 8-bit signal and 2-bit CG signal D _M ,
One of 8-bit signals in which D _S is converted to 8-bit is selected and input to the frame buffer 2.

Therefore, the analog CG signal AN is A / A based on its scanning line structure (the number of scanning lines, interlaced / non-interlaced, and frequency of horizontal / vertical synchronizing signals).
The data is D-converted and written in the frame buffer 2, read out from the frame buffer 2 and D / A-converted based on the scanning line structure of the monitor device.

Next, the operation of the conversion circuit 7a will be described.
Input in conversion circuit 7a (D_M, D _S) And output
(D₇, D₆... D₀) Is shown in Table 1.

[0017]

[Table 1]

Table 2 shows decimal values corresponding to the inputs and outputs in Table 1.

[0019]

[Table 2]

As shown in Table 2, the output decimal value is 85 times the input decimal value. That is, the conversion circuit 7a converts 2 bits into 8 bits, and the input value and the output value are proportional constants 85.
Is converted so that it becomes a proportional relationship of.

By using the conversion circuit 7a for arranging four sets of 2-bit CG signals side by side to obtain an 8-bit signal in the scanning conversion device, even if the CG signal is an analog CG signal, it is a 2-bit CG signal. However, it is possible to perform scan conversion using a common 8-bit processing circuit. In this embodiment, by arranging 4 sets of 2-bit CG signals in parallel,
The 2-bit to 8-bit conversion circuit 7a in which the output value is 85 times the input value is shown, but the number of output bits is not limited to 8 bits, and n sets of 2-bit CG signals are arranged side by side to output 2n-bit signals. The resulting transducer can also be easily constructed. The proportional constant in the proportional relationship between the input value and the output value in this case is

[0022]

[Equation 1]

It is Further, it is possible to easily configure a changer for arranging n sets of 3-bit CG signals in parallel to obtain a 3n-bit signal. The proportional constant in the proportional relationship between the input value and the output value in this case is

[0024]

[Equation 2]

[0025] Furthermore, a converter for arranging n sets of m-bit CG signals in parallel to obtain m-n-bit signals can be easily constructed. The proportional constant in the proportional relationship between the input value and the output value in this case is

[0026]

[Equation 3]

It is

[0028]

As described above, according to the present invention, the conversion circuit for arranging n sets of m-bit CG signals in parallel to obtain an m-n-bit signal is used. Therefore, even if the CG signal is an analog CG signal, m Even if it is a bit digital CG signal, common m / n
Since the scan conversion can be performed using the bit processing circuit, the structure of the scan conversion device for displaying the CG frequency on the monitor device of NTSC or HDTV is easy and the cost is reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of a conversion circuit and a scan conversion device according to the present invention.

FIG. 2 is a block diagram of a conventional scan conversion device.

FIG. 3 is a block diagram of another conventional scan conversion device.

[Explanation of symbols]

 1 A / D converter 2 Frame buffer 3 D / A converter 4 First timing signal generation circuit 5 Second timing signal generation circuit 6a Selector 7a Conversion circuit

Claims (4)

[Claims] 1. A conversion circuit for converting an m-bit digital signal so that the number of bits of the m-bit digital signal becomes an integral multiple, comprising a circuit for arranging one set of m-bit signals in parallel to generate an m · n-bit signal. A conversion circuit characterized by that. 2. An analog-type graphics signal or a digital-type graphics signal is selected, m / n-bit digital processing is performed, and the structure of the selected signal is matched with the scanning line structure of the display device. In the scan conversion apparatus for performing the above conversion and displaying as an image, a scan conversion apparatus comprising a conversion circuit for arranging one set of m bit signals in parallel and converting into m · n bit signals. 3. The conversion circuit according to claim 1, wherein m = 2 and n = 4. 4. The scan conversion device according to claim 2, wherein m = 2 and n = 4.