JPH07181937A - Image processor - Google Patents

Abstract

PURPOSE:To form multiple pictures from images of different video signal standards. CONSTITUTION:A switch 18 selects video signals which are inputted and processed by input processing circuits 14 and 16, and a switch 20 selects synchronizing signals separated by the input processing circuits 14 and 16. The output of the switch 18 is impressed to an image memory 26 through an LPF 22 and an A/D converter 24. A reduction control circuit 34 outputs a horizontal and a vertical enable signal to a memory control circuit 36 at timing corresponding to the reduction rate (k) (0<=k<=1) from a CPU 38 on the basis of the synchronizing signal from the switch 20. The memory control circuit 36 controls writing to the image memory 26 according to the synchronizing signal from the switch 20 and the enable signal from the reduction control circuit 34 and controls the write address according to the storage coordinate information from a CPU 38.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus,
More specifically, the present invention relates to an image synthesizing device capable of handling image signals of different signal standards in the same manner.

[0002] Related.

[0003]

2. Description of the Related Art Conventionally, as a conventional image processing device for synthesizing a plurality of images into a multi-image on one screen, a device for displaying the image of each channel of television broadcasting on one screen and recording it on a recording medium. There is a device for displaying a plurality of still images or a plurality of moving images displayed as a multi-image, but in each case, the signal standards of the plurality of input image signals to be made into the multi-image need to be the same. For example, in the case of NTSC video signals, they must all be in NTSC format.

[0004]

However, even if it is limited to the television system, there are currently PAL video signal, SECAM video signal and high-definition signal other than the NTSC video signal, and in the future, various systems will be available. Digital high definition signals have been proposed. Furthermore, the image
There are various formats for an image input by an image input device such as a scanner and a computer image.

An image synthesizing apparatus capable of handling many of these signal formats is desired, and an object of the present invention is to provide an image processing apparatus capable of handling a plurality of signal formats.

[0006]

An image processing apparatus according to the present invention comprises an image memory means for storing image data of at least one screen, and a reduction control means for generating a reduction control signal for an input image according to a designated reduction ratio. And a memory control means for controlling the storage of the input image in the image memory means according to the reduction control signal of the reduction control means and the storage position control signal of the image memory means. The reduction ratio can be freely changed for each image to be displayed.

[0007]

By the above means, the input image can be reduced according to the designated reduction ratio and stored in the designated position of the image memory means regardless of the signal format of the input image.
As a result, even if the images have different video signal standards,
A multi-image can be easily formed.

Since the reduction ratio can be set for each input image, for example, images of different signal standards can be reduced to the same size.

[0009]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a schematic block diagram of an embodiment of the present invention. 10 and 12 are video signal input terminals, 1
4 and 16 are RGs for video signals from the input terminals 10 and 12.
An input processing circuit for converting into a common representation format of B (or luminance / color difference), 18 is a switch for selecting the video output of the input processing circuits 14 and 16, and 20 is a synchronizing signal output from the input processing circuits 14 and 16. It is a switch to do. The switches 18 and 20 are interlocked, and when the switch 18 selects the video output of the input processing circuit 14, the switch 20 selects the sync signal output of the input processing circuit 14. Conversely, when switch 18 selects the video output of input processing circuit 16, switch 20 selects the sync signal output of input processing circuit 16.

Reference numeral 22 is a low-pass filter (LP) which can freely change the limiting frequency for limiting the output of the switch 18.
F) and 24 are A / D converters that convert the output of the LPF 22 into digital signals, and 26 is an image memory that stores the image data output from the A / D converter 24. 28 is a D / A converter for converting the image data read from the image memory 26 into an analog signal, and 30 is a converter for converting the image signal output from the D / A converter 28 into a predetermined video signal format and outputting it. The output processing circuit 32 is an output terminal for outputting the output signal of the output processing circuit 30 to the outside.

Reference numeral 34 is a reduction control circuit for controlling the reduction processing of an input image for forming a multi-image, and 36 is a control for writing and reading of the image memory 26, and an A / D.
A memory control circuit for supplying an appropriate sampling clock to the converter 24 and the D / A converter 28.

Reference numeral 38 is a CPU for controlling the whole, and a CPU bus 40 thereof has a ROM 42, a RAM 44, and an I / O.
A circuit 46, a storage device 48 such as a hard disk device, and an external interface 50 are connected. CPU38
Can access the image memory 26 via the CPU bus 40, and controls the switches 18 and 20, the pass band of the LPF 22, the reduction control circuit 34, and the memory control circuit 36.

The operation of this embodiment will be described in detail below.
The input processing circuits 14 and 16 convert the video signals from the input terminals 10 and 12 into a common format such as an RGB signal (or a luminance signal and a color difference signal) and supply them to the a contact and the b contact of the switch 18, respectively. The input processing circuits 14 and 16 also
The horizontal and vertical synchronizing signals separated from the video signal are supplied to the a contact and the b contact of the switch 20, respectively.

The synchronization signal selected by the switch 20 is applied to the reduction control circuit 34 and the memory control circuit 36. The reduction control circuit 34 has a reduction rate k from the CPU 38.
The control signal of (0 <k ≦ 1) is supplied to the reduction control circuit 3
The reference numeral 4 outputs a horizontal and vertical enable signal to the memory control circuit 36 at a timing corresponding to the reduction rate k with reference to the synchronization signal from the switch 20. The CPU 38 sends information regarding the storage coordinates on the image memory 26 to the memory control circuit 36.
The memory control circuit 36 supplies the sampling clock to the A / D converter 24 in accordance with the synchronization signal from the switch 20 and the enable signal from the reduction control circuit 34.
It also generates a write address and a write control signal for the image memory 26.

The video signal selected by the switch 18 is applied to the LPF 22, and the LPF 22 band-limits the signal from the switch 18 to the limiting frequency controlled by the CPU 38. The A / D converter 24 includes the memory control circuit 3
The output of the LPF 22 is converted into a digital signal in accordance with the sampling clock from 6 and applied to the image memory 26. The image memory 26 sequentially stores the output data of the A / D converter 24 at the write address from the memory control circuit 36. As a result, the image memory 26 has a CPU 38
The image reduced at the reduction rate k designated by the CPU 38 is stored at the coordinate position designated by.

When a multi-image composed of a desired number of images is formed in the image memory 26, the CPU 38 causes the memory control circuit 3 to operate.
6 is instructed to read. According to this instruction, the memory control circuit 36 sequentially reads the stored data from the image memory 26. The image data read from the image memory 26 is D
The signal is converted into an analog signal by the A / A converter 28, and converted into a predetermined video signal format by the output processing circuit 30. The output of the output processing circuit 30 is applied from an output terminal 32 to an external monitor device or the like and displayed as an image.

The image memory 26 communicates with the storage device 48 and the external interface 50 via the CPU bus 40, stores the storage data of the image memory 26 in the storage device 48, or external devices via the external interface 50. (Not shown). On the contrary, the image stored in the storage device 48 can be stored in the image memory 26 with the size as it is or reduced, and the image captured from an external device (not shown) via the external interface 50. Can be stored in the image memory 26 with the same size or reduced. Reduction processing is C
The PU 38 (or the reduction control circuit 34) may be in charge.

FIG. 2 shows a circuit example of the reduction control circuit 34. However, a circuit portion which is reduced in the horizontal direction is shown. Reference numeral 60 is a latch for storing the reduction rate k from the CPU 38, 62 is a latch for temporarily storing coefficient values, and 64 is an adder for adding the holding values of the latches 60 and 62. Adder 6
4 most significant bit MSB becomes horizontal enable signal,
The other bits than the most significant bit are input to the latch 62. Latch 6
The 2 most significant bits are always 0.

The latch 60 stores the reduction ratio k from the CPU 38, and the latch 62 is reset by the horizontal synchronizing signal Hsync. The adder 64 adds the holding values of the latches 60 and 62, and the MSB of the addition result becomes the horizontal enable signal. All but the MSB of the addition result are input to the latch 62,
Captured by the clock. The horizontal enable signal advances the horizontal address counter of memory control circuit 36.
Thus, for example, when the horizontal reduction ratio is 0.5, 2
The horizontal enable signal is generated once every clock, and when the horizontal reduction ratio is 0.25, the horizontal enable signal is generated once every four clocks.

FIG. 3 is a mathematical representation of the operation of FIG. The upper row shows the stored value of the latch 60 (reduction rate k), and the lower row shows the stored value of the latch 62. The fractional part of the addition result is fed back to the latch 62. The MSB of latch 62 is always 0. When a carry occurs in the addition result, it is output to the memory control circuit 36 as a horizontal enable signal.

When 1 is set in the latch 60, the MSB of the addition result is always 1, and the horizontal enable signal is generated every clock. That is, the image data is written in the image memory 26 at a non-reduced size.

Although the horizontal reduction has been described, the same applies to the vertical reduction.

In the above embodiment, for example, an NTSC video signal of 640 × 480 pixels is 25% horizontally and vertically.
When the reduction ratio of is specified, a reduced image of 160 × 120 pixels is obtained. When a PAL video signal of 768 × 576 pixels is input and a reduction ratio of 20% is designated in each of the horizontal and vertical directions, a reduced image of 154 × 115 pixels is obtained. Also,
When inputting a high-definition video signal of 1,920 × 1,035 pixels and instructing a reduction ratio of 10% in each of the horizontal and vertical directions, a reduced image of 192 × 104 pixels is obtained.

FIG. 4 shows an example of a multi-image displayed on the monitor screen. Reference numeral 70 is an image obtained by reducing an NTSC video image in horizontal and vertical directions by 25%, 72 is an image obtained by reducing a PAL video image in horizontal and vertical directions by 20%, and 74 is an image obtained by reducing a high-definition image in horizontal and vertical directions by 10%. 76
Is a reduced image of an image input from the external interface 50 by an image scanner or the like. 7
Reference numeral 8 is a reduced image of an NTSC video image, and 80 is a reduced image of a PAL video image.

It goes without saying that not only the image input to the input terminals 10 and 12, but also the image stored in the storage device 48 and the image input from the external interface 50 can be the targets of the above-described multi-image formation. . Of course, the external interface 50 may be a communication interface.

[0027]

As can be easily understood from the above description, according to the present invention, images of different signal formats can be handled very easily and a multi-image can be freely formed.

[Brief description of drawings]

FIG. 1 is a schematic block diagram of an embodiment of the present invention.

FIG. 2 is a circuit diagram of a horizontal enable signal generation circuit portion of the reduction control circuit 34.

FIG. 3 is an arithmetic operation expression corresponding to FIG.

FIG. 4 is an example of a multi-image.

[Explanation of symbols]

10, 12: Video signal input terminal 14, 16: Input processing circuit 18, 20: Switch 22: Low-pass filter 24: A / D converter 26: Image memory 28: D / A converter 30: Output processing circuit 32: Output terminal 34: Reduction control circuit 36: Memory control circuit 3
8: CPU 40: CPU bus 42: ROM44: R
AM 46: I / O circuit 48: Storage device 50: External interface 60, 62: Latch 62: Adder 70: NTSC image reduced horizontally and vertically by 20% image 72: PAL image reduced horizontally and vertically by 20% Image 74: An image obtained by reducing the high-definition image to 20% each in the horizontal and vertical directions 76: A reduced image of the image captured from the outside 7
8: Reduced image of NTSC video image 80: Reduced image of PAL video image

Claims (3)

[Claims] 1. An image memory unit for storing image data of at least one screen, a reduction control unit for generating a reduction control signal for an input image according to a designated reduction ratio, a reduction control signal for the reduction control unit and an image memory. A memory control means for controlling storage of the input image in the image memory means in accordance with a storage position control signal of the means, and the reduction rate can be freely changed for each image to be stored in the image memory means. A characteristic image processing device. 2. The image processing apparatus according to claim 1, further comprising a large-capacity storage means, and data can be transferred between the large-capacity storage means and the image memory means. 3. Further comprising an external interface,
The image processing apparatus according to claim 1, wherein data transfer is possible between the external interface and the image memory means.