JP3420151B2 - Image processing device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus, and more particularly, to an on-screen display (hereinafter referred to as OSD) function for superimposing control information such as characters and graphics or service information on an image. The present invention relates to a provided image processing device.

[0002]

2. Description of the Related Art FIG. 5 shows a conventional image processing apparatus. The image processing apparatus includes a RAM (Random Access Memory) 1, a data bus 2 connected to the RAM 1, and an RA.
A RAM control block 3 that manages the states of M1 and the data bus 2, an image data transfer unit 4 that reads color or monochrome image data from the RAM 1 via the data bus 2, and a video signal is generated from the output from the image data transfer unit 4. Video signal generation circuit 5 and data bus 2
It is connected to RAM1 via
It is configured to include a superimpose circuit 10 that generates per-posed “image + OSD” data 20.

The RAM 1 as a storage means has an OSD mask data 6, OSD data 7 as the processing information, and the OS.
Image data 8 in which D data 7 is combined, “Image + OS
Each data of the “D” data 20 is stored. For example, if the video signal output from the video signal generation circuit 5 is NTSC
In the case of (National Television System Committee) system, OSD mask data 6 for 720 × 480 pixels,
OSD data 7 and image data 8 are stored. The OSD mask data 6 includes position information at the time of superimposing, color information, information for masking a part of the image as necessary, and the like. The image data transfer unit 4 includes an image data buffer memory 11 for reading and storing “image + OSD” data 20, an image buffer write control circuit 12 for controlling writing of data into the buffer memory 11, and an image data buffer memory. 1
The buffer read control circuit 13 controls the reading of data from 1 to the video signal generation circuit 5. The video signal generation circuit 5 includes a timing signal generation unit 9 that controls the image buffer write control circuit 12 and the buffer read control circuit 13. Also,
The superimposing circuit 10 includes an “image + OSD” data synthesis circuit 14 that synthesizes OSD data with an image and outputs “image + OSD” data 20.

FIG. 6 shows image processing of the image processing apparatus shown in FIG. The operation of the image processing apparatus in FIG. 5 will be described with reference to FIG. The conventional image processing is roughly divided into two processes, and the superimposing circuit 10 causes "image + OS".
Processing 1 for generating and storing "D" data 20, and RAM 1
From "image + OSD" data 20 to generate a video signal.

First, the superimposing circuit 10 reads the image data 8, the OSD data 7, and the OSD mask data 6 from the RAM 1 via the data bus 2 (step 301), and the "image + OSD" data synthesizing circuit 14 is used. Then, the image data 8 and the OSD data 7 are superimposed according to the OSD mask data 6 to generate "image + OSD" data (step 302), and are stored again in the RAM 1 as "image + OSD" data 20 (step 303). Next, as process 2, the "image + OSD" data 20 stored in the RAM 1 is read from the RAM by the image data transfer unit 4 (step 304), and the "image + OSD" is stored in the image data buffer memory 11 of the image data transfer unit 4. The data 20 is written (step 305), and the image data written in the image data buffer memory 11 is buffer read control circuit in accordance with the image input timing required by the video signal generation circuit 5 in accordance with the timing of the video signal timing generation circuit 9. It is read under the control of 13 and input to the video signal generation circuit 5. The video signal generation circuit 5 is
Since the image of "image + OSD" obtained by superimposing the OSD data 7 on the image data 8 is an R, G, B digital signal, this is converted to an NTSC video signal and output (step 306).

[0006]

However, according to the conventional image processing apparatus, the superimposed "image + OS" is used.
Processing 1 of superimposing in steps 301 to 303 in order to output the "D" image as a video signal;
It is necessary to execute the process 2 of outputting the "image + OSD" data 20 after superimposing as a video signal. And "image + OSD" after superimposing
Since the data is stored in the RAM 1, the data bus 2 is frequently used, and the bus processing is likely to fail.

Further, since the image is once stored in the RAM 1, the continuity of the process is lost, and the utilization rate of the data bus is increased as described above.
It is difficult to continuously output the video output by repeatedly updating the contents of the “OSD” data 20. If you try not to interrupt the video signal, the image of the same content will be output repeatedly and continuously.
It was necessary to reduce the update frequency of the "D" data 20. Also, "Image + OSD" data 2 after superimposing
Since 0 is stored in the RAM 1, it is necessary to secure the storage area in the RAM 1, and the minimum storage capacity required to realize the image processing apparatus is large.

An object of the present invention is to provide an image processing apparatus which can reduce the usage rate of a data bus when superimposing OSD data on image data, improve the frequency of updating image contents, and reduce the storage capacity. To provide.

[0009]

To achieve the above object, the present invention stores OSD data and superimposes the OSD (on-screen display) data on the image data, and the OSD data. the processing information is the amount of information to superimpose
A storage means which is stored at a reduced format, image generating means for generating a composite image wherein the superimpose the OSD data to the image data based on pre-Symbol processing information, the composite image from the image generating unit A video signal generating means for converting into a video signal of NTSC system or the like ;
The image generation means is configured to read the O read from the storage means.
The reduced amount of information with respect to the SD data and the processing information
First and second interpolation circuits for interpolating the
To provide an image processing apparatus according to claim Rukoto which having a data combining unit for processing the Inpozu.

According to this structure, in the superimposing process, the image data, the OSD data, and the processing information stored in the storage means are read out in the superimposing process, and the OSD data are stored before the superimposing process.
Jo before reducing the amount of information processed information is Low reduced by the interpolation circuit
After being interpolation processing state, it is supplied at a predetermined timing to the data synthesis section, interpolation processing process information thus the image data
The OSD data subjected to is superimposed. The obtained superimposed image is not stored,
The video signal is sent to the video signal generating means as it is, and becomes a video signal converted into a predetermined system. Therefore, the utilization rate of the data bus is reduced when the OSD data is superimposed on the image data and the video is output. Therefore, each time updating the image content, real time increase the update frequency of the image content such continuously outputs a video signal processing can be ing. And, in the storage means, the OSD data
Since the processing information is stored with a reduced amount of information and the image data after superimposing is not required to be stored, it is possible to reduce the used storage area.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. [First Embodiment] FIG. 1 shows an image processing apparatus according to a first embodiment of the present invention. The image processing apparatus of the present invention is
RAM1, data bus 2 connected to the RAM1, RA
RAM control block 3, which manages the states of M1 and data bus 2, three kinds of data (OSD mask data 6, OSD data 7, and image data 8) are read from RAM 1 via data bus 2 to obtain “image + OSD” data. An image data transfer unit 40 for generating 20 and a video signal generation circuit 5 for generating a video signal based on the “image + OSD” data 20 from the image data transfer unit 40.

The image data transfer section 40 is shown in FIG.
In addition to the image data buffer memory 11, the image buffer write control circuit 12, the buffer read control circuit 13, and the “image + OSD” data synthesis circuit 14 shown in FIG.
A mask buffer write control circuit 42, an OSD data buffer memory 43, and an OSD buffer write control circuit 44 are provided. The OSD mask data buffer memory 41 is used for storing the OSD mask data 6, and the OSD data buffer memory 43 is used for the OSD mask data 6.
Used to store data 7. The image data 8 is stored in the image data buffer memory 11. And
A FIFO memory is used for the image data buffer memory 11, the OSD mask data buffer memory 41, and the OSD data buffer memory 43.

FIG. 2 shows the processing of the embodiment shown in FIG. The operation of the image processing apparatus configured as shown in FIG. 1 will be described with reference to FIGS. 2 and 1. First, under the control of the RAM control circuit 3, the image data 8, the OSD data 7, and the OSD mask data 6 stored in the RAM 1 are read out to the image data transfer unit 40 via the data bus 2, and the image data is transferred. 8 is a buffer memory for image data 11
First, the OSD mask data 6 is stored in the OSD mask data buffer memory 41, and the OSD data 7 is stored in the OSD data buffer memory 43 (step 101). When the image data 8 is written in the image data buffer memory 11, it is written in the image data buffer memory 11 in accordance with the image input timing required by the video signal generation circuit 5 in accordance with the timing of the video signal timing generation circuit 9. Buffer memory 11, 41, 43
The buffer read circuit 13 simultaneously reads out the respective data written in 1) to the "image + OSD" data synthesizing circuit 14. The “image + OSD” data composition circuit 14 reads the OSD
OS for image data 8 according to the contents of mask data 6
The process of superimposing the D data 7 is performed (step 102), and the "image + OSD" data 20 is generated.
This is output to the video signal generation circuit 5 (step 10)
3). The video signal generation circuit 5 uses the OSD for the image data 8.
"Image + OSD" with data 7 superimposed
The image of is output as a video signal (step 10).
4).

As described above, in the present embodiment,
The image data transfer unit 40 stores the image data 8 and the OSD data 7 separately stored in the RAM 1 into the RA.
"Image + OSD" data composition circuit 1 read from M1
By generating a superimpose image in 4 and directly outputting the video without storing it in the RAM 1 as in the conventional case, continuous image processing becomes possible. Also, RAM1
However, since only reading is performed, the load on the data bus can be reduced and the data storage capacity in the RAM 1 can be reduced as compared with the related art.

[Second Embodiment] FIG. 3 shows a second embodiment of the present invention.
An embodiment of is shown. The present embodiment is characterized in that an image data transfer unit 50 is used instead of the image data transfer unit 40 in the configuration of FIG. In addition to the configuration of the image data transfer unit 40, the image data transfer unit 50 is provided with an interpolation circuit 51 between the OSD mask data buffer memory 41 and the “image + OSD” data synthesis circuit 14, and the OSD data buffer memory 43 and Image + OSD "data composition circuit 14
An interpolating circuit 52 is provided between the two.

The interpolation circuits 51 and 52 read from the buffer memories 41 and 43 in the image data transfer section 50 when the information amount of the OSD data 7 and the OSD mask data 6 stored in the RAM 1 is reduced with respect to the image data 8. Then, it is used to supplement the reduced original information amount by the interpolation circuits 51 and 52. The process of reducing the information amount of the OSD data 7 and the OSD mask data 6 is performed by a circuit (not shown) and then stored in the RAM 1. There are various processes for reducing the information amount of the OSD data 7 and the OSD mask data 6, but they are achieved by, for example, a process of thinning out each pixel. The interpolation processing by the interpolation circuits 51 and 52 may be the reverse of the processing for reducing the amount of information.

In general, it is known that the OSD data 7 has a sufficient amount of information even if it is smaller than the image data 8. For example, assuming that the total number of pixels of the image data 8 is 720 pixels × 480 lines,
360 pixels x 48 with half the number of horizontal pixels
Data for 0 lines is stored in the RAM 1 as OSD data 70 and OSD mask data 60. In the image processing apparatus, it is necessary that the OSD data 7 and the image data 8 have the same number of pixels at the time of performing the superimposing. However, as mentioned above, RAM1
Stores the OSD data 70 whose data amount is reduced to 1/2 of the image data 8. This OSD data 70 is directly used as the “image + OSD” data composition circuit 14
Cannot be read into. Therefore, the O read from the RAM 1 and stored in the OSD data buffer memory 43
When the SD data 70 is read, the interpolation circuit 52 interpolates the OSD data 7. Further, when the OSD mask data 60 read from the RAM 1 and stored in the OSD mask data buffer memory 41 is read, the interpolation circuit 51 is used.
To generate OSD mask data 6. As a result, the information amount of the OSD data 7 to be stored in the RAM 1 can be reduced and stored as the OSD data 70, so that the frequency of use of the data bus 2 is reduced and the load on the data bus 2 is significantly larger than that in the first embodiment. Reduce to.

FIG. 4 shows the processing of the image processing apparatus shown in FIG.
The operation of the image processing apparatus configured as shown in FIG. 3 will be described with reference to FIGS. 3 and 4. In the RAM 1, as described above, the data in which the number of pixels in the horizontal direction is reduced to 1/2 is stored in the OS.
It is stored as D data 70 and OSD mask data 60. Under the control management of the RAM control circuit 3, R
Image data 8 and OSD data 7 stored in AM1
0 and the OSD mask data 60 are read by the image data transfer unit 50, the image data 8 is stored in the image data buffer memory 11, and the OSD mask data 60 is stored in the OS.
The OSD data 70 is stored in the D-mask data buffer memory 41 and the OSD data buffer memory 43 (step 201). Buffer memory 11, 41, 43
Under the control of the buffer reading circuit 13, the respective data regarding the same pixel are simultaneously read out to the “image + OSD” data synthesizing circuit 14 under the control of the buffer reading circuit 13. At this time, the interpolation circuit 52 is added to the OSD data 70 read from the OSD data buffer memory 43.
The OSD mask data 6 read from the OSD mask data buffer memory 41 is interpolated by the original OSD data 7 for 720 pixels × 480 lines.
For 0, the original 720 pixels x 48 by the interpolation circuit 51
A process of interpolating the OSD mask data 6 for 0 lines is performed, and each is sent to the "image + OSD" data synthesizing circuit 14 (step 202). The “image + OSD” data synthesizing circuit 14 interpolates the image data 8 with the interpolating circuit 52 according to the contents of the OSD mask data 6 from the interpolating circuit 51.
The process of superimposing the OSD data 7 from the image is performed (step 203), and the "image + OSD" data 20
To generate. This superposed image data is output to the video signal generation circuit 5 (step 204).
The video signal generation circuit 5 outputs an image of "image + OSD" in which the OSD data 7 is superimposed on the image data 8 as an NTSC video signal (step 205).

In the above embodiment, the RAM is used to store the image data 8, the OSD data 7, and the OSD mask data 6, but the RAM is not limited to this, and for example, a Herba disk, a CD-ROM, etc. It may be a storage medium. Alternatively, only the OSD mask data 6 may be stored in a ROM (read only memory), and the image data 8 and the OSD data 7 may be stored in the RAM 1. Furthermore, although the video signal output from the video signal generation circuit 5 is based on the NTSC system, the present invention is not limited to this, and the PAL or secum system may be used. Note that the RAM1
The amount of data stored in is different.

[0020]

As described above, according to the image processing apparatus of the present invention, the OSD data and the processing information stored with the reduced amount of information are read out from the storage means and the interpolation time is read.
This OSD data, processing information, and
And image generating means for supplying the image data read from the storage means to the data synthesizing section at a predetermined timing, and generating the synthesized image in which the OSD data is superimposed on the image data according to the processing information by the data synthesizing section. Therefore, the superimposed image can be directly used as the video signal generation means without re-storing it in the storage means, which reduces the load on the data bus and the storage means .
Shows the OSD data and processing information in a state where the amount of information is reduced.
In addition, the image data after being superposed and
Since there is no need to store it, it is possible to reduce the storage area used by the storage means .

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of an image processing apparatus of the present invention.

FIG. 2 is a flowchart showing processing of the image processing apparatus of FIG.

FIG. 3 is a block diagram showing a second embodiment of the image processing apparatus of the invention.

FIG. 4 is a flowchart showing processing of the image processing apparatus of FIG.

FIG. 5 is a block diagram showing a conventional image processing apparatus.

6 is a flowchart showing processing of the image processing apparatus of FIG.

[Explanation of symbols]

1 RAM 2 data bus 40 Image data transfer section 5 Video signal generation circuit 11 Image data buffer memory 12 Image buffer write control circuit 13 Buffer read control circuit 14 "Image + OSD" data synthesis circuit 41 OSD mask data buffer memory 42 OSD mask buffer write control circuit 43 OSD data buffer memory 44 OSD Buffer Write Control Circuit 51,52 Interpolation circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H04N 5/278 H04N 5/445 G09G 5/00-5/377

Claims (4)

(57) [Claims] 1. The image data is stored , and OSD (on-screen display) data superimposed on the image data and processing information for superimposing the OSD data have an information amount.
A storage means which is stored at a reduced format, image generating means for generating a composite image wherein the superimpose the OSD data to the image data based on pre-Symbol processing information, the composite image from the image generating unit A video signal generating means for converting into a video signal of NTSC system or the like is provided , and the image generating means is before read from the storage means.
The reduced information with respect to the OSD data and the processing information.
It has first and second interpolation circuits for interpolating the information and a data synthesizing unit for performing the superimposing processing.
The image processing apparatus according to claim to Rukoto. Wherein said image generating means, wherein a first buffer memory for temporarily storing the image data read out from said memory means and temporarily storing the OSD data read from the memory means A second buffer memory for outputting to the first interpolating circuit; a third buffer memory for temporarily storing the processing information read from the storing means and outputting to the second interpolating circuit; and the storing means. From the storage means to the second buffer memory, and a first write control circuit for controlling writing of the image data from the storage means to the second buffer memory.
A second write control circuit for controlling writing of SD data, a third write control circuit for controlling writing of the processing information from the storage means to the third buffer memory, the first, second and The image processing apparatus according to claim 1, further comprising a read control circuit that controls reading of the image data, the OSD data, and the processing information from a third buffer memory to the data combining unit. 3. The video signal generating means comprises:
The image processing apparatus according to claim 2 , further comprising a second and third write control circuit, and a timing signal generation unit that supplies a timing signal for writing and reading to and from the read control circuit. 4. The storage means stores the image data and the image data.
Each of the OSD data and the processing information is common
The image processing apparatus according to claim 1, wherein the image processing apparatus is a RAM read via a data bus .