JP3338002B2 - Video device with image memory function - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video device having an image memory function for performing video processing, and more particularly to a video device having a general purpose in an information processing device without using a 3-port field memory dedicated to video. And inexpensive SRAM
A plurality of times of writing and reading are realized by using one memory of one port such as a memory and a DRAM.

[0002]

2. Description of the Related Art Conventionally, a video signal processing device stores a part or the whole of a screen in a memory and processes signals in the memory to realize functions such as noise reduction and special effects. In a video signal processing device using a memory, in order to meet demands for miniaturization, low power consumption, and low price, various devices with a small memory capacity are used to realize various functions.

For example, Japanese Patent Application Laid-Open No. 8-307760 proposes a method for realizing various functions with a small memory capacity by using a memory.

Hereinafter, a conventional video apparatus will be described with reference to FIG. In FIG. 20, a signal input from a video input 101 is written to a write port of a field memory 102 by a control signal of a write control circuit 103. The signal written to the field memory 102 is 1
After a field period delay, the data is read from the first read port of the field memory 102 by the control signal of the first read control circuit 104, and the second read control circuit 105
Is read from the second read port of the field memory 102 by the control signal of

The first read control circuit 104 performs control so as to read an area from an address given by a read start relative address 107 to an address given by a read end relative address 108. Then, the signal read from the first read port of the field memory 102 is output from the video output 106, and is electronically enlarged by an interpolation circuit (not shown).

The second read control circuit 105 reads the written signal of the entire area, and the signal read from the second read port of the field memory 102 is subjected to noise reduction by a recursive noise reduction circuit (not shown). Is used as a signal. The write control circuit 103 uses the field memory 102 in a ring shape by controlling to perform writing from the address next to the address given by the read end address 108, so that the write address overtakes the first read address. Disappears. Note that the synchronization signal terminal 109 is arranged to synchronize the operations of the writing circuit 103, the first read control circuit 104, and the second read control circuit 105 by inputting a synchronization signal.

As described above, by controlling the field memory in a ring shape using the three-port field memory having one write port and two read ports, an electronic enlargement function and a cyclic noise reduction function can be achieved. Multiple functions can be compatible at the same time.

[0008]

However, a three-port field memory used in a conventional video device is dedicated to a video device, and is generally used for a one-port SRAM or DRAM used in an information processing device or the like. There was a problem that it was very expensive.

The present invention solves such a conventional problem, and does not use a three-port field memory dedicated to video as in the prior art. It is an object of the present invention to provide a video device with an image memory function that can realize writing and reading a plurality of times using one memory of one port such as a DRAM.

[0010]

In order to achieve this object, the number of the video devices with the image memory function of the present invention is m (m
≧ 1 and a natural number) and n (n ≧ 1 and a natural number) read buffer memories using a normal write or read frequency (m +
n) Writing and reading to and from a one-port memory are performed in a time-division manner at twice or more times the frequency.

As described above, according to the present invention, even if one general and inexpensive one-port memory is used, m writing and n reading are performed on the memory, and (m
+ N) A video device with an image memory function capable of performing the same operation as the memory of the port is obtained.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is a one-port memory having an image storage capacity of one field or more, and m (m ≧ 1 and a natural number) write buffer memories. And m write control units for controlling the writing of the m write buffer memories, and n ( n ≧ 2 and a natural number) read buffer memories;
N reading control units for controlling reading of the n reading buffer memories, reading of the m writing buffer memories, writing of the n reading buffer memories, and storing images of one field or more. A memory input / output control unit for controlling writing and reading of a one-port memory having a capacity, wherein the video input is written to the m writing buffer memories by controlling the m writing control units; Under the control of the input / output control unit, the read signals of the m write buffer memories are written to a one-port memory having the storage capacity of the image of one field or more, and the storage capacity of the image of one field or more is provided. Reading the delayed signal from the one-port memory and writing it to the n read buffer memories; The reading of the n read buffer memories is controlled by the n read control units to output a read signal as a video output, and a 1-port memory having a storage capacity of an image for one field or more is provided. The frequency at which the writing to the m writing buffer memories and the reading to the n reading buffer memories are performed at a frequency (m + n) times or more such that only one writing or reading is performed in a time-division manner. The memory input / output control unit controls time-division (m + n) double-speed conversion so as to perform reading of m write buffer memories and writing of the n read buffer memories. The video outputs of the read buffer memories are subjected to electronic enlargement processing, The video output of at least one read buffer memory is subjected to noise reduction processing, and is a video device with an image memory function. By performing writing in the n read buffer memories at a frequency of (m + n) times or more in a time-division manner, the same operation as the memory of the (m + n) port is performed, and the video output of one or more read buffer memories is performed. Has an effect that an image device with an image memory function that performs an electronic enlargement process and performs a noise reduction process with the image output of one or more other read buffer memories can be configured.

[0013]

[0014]

[0015]

According to a second aspect of the present invention, there is provided a one-port memory having a storage capacity for an image of one field or more, and a video signal is inputted at a clock having the same frequency as that of the inputted video signal. M bits (m ≧ 1 and a natural number) for performing a bit operation of dividing a video signal input by a certain clock and synthesizing a video signal of the divided clock into a video signal input by another clock among the signals An operation unit, and m for inputting output signals of the m bit operation units
Write buffer memories, m write control units for controlling the writing of the m write buffer memories, n read buffer memories ( n ≧ 2 and a natural number), and the n read buffers N read control units for controlling reading of the buffer memory for reading, and n read signals for inputting the output signals of the n read buffer memories and restoring the signals subjected to bit manipulation by the m bit manipulation units A bit restoring unit, and controls reading of the m writing buffer memories, writing of the n reading buffer memories, and writing and reading of a one-port memory having a storage capacity of one or more fields of images. A memory input / output control unit, wherein the bit operation unit performs a bit operation, and then transfers the bit operation to the m write buffer memories. Writing is performed under the control of the m write control units, and the read signals of the m write buffer memories are transferred to the one-port memory having the image storage capacity of one field or more under the control of the memory input / output control unit. Writing, reading the delayed signal from the one-port memory having the image storage capacity of one field or more, writing the signals into the n read buffer memories, and reading the n read buffer memories from the n read buffer memories , A signal is restored by the n number of bit restoration units and output as a video output, and 1 bit is stored in a 1-port memory having an image storage capacity of one field or more. The memory input / output control unit controls so that only one write or read is performed in a time-division manner, To perform the conversion, furthermore, the video output of the at least one bit recovery unit is subjected to electronic enlargement processing, yet another at least
The video output of the bit restoring unit is a video device with an image memory function, which is subjected to noise reduction processing. Only one write or read to one port memory is performed in a time-division manner. The memory input / output control unit performs time-division pseudo (m + n) double-speed conversion under the control of the memory input / output control unit, and performs bit operations when writing to m write buffers, and performs bit operations when reading n read buffer memories. By restoring (m +
n) The same operation as the port memory is performed, electronic enlargement processing is performed with the video output of one or more read buffer memories, and noise reduction processing is performed with the video output of another one or more read buffer memories. This has the effect that a video device with an image memory function can be constructed.

[0017]

[0018]

[0019]

According to a third aspect of the present invention, there is provided a one-port memory having an image storage capacity of one field or more, and m (m ≧ 1 and a natural number) write buffer memories;
M write control units for controlling the writing of the m write buffer memories, n ( n ≧ 2 and a natural number) read buffer memories, and read control of the n read buffer memories an n read control unit, which controls reading of the m write buffer memories, writing of the n read buffer memories, and writing and reading of a one-port memory having a storage capacity of one or more fields of images; A memory input / output control unit for controlling the memory input / output control unit, wherein the video input is controlled and written to the m write buffer memories by the m write control units. The read signals from the m write buffer memories are transferred to one port having an image storage capacity of one field or more. Writing to a memory, reading a delayed signal from a one-port memory having a storage capacity for the image of one field or more, writing the delayed signal to the n read buffer memories, and reading the n read buffer memories. A read signal is output as a video output under the control of the n read control units, and only one write or read is performed in a time-division manner with respect to the one-port memory having the image storage capacity of one field or more. As described above, the reading of the m writing buffer memories and the n reading of the n writing buffer memories are performed at a frequency of (m + n) times or more the frequency at which the writing to the m writing buffer memories and the reading to the n reading buffer memories are performed. Memory input / output control so as to perform writing to the read buffer memories. A time division (m + n) double speed conversion is performed by the control of the section, and writing to at least one of the n read buffer memories is necessary for the electronic enlargement processing by the electronic enlargement control section. The memory input / output control unit is controlled so as to be in an arbitrary vertical direction so as to perform vertical cutout. Further, the video output of at least one other read buffer memory is subjected to noise reduction processing. A video device with an image memory function, wherein reading of m write buffer memories and writing of n read buffer memories are performed in a time-division manner (m + n) times for one port of memory. By performing the above-described operation at the above frequency, the same operation as that of the memory of the (m + n) port is performed, and one or more read buffer memories A video device with an image memory function that reads out only the vertical area necessary for electronic enlargement processing from the memory of one port at the time of writing, and performs noise reduction processing with the video output of one or more other read buffer memories Has the effect of being able to

[0021]

According to a fourth aspect of the present invention, there is provided a one-port memory having an image storage capacity of one field or more, and a video signal is input at a clock having the same frequency as the input video signal. M bits (m ≧ 1 and a natural number) for performing a bit operation of dividing a video signal input by a certain clock and synthesizing a video signal of the divided clock into a video signal input by another clock among the signals An operation unit, and m for inputting output signals of the m bit operation units
Write buffer memories, m write control units for controlling the writing of the m write buffer memories, n read buffer memories ( n ≧ 2 and a natural number), and the n read buffers N read control units for controlling reading of the buffer memory for reading, and n read signals for inputting the output signals of the n read buffer memories and restoring the signals subjected to bit manipulation by the m bit manipulation units A bit restoring unit, and controls reading of the m writing buffer memories, writing of the n reading buffer memories, and writing and reading of a one-port memory having a storage capacity of one or more fields of images. A memory input / output control unit, and an electronic enlargement control unit. The m write control units write data to the buffer memory under the control of the m write control units, and the read signals of the m write buffer memories are controlled by the memory input / output control unit to have a storage capacity of the image of one field or more. Writing to the port memory, reading the delayed signal from the one-port memory having the image storage capacity of one field or more, writing the delayed signals to the n read buffer memories, and reading the n read buffer memories Is controlled by the n read control units, and a signal is restored by the n bit restoring units and output as a video output. The memory input / output control unit controls so that only one write or read is performed in a time-division manner Split pseudo (m + n)
Double speed conversion is performed so that the electronic enlargement control unit writes in at least one of the n read buffer memories to any vertical area required for electronic enlargement processing. The image input / output control unit controls the memory input / output control unit to perform vertical cutout, and further performs a noise reduction process on a video output of at least one other bit restoration unit. A video device, performing time-division pseudo (m + n) double-speed conversion under the control of the memory input / output control unit so that only one write or read operation is performed in a time-division manner with respect to a one-port memory; By performing a bit operation when writing to the write buffer and restoring the bit operation when reading the n read buffer memories. The same operation as that of the (m + n) -port memory is performed, and at the time of writing to one or more read buffer memories, only the vertical area necessary for the electronic enlarging process is read from the one-port memory. This has the effect that a video device with an image memory function for performing noise reduction processing on the video output of the read buffer memory can be configured.

[0023]

According to a fifth aspect of the present invention, there is provided a one-port memory having an image storage capacity of one field or more, and m (m ≧ 1 and a natural number) write buffer memories.
M write control units for controlling the writing of the m write buffer memories, n read buffer memories (n ≧ 1 and a natural number), and read control of the n read buffer memories an n read control unit, which controls reading of the m write buffer memories, writing of the n read buffer memories, and writing and reading of a one-port memory having a storage capacity of one or more fields of images; A memory input / output control unit for controlling the memory input / output control unit, wherein the video input is controlled and written to the m write buffer memories by the m write control units. The read signals from the m write buffer memories are transferred to one port having an image storage capacity of one field or more. Writing to the memory, reading the delayed signal from the one-port memory having the storage capacity of the image for one field or more, writing the delayed signal to the n read buffer memories, and reading the n read buffer memories. A read signal is output as a video output under the control of the n read control units, and only one write or read is performed in a time-division manner with respect to the one-port memory having the image storage capacity of one field or more. As described above, the reading of the m writing buffer memories and the n reading of the n writing buffer memories are performed at a frequency of (m + n) times or more the frequency at which the writing to the m writing buffer memories and the reading to the n reading buffer memories are performed. Memory input / output control so as to perform writing to the read buffer memories. A time division (m + n) double speed conversion is performed by the control of the section, and writing to at least one of the n read buffer memories is necessary for the electronic enlargement processing by the electronic enlargement control section. The memory input / output control unit is controlled so as to be in an arbitrary vertical direction, and a vertical cutout is performed. Further, reading of the at least one read buffer memory is performed in an arbitrary horizontal direction necessary for electronic enlarging processing. A video device with an image memory function, wherein one of the n read control units corresponding to the at least one read buffer memory is controlled so as to form an area in a horizontal direction so as to perform horizontal cutout. And reading of m write buffer memories and writing of n read buffer memories to one port memory The same operation as the memory of the (m + n) port is performed by performing only the time division on the frequency of (m + n) times or more, and the vertical direction necessary for the electronic enlargement processing at the time of writing to one or more read buffer memories is performed. It is possible to configure a video device with an image memory function that reads only an area from the one-port memory and reads only an arbitrary horizontal area necessary for electronic enlarging processing when reading one or more read buffer memories. Has an action.

According to a sixth aspect of the present invention, in the video device with the image memory function according to the thirteenth aspect, the video output of at least one other read buffer memory is subjected to noise reduction processing. By performing reading of m write buffer memories and writing of n read buffer memories in a one-port memory in a time-division manner at a frequency of (m + n) times or more, (m
+ N) The same operation as the port memory is performed, and at the time of writing to one or more read buffer memories, only the vertical area necessary for the electronic enlarging process is read from the one port memory, and one or more read buffers are read. To configure an image device with an image memory function that reads only an arbitrary horizontal area necessary for electronic enlargement processing at the time of memory reading, and performs noise reduction processing with the video output of one or more other reading buffer memories. It has the effect of being able to.

[0026] The invention according to claim 7, the memory of one port having a storage capacity of one field or more images, input
The video signal is input with a clock of the same frequency as the input video signal.
Of the input video signals
The input video signal is divided and the divided video signal is
M (m ≧ 1 and a natural number) bit operation units for performing a bit operation for synthesizing a signal with a video signal input by another clock, and inputting the output signals of the m bit operation units M
Write buffer memories, m write control units for controlling the writing of the m write buffer memories, n read buffer memories (n ≧ 1 and a natural number), and the n read buffers to restore the n pieces of read control section for controlling reading of the use buffer memory, the n-number of signals of the m-bit operation unit Devi Tsu preparative operation by inputting the output signal of the read buffer memory n bit restoring units, for reading out the m write buffer memories, writing in the n read buffer memories, and writing and reading in a one-port memory having a storage capacity of one or more fields of images; a memory output control unit for controlling, and a electronic enlargement control unit, said m write after performing the previous SL bit manipulation unit Devi Tsu preparative operation 1 port having an image storage capacity of one field or more of the read signals of the m write buffer memories under the control of the memory input / output control section under the control of the m write control sections. And reads the delayed signal from the one-port memory having the image storage capacity of one field or more, writes the delayed signal into the n read buffer memories, and reads the n read buffer memories. The control is performed by the n read control units, the signals are read out, the signals are restored by the n bit restoring units, and output as a video output. On the other hand, the memory input / output control unit controls such that only one write or read is performed in a time-division manner. Time division pseudo (m + n)
Double speed conversion is performed so that the electronic enlargement control unit writes in at least one of the n read buffer memories to any vertical area required for electronic enlargement processing. The memory input / output control unit is controlled to perform a vertical cutout, and the at least one read buffer memory is read out from the at least one read buffer memory in an arbitrary horizontal area required for electronic enlarging processing. A video device with an image memory function, characterized in that the read control unit corresponding to a plurality of read buffer memories is controlled to cut out in the horizontal direction .
So that only writing or reading
Time division pseudo (m + n) times controlled by memory input / output control unit
By performing the speed conversion, the same operation as that of the (m + n) port memory is performed, and at the time of writing to one or more read buffer memories, only the vertical area necessary for the electronic enlarging process is read from the one port memory. , 1
This has the effect that it is possible to configure a video device with an image memory function that reads only an arbitrary horizontal area required for electronic enlargement processing when reading out more than one read buffer memory.

The invention according to claim 8 is the video device with an image memory function according to claim 15, wherein the video output of at least one other bit restoration unit is subjected to noise reduction processing. Reading of m write buffer memories and writing of n read buffer memories to a one-port memory in a time sharing manner (m + n)
By performing the operation at less than twice the frequency, the same operation as that of the (m + n) port memory is performed, and only the vertical area necessary for the electronic enlargement processing at the time of writing in one or more read buffer memories is performed from the one-port memory. At the time of reading, at the time of reading of one or more read buffer memories, only an arbitrary horizontal area necessary for the electronic enlarging process is read, and further, noise reduction processing is performed with the video output of another one or more read buffer memories. This has the effect that a video device with an image memory function can be configured.

According to a ninth aspect of the present invention, there is provided a one-port memory having an image storage capacity of one field or more, and m (m ≧ 1 and a natural number) write buffer memories;
M write control units for controlling the writing of the m write buffer memories, n ( n ≧ 2 and a natural number) read buffer memories, and read control of the n read buffer memories an n read control unit, which controls reading of the m write buffer memories, writing of the n read buffer memories, and writing and reading of a one-port memory having a storage capacity of one or more fields of images; A memory input / output control unit for controlling the memory input / output control unit, wherein the video input is controlled and written to the m write buffer memories by the m write control units. The read signals from the m write buffer memories are transferred to one port having an image storage capacity of one field or more. Writing to a memory, reading a delayed signal from a one-port memory having a storage capacity for the image of one field or more, writing the delayed signal to the n read buffer memories, and reading the n read buffer memories. A read signal is output as a video output under the control of the n read control units, and only one write or read is performed in a time-division manner with respect to the one-port memory having the image storage capacity of one field or more. As described above, the reading of the m writing buffer memories and the n reading of the n writing buffer memories are performed at a frequency of (m + n) times or more the frequency at which the writing to the m writing buffer memories and the reading to the n reading buffer memories are performed. Memory input / output control so as to perform writing to the read buffer memories. A time division (m + n) double speed conversion is performed by the control of the section, and writing to at least one of the n read buffer memories is necessary for the electronic enlargement processing by the electronic enlargement control section. The memory input / output control section is controlled so as to be in an arbitrary area so as to perform vertical and horizontal cutouts. Further, the video output of at least one other read buffer memory is subjected to noise reduction processing. A video device with an image memory function, wherein reading of m write buffer memories and writing of n read buffer memories are performed in a time-division manner (m + n) times for one port of memory. By performing the above-mentioned operation at the above frequency, the same operation as the memory of the (m + n) port is performed, and one or more read buffer memories are read. Region required for electronic enlargement processing when writing only 1
This has the effect that a video device with an image memory function can be configured to read from the memory of the port and perform noise reduction processing with the video output of one or more other read buffer memories.

[0029]

Hereinafter, an embodiment of the present invention will be described with reference to FIG.
19 will be described with reference to FIG.

(First Embodiment) FIG. 1 is a block diagram showing a configuration of a video apparatus with an image memory function according to a first embodiment of the present invention. In FIG. 1, a video device with an image memory function holds a one-port memory 2 having a storage capacity of an image of one field or more, and temporarily holds a write video signal for one horizontal scanning period when writing to the one-port memory 2. A write buffer memory 3, a write control circuit 4 for controlling the write side of the write buffer memory, and a first buffer for temporarily holding a read video signal for one horizontal scanning period at the time of the first read from the one-port memory 2.
Read buffer memory 5 and first read control circuit 6 for controlling the read side of first read buffer memory 5
A second read buffer memory 7 for temporarily holding a read video signal for one horizontal scanning period at the time of the second read from the one-port memory 2, and a second read for controlling the read side of the second read buffer memory 7. Control circuit 8
The reading side of the write buffer memory 3 and the first
A memory input / output control circuit 9 for controlling the write side of each of the read buffer memory 5 and the second read buffer memory 7 and further controlling the writing and reading of the one-port memory 2; a write buffer memory 3 and a first read buffer memory 5; And a bidirectional buffer 10 for controlling the signal direction between the second read buffer memory 7 and the one-port memory 2.

A video input signal is input from the input terminal 1, a first read signal output from the first read buffer memory 5 is output from the output terminal 11, and a sync signal of the video signal is output from the sync input terminal 12. Is entered.

Hereinafter, the operation of the first embodiment of the present invention will be described. In FIG. 1, a video signal for one horizontal scanning period input from the video input terminal 1 is written into the write buffer memory 3 at the same frequency as the input video signal by the control signal of the write control circuit 4. The video signal for one horizontal scanning period written to the write buffer memory 3 is read out at a frequency three times the input video signal and written to the one-port memory 2 by a control signal of the memory input / output control circuit 9.

In order to read from the one-port memory 2 the areas required for the first and second read signals among the video signals written one field before, the control signal of the memory input / output control circuit 9 controls Port memory 2
, One horizontal scanning period of a necessary region at a frequency three times as high as that of the input video signal is read out, and written into the corresponding first read buffer memory 5 and second read buffer memory 7 by the control signal of the memory input / output control circuit 9.

The bidirectional buffer 10 controls the output signal of the write buffer memory 3 to be output to the 1-port memory 2 when writing to the 1-port memory 2 by the control signal of the memory input / output control circuit 9. Control is performed such that an output signal from the one-port memory 2 is input to the first read buffer memory 5 and the second read buffer memory 7 when reading from the port memory 2.

The video signal for one horizontal scanning period written in the first read buffer memory 5 is supplied to the first read control circuit 6 at the same frequency as the input video signal.
It is read out as a readout signal and output from the output terminal 11 as an output video signal. The video signal for one horizontal scanning period written in the second read buffer memory 7 is read as a second read signal at the same frequency as the input video signal by the control signal of the second read control circuit 8.

The synchronizing signal input terminal 12 is arranged to synchronize the operations of the write control circuit 4, the first read control circuit 6, the second read control circuit 8, and the memory input / output control circuit 9 by inputting a synchronizing signal. You.

Next, the operation of the one-port memory 2, the write buffer memory 3, the first read buffer memory 5, and the second read buffer memory 7 will be described with reference to FIG.

FIG. 2 is a diagram for explaining the operation of the time-division processing of the one-port memory, the write buffer memory, the first read and the second read buffer memory. Each partial diagram shown in FIG. 2 shows the operation timing of the one-port memory 2. In FIG. 2A, since the one-port memory 2 has only one input / output terminal, one write operation and two read operations are performed in a time-sharing manner within one horizontal scanning period. That is, one horizontal scanning period is divided into ３, and the writing and reading operations are performed at three times the frequency. 3
The write buffer memory 3, the first buffer memory 5, and the second
The buffer memory 7 is used.

FIG. 2B shows the write buffer memory 3.
The operation timing of FIG. A signal of one horizontal scanning period is input and written at one frequency over one horizontal scanning period, and read and output at three times the frequency. The read operation is performed in the 1/3 period after one horizontal scanning period so that the read does not overtake the write.

FIG. 2C shows the operation timing of the first read buffer memory 5. 1 at 3 times the frequency
A signal for a horizontal scanning period is input and written, and is read out and output at a frequency of 1 over one horizontal scanning period. The writing operation is performed in a 1/3 period located in the middle of one horizontal scanning period. In the first read buffer memory 5, the writing overtakes the reading in the middle of one horizontal scanning period. Therefore, a loop control for shifting the writing start position and the reading start position every horizontal scanning period to prevent the overtaking occurs, or Control is performed so that writing and reading are not performed simultaneously on the same memory by using two or more.

FIG. 2D shows the operation timing of the second read buffer memory 7. 1 at 3 times the frequency
A signal for a horizontal scanning period is input and written, and is read out and output at a frequency of 1 over one horizontal scanning period. The writing operation is performed in the first 前 period of one horizontal scanning period so that the reading does not overtake the writing.

Next, an operation in which an electronic enlargement circuit and a cyclic noise reduction circuit are added will be described with reference to FIG. FIG. 3 is a block diagram illustrating a configuration of a video device with an image memory function including an electronic enlargement circuit and a cyclic noise reduction circuit. FIG. 3 shows an electronic enlargement circuit 13 and a cyclic noise reduction circuit 14 added to FIG.
1 are denoted by the same reference numerals, and the description of the operation is omitted.

In FIG. 3, a first read signal which is an output of the first read buffer memory 5 is supplied to an electronic magnifying circuit 13.
And an electronic enlargement process is performed. Further, the input video signal and the second read signal which is the output of the second read buffer memory 7 are input to the cyclic noise reduction circuit 14, where the input video signal and the second read signal delayed by one or more field periods form a cyclic readout signal. Noise reduction processing is performed.

Electronic expansion circuit 13 and cyclic noise reduction circuit
The 14 input signals are separate and can be operated separately. For example, when the cyclic noise reduction circuit 14 is operated using an interlace signal, if the second readout signal is a signal delayed by one field period, a signal whose spatial vertical phase is shifted by ラ イ ン line from the input video signal And cyclic noise reduction processing. Further, if the second read signal is a signal delayed by two field periods, it becomes a signal spatially coincident with the input video signal, and the effect of the cyclic noise reduction processing is improved.

In the electronic magnifying circuit 13, it is desirable to reduce the delay time between the input video signal and the output video signal, and independently of the delay time of the second read signal used in the cyclic noise reduction processing, the first read signal is independent. A signal delayed by one field period can be input.

As described above, according to the first embodiment of the present invention, one write and two read operations to the memory are performed.
Convert to double frequency and write to 1-port memory, and read from 1-port memory to triple frequency is inversely converted to 1-times frequency by two read buffer memories, respectively. It is possible to obtain a video device with an image memory function that realizes one writing and two readings using a memory.

Further, it is possible to obtain a video device with an image memory function in which an electronic enlargement process is performed using the first read signal and a cyclic noise reduction process is performed independently using the second read signal.

(Second Embodiment) FIG. 4 is a block diagram showing a configuration of a video device with an image memory function according to a second embodiment of the present invention. In FIG. 4, the same parts as those in the first embodiment and FIG. 1 are denoted by the same reference numerals, and the operation and function are the same, so that the description of the operation is omitted.
FIG. 4 differs from FIG. 1 in that it includes a bit operation circuit 15 for performing a bit operation between signals and bit restoration circuits 16 and 17 for restoring a signal on which the bit operation has been performed.

Hereinafter, the operation of the second embodiment of the present invention will be described mainly for parts different from the first embodiment. In FIG. 4, a video signal input from a video input terminal 1 is input as a write signal to a bit operation circuit 15, where a bit operation is performed between the signals and output. The signal output from the bit operation circuit 15 is input to the write buffer memory 3.

The signal output from the first read buffer memory 5 is input to the bit restoration circuit 16, and the bit restoration circuit 16 performs an operation opposite to that in which the bit operation between the signals is performed in the bit operation circuit 15. , And restores and outputs the signal. The signal output from the bit restoration circuit 16 is
It is output from the video output terminal 11 as a read signal. Similarly, the signal output from the second read buffer memory 7 is restored by performing the reverse operation of the bit operation between the signals in the bit restoration circuit 17, and the video output terminal is used as the second read signal. Output from 11.

Next, the operation of the bit operation circuit 15 and the bit restoration circuits 16 and 17 will be described with reference to FIG. FIG.
FIG. 3 is a diagram for explaining operations of a bit operation circuit and a bit restoration circuit. FIG. 5A shows an input signal of the bit operation circuit 15, and a signal having a 10-bit width is input every clock, with the input signal having a 10-bit width.

FIG. 5B shows an output signal of the bit operation circuit 15, which divides the input 10-bit width signal of the third clock into upper 5 bits and lower 5 bits, and divides the upper 5 bits into the 10-bit width signal of the first clock. And the lower 5 bits of the second clock
Combined with a 10-bit width signal, a 10-bit width 3 clock signal is
The bits are converted into a signal having a bit width of 2 clocks by manipulating the bits.

FIG. 5C shows the input signals of the bit restoration circuits 16 and 17. 15 bits for 2 out of 3 clocks
A width signal is input.

FIG. 5D shows the output signals of the bit restoration circuits 16 and 17, which are 15 of two clocks among the three input clocks.
Of the bit width signals, the upper 5 bits and lower 5 bits of the third clock synthesized at the first and second clocks are synthesized as a signal of the third clock, and a signal of 15 bits width 2 clocks is combined with a signal of 10 bits width 3 clocks. The bit is restored and output by performing the reverse operation of the bit operation circuit 15 so that

The output signal of the bit operation circuit 15 is input to the write buffer memory 3, and only two clocks out of three clocks are written by the control signal of the write control circuit 4. The number of data output from the write buffer memory 3 to the one-port memory 2 in one horizontal scanning period is ／ of the input video signal.

Similarly, the 1-port memory 2 to the first read buffer memory 5 and the second read buffer memory 7
The number of data output in one horizontal scanning period is 2/3 of the input video signal.

The first read buffer memory 5 and the second read buffer memory 5
In the reading of the read buffer memory 7, a signal of one horizontal scanning period can be restored by reading a signal of two clocks in three clock periods so that bit operations can be restored by the bit restoration circuits 16 and 17.

Since the number of input / output data to / from the one-port memory 2 during one horizontal scanning period is 2/3, the read frequency of the write buffer memory 3, the first read buffer memory 5, and the second read buffer memory 7 If the writing frequency is at least twice as high, one writing and two readings can be performed within one horizontal scanning period.

Next, an operation in which an electronic enlargement circuit and a cyclic noise reduction circuit are added will be described with reference to FIG. FIG. 6 is a block diagram showing the configuration of a video device with an image memory function including an electronic enlargement circuit and a cyclic noise reduction circuit. FIG. 6 is an electronic enlargement circuit corresponding to FIG.
13 and a cyclic noise reduction circuit 14 are added, and the same parts as those in FIG.

In FIG. 6, the first read signal output from the first read buffer memory 5 is an electronic magnifying circuit.
13 and is subjected to electronic enlarging processing.

The input video signal and the second read signal which is the output of the second read buffer memory 7 are input to the cyclic noise reduction circuit 14 and are delayed from the input video signal by one or more field periods. Performs a cyclic noise reduction process.

Since the input signals to the electronic magnifying circuit 13 and the cyclic noise reduction circuit 14 are different, the operations can be performed separately.

As described above, according to the second embodiment of the present invention, one write and two read operations are performed on the memory. The signal is converted to twice the frequency and written to the one-port memory, and the two-
Double-frequency reading is performed by inverting the frequency to twice the frequency with two read buffer memories and restoring the bit, thereby using a low-cost general one-port memory and inputting / outputting to / from the one-port memory. And a video device with an image memory function that realizes one writing and two reading while keeping the frequency low.

Further, it is possible to obtain a video device with an image memory function in which electronic enlargement processing is performed using the first read signal and cyclic noise reduction processing is performed independently using the second read signal.

(Third Embodiment) FIG. 7 is a block diagram showing a configuration of a video device with an image memory function according to a third embodiment of the present invention. 7, the same parts as those in the first embodiment and FIG. 1 are denoted by the same reference numerals, and their operations and functions are the same. FIG. 7 differs from FIG. 1 in that an electronic enlargement circuit 18 for performing electronic enlargement processing and a memory input / output control circuit 19 are provided.

In the following, the operation of the third embodiment of the present invention will be described mainly for parts different from the first embodiment. In FIG. 7, the first read buffer memory 5
The first read signal, which is the output of (1), is input to the electronic enlarging circuit 18 and is subjected to electronic enlarging processing. Electronic expansion circuit
Numeral 18 outputs a vertical read start line and a next line read control signal required for the electronic enlarging process to the memory input / output control circuit 19, and the memory input / output control circuit 19 outputs 1 according to the read start line and the next line read control signal. The read from the port memory 2 to the first read buffer memory 5 is controlled.

Next, control of the vertical read start line and the next line read control of the electronic enlarging circuit 18 will be described with reference to FIG. FIG. 8 is a diagram for explaining the operation of the vertical enlargement in the electronic enlargement circuit. That is, FIG. 8A shows the vertical enlargement of the electronic enlarging circuit 18, and the vertical control of the electronic enlarging process is performed in the vertical direction corresponding to the area necessary for enlargement in the video signal of one field period. A read start line is determined, and an area necessary for enlargement is read over one field period from the read start line. To read an area necessary for enlargement over one field period, the next line read control is performed.

FIG. 8B is a diagram for explaining the next line read control of the electronic enlarging circuit 18. When the next line read control signal is L, the read line control is performed for one horizontal scanning period. The next line is read every time. When the next line read control signal is H, the read line control does not read the next line but reads the same line as in the previous one horizontal scanning period.

Next, an operation in which a cyclic noise reduction circuit is added will be described with reference to FIG. FIG. 9 is a block diagram illustrating a configuration of a video device with an image memory function including an electronic enlargement circuit and a cyclic noise reduction circuit. FIG.
7 is obtained by adding a cyclic noise reduction circuit 14 to FIG. 7, and the same parts as those in FIG.

In FIG. 9, the input video signal and the second read signal which is the output of the second read buffer memory 7 are input to the cyclic noise reduction circuit 14 and are delayed by one or more field periods from the input video signal. A cyclic noise reduction process is performed on the read signal. Since the input signals of the electronic enlargement circuit 18 and the cyclic noise reduction circuit 14 are different, the operations can be performed separately.

As described above, according to the third embodiment of the present invention, one write and two read operations to the memory are performed.
The frequency is converted to double the frequency and written to the 1-port memory, and the read of the triple frequency from the 1-port memory is inversely converted to the frequency of 1 by the two read buffer memories, respectively. By controlling reading from the one-port memory so as to read only the vertical area necessary for enlargement, one-time writing and two-time reading can be realized using an inexpensive general one-port memory. It is possible to obtain a video device with an image memory function in which the vertical area control required for electronic enlargement is performed by the same one-port memory.

Further, it is possible to obtain a video device with an image memory function in which the cyclic noise reduction process is performed independently of the electronic enlargement process using the second read signal.

(Fourth Embodiment) FIG. 10 is a block diagram showing a configuration of a video device with an image memory function according to a fourth embodiment of the present invention. In FIG. 10, the second
4 and FIG. 4 are denoted by the same reference numerals, and their operations and functions are the same. FIG. 10 differs from FIG. 4 in that an electronic enlargement circuit 18 for performing electronic enlargement processing and a memory input / output control circuit 19 are provided.

In the following, the operation of the fourth embodiment of the present invention will be described mainly for parts different from the second embodiment. In FIG. 10, the first read buffer memory 5
The first readout signal, which is the output of (1), is input to the electronic enlargement circuit 18 via the bit restoration circuit 16, and is subjected to electronic enlargement processing. The electronic enlargement circuit 18 outputs a vertical read start line and a next line read control signal required for the electronic enlargement processing to the memory input / output control circuit 19, and the memory input / output control circuit 19 reads the read start line and the next line. Reading from the one-port memory 2 to the first read buffer memory 5 is controlled by a control signal.

Next, an operation in which a cyclic noise reduction circuit is added will be described with reference to FIG. FIG. 11 is a block diagram showing a configuration of a video device with an image memory function including an electronic enlargement circuit and a cyclic noise reduction circuit.
FIG. 11 differs from FIG. 10 in that a cyclic noise reduction circuit 14 is added, and the same parts as in FIG.

In FIG. 11, the input video signal and the second read signal output from the second read buffer memory 7 via the bit restoration circuit 17 are output from a cyclic noise reduction circuit.
The signal is input to the input video signal 14, and a cyclic noise reduction process is performed on the input video signal and the second read signal delayed by one or more field periods.

Since the input signals to the electronic enlarging circuit 18 and the recursive noise reduction circuit 14 are different, the operations can be performed separately.

As described above, according to the fourth embodiment of the present invention, since the writing to the memory is performed once and the reading is performed twice, the number of data is set to 2/3 by the bit operation and input to the write buffer memory. The signal is converted to twice the frequency and written to the one-port memory, and the two-
For double frequency reading, two read buffer memories inversely convert each frequency to a single frequency to perform further bit restoration, and for the first read signal, read only a vertical area necessary for electronic enlargement. By controlling the reading from the one-port memory, one-time writing and two-time reading are realized by using an inexpensive general one-port memory, and the vertical area control required for electronic enlargement is also performed. A video device with an image memory function performed by the same one-port memory can be obtained.

Further, it is possible to obtain an image device with an image memory function that performs the cyclic noise reduction processing using the second readout signal independently of the electronic enlarging processing.

(Fifth Embodiment) FIG. 12 is a block diagram showing the configuration of a video device with an image memory function according to a fifth embodiment of the present invention. In FIG. 12, the third
The same reference numerals are given to the same parts as in the embodiment and FIG. 7, and the operation and the operation are the same, so that the description of the operation is omitted. FIG. 12 differs from FIG. 7 in that an electronic enlargement circuit 20 for performing electronic enlargement processing and a first read control circuit 21 are provided.

Hereinafter, the operation of the fifth embodiment of the present invention will be described mainly for portions different from the third embodiment. In FIG. 12, a first read signal, which is an output of the first read buffer memory 5, is an electronic magnifying circuit 20.
And an electronic enlargement process is performed.

The electronic magnifying circuit 20 outputs a vertical read start line and a next line read control signal required for electronic magnifying processing to the memory input / output control circuit 19, and the memory input / output control circuit 19 reads the read start line. In addition, reading from the one-port memory 2 to the first reading buffer memory 5 is controlled by the next line reading control signal.

The electronic magnifying circuit 20 outputs a horizontal read start pixel and a next pixel read control signal required for the electronic magnifying process to the first read control circuit 21. First read buffer memory 5 according to a start pixel and next pixel read control signal
Is controlled.

Next, the read control in the vertical and horizontal directions of the electronic magnifying circuit 20 will be described with reference to FIG. FIG. 13 is a diagram for explaining an enlargement method of the electronic enlargement circuit. That is, FIG. 13A shows an enlargement method of the electronic enlargement circuit 20. The vertical control of the electronic enlargement processing is performed by controlling the vertical direction corresponding to the area necessary for enlargement in the video signal of one field period. Is determined, and an area necessary for enlargement is read over one field period from the read start line. To read an area necessary for enlargement over one field period, the next line read control is performed.

In the horizontal control of the electronic enlarging process, a corresponding horizontal read start pixel is determined from an area necessary for enlargement in a video signal in one horizontal scan period, and one horizontal scan period from the read start pixel. To read the area required for enlargement. To read an area necessary for enlargement over one horizontal scanning period, next pixel read control is performed.

FIG. 13B shows the next pixel read control of the electronic enlarging circuit 20. When the next pixel read control signal is at L, the read pixel control reads the next pixel every one pixel period. When the next pixel read control signal is H, the read pixel control does not read the next pixel but reads the same pixel as in the previous one pixel period.

Next, an operation in which a cyclic noise reduction circuit is added will be described with reference to FIG. FIG. 14 is a block diagram showing a configuration of a video device with an image memory function including an electronic enlargement circuit and a cyclic noise reduction circuit.
FIG. 14 is obtained by adding a cyclic noise reduction circuit 14 to FIG. 12, and the common parts to FIG.

In FIG. 14, the input video signal and the second
The second read signal output from the read buffer memory 7 is input to the cyclic noise reduction circuit 14, where a cyclic noise reduction process is performed on the input video signal and the second read signal delayed by one or more field periods. . Since the input signals to the electronic magnifying circuit 20 and the cyclic noise reduction circuit 14 are different, the operations can be performed separately.

As described above, according to the fifth embodiment of the present invention, one write and two read operations to the memory are performed.
The frequency is converted to double the frequency and written to the 1-port memory, and the read of the triple frequency from the 1-port memory is inversely converted to the frequency of 1 by the two read buffer memories, respectively. By controlling the reading from the one-port memory so as to read only the vertical area necessary for enlargement, and controlling the reading from the read buffer memory so as to read only the horizontal area necessary for electronic enlargement, One writing and two readings are realized by using an inexpensive general one-port memory, and the vertical area control required for electronic enlargement is also performed by the same one-port memory. It is possible to obtain a video device with an image memory function using a buffer memory for reading from a one-port memory.

Further, it is possible to obtain a video device with an image memory function in which the cyclic noise reduction process is performed independently of the electronic enlarging process using the second read signal.

(Sixth Embodiment) FIG. 15 is a block diagram showing a configuration of a video device with an image memory function according to a sixth embodiment of the present invention. In FIG. 15, the fourth
10 and FIG. 10 are denoted by the same reference numerals, and their operations and functions are the same. FIG. 15 differs from FIG. 10 in that an electronic enlargement circuit 20 for performing electronic enlargement processing and a first read control circuit 22 are provided.

Hereinafter, the operation of the sixth embodiment of the present invention will be described mainly for portions different from the fourth embodiment. In FIG. 15, a first read signal output from the first read buffer memory 5 is supplied to a bit restoration circuit 16.
Is input to the electronic enlarging circuit 20 through which the electronic enlarging process is performed.

The electronic enlargement circuit 20 outputs a vertical read start line and a next line read control signal required for electronic enlargement processing to the memory input / output control circuit 19, and the memory input / output control circuit 19 outputs the read start line. In addition, reading from the one-port memory 2 to the first reading buffer memory 5 is controlled by the next line reading control signal.

The electronic magnifying circuit 20 outputs a horizontal read start pixel and a next pixel read control signal required for the electronic magnifying process to the first read control circuit 22, and the first read control circuit 22 reads the read data. First read buffer memory 5 according to a start pixel and next pixel read control signal
Is controlled.

Since the signal written in the first read buffer memory 5 is bit-operated, the first read control circuit 22 is required to correspond to an arbitrary read start pixel.
It is necessary to control the timing of starting reading from the read buffer memory 5.

Next, horizontal read control of the first read control circuit 22 will be described with reference to FIG. FIG.
FIG. 6 is a diagram for explaining a read control method of the first read control circuit. That is, FIG. 16A shows a normal horizontal read control method of the first read control circuit 22, reads the first pixel from the read start timing, configures three pixels with two clocks by bit operation, and thereafter. The same operation is performed.

FIG. 16B shows a case where the read start pixel is shifted by one pixel with respect to FIG. 16A, and the read is started one clock earlier than the original read start, and the read start timing is the second. Is controlled so that the pixel of the output is output.

FIG. 16C shows a case where the read start pixel is shifted by 2 pixels from FIG. 16A, and the read is started two clocks earlier than the original read start, and the read start timing is the third. Is controlled so that the pixel of the output is output.

The signal subjected to the bit operation in this manner can correspond to an arbitrary read start pixel. It is needless to say that the same operation can be obtained by keeping the read start timing constant and using the delay circuit to switch the delay amount of the delay circuit corresponding to the read start pixel.

Next, an operation in which a cyclic noise reduction circuit is added will be described with reference to FIG. FIG. 17 is a block diagram showing a configuration of a video device with an image memory function including an electronic enlargement circuit and a cyclic noise reduction circuit.
17 is obtained by adding a cyclic noise reduction circuit 14 to FIG. 15, and the same parts as those in FIG.

In FIG. 17, an input video signal and a second read signal output from the second read buffer memory 7 via the bit restoration circuit 16 are supplied to a cyclic noise reduction circuit.
The signal is input to the input video signal 14, and a cyclic noise reduction process is performed on the input video signal and the second read signal delayed by one or more field periods. Since the input signals to the electronic magnifying circuit 20 and the cyclic noise reduction circuit 14 are different, the operations can be performed separately.

As described above, according to the sixth embodiment of the present invention, since one write and two read operations are performed on the memory, the number of data is reduced to 2/3 by a bit operation and input to the write buffer memory. The signal is converted to twice the frequency and written to the one-port memory, and the two-
For double frequency reading, two read buffer memories inversely convert each frequency to a single frequency to perform further bit restoration, and for the first read signal, read only a vertical area necessary for electronic enlargement. By controlling the reading from the one-port memory and controlling the reading from the reading buffer memory so as to read only the horizontal area necessary for the electronic enlargement, a low-cost general one-port memory can be used. One writing and two readings are realized, and the vertical area control necessary for electronic enlargement is performed by the same one-port memory.
A video device with an image memory function can be obtained in which horizontal area control is performed with a buffer memory for reading from a one-port memory.

Further, it is possible to obtain a video device with an image memory function in which the cyclic noise reduction process is performed independently of the electronic enlargement process using the second read signal.

(Seventh Embodiment) FIG. 18 is a block diagram showing a configuration of a video device with an image memory function according to a seventh embodiment of the present invention. In FIG. 18, the third
The same reference numerals are given to the same parts as in the embodiment and FIG. 7, and the operation and the operation are the same, so that the description of the operation is omitted. FIG. 18 differs from FIG. 7 in that an electronic enlargement circuit 20 for performing electronic enlargement processing and a memory input / output control circuit 23 are provided.

Hereinafter, the operation of the seventh embodiment of the present invention will be described mainly for portions different from the third embodiment. In FIG. 18, a first read signal output from the first read buffer memory 5 is input to an electronic enlarging circuit 20 and subjected to electronic enlarging processing.

The electronic enlarging circuit 20 outputs a vertical read start line and a next line read control signal necessary for the electronic enlarging process to the memory input / output control circuit 23.

The electronic enlargement circuit 20 outputs a horizontal read start pixel and a next pixel read control signal necessary for the electronic enlargement processing to the memory input / output control circuit 23.
The memory input / output control circuit 23 controls the 1-port memory 2
The read control in the vertical direction is performed by the read start line and the next line read control signal, the read control in the horizontal direction is performed by the read start pixel and the next pixel read control signal, and the read to the first read buffer memory 5 is controlled.

Next, an operation in which a cyclic noise reduction circuit is added will be described with reference to FIG. FIG. 19 is a block diagram showing a configuration of a video device with an image memory function including an electronic enlargement circuit and a cyclic noise reduction circuit.
19 is obtained by adding the cyclic noise reduction circuit 14 to FIG. 18, and the common parts to FIG. 18 are denoted by the same reference numerals, and the description of the operation is omitted.

In FIG. 19, the input video signal and the second
The second read signal output from the read buffer memory 7 is input to the cyclic noise reduction circuit 14, where a cyclic noise reduction process is performed on the input video signal and the second read signal delayed by one or more field periods. . Since the input signals to the electronic magnifying circuit 20 and the cyclic noise reduction circuit 14 are different, the operations can be performed separately.

As described above, according to the seventh embodiment of the present invention, one write and two read operations to the memory are performed.
The frequency is converted to double the frequency, written to the 1-port memory, and the read of the triple frequency from the 1-port memory is inversely converted to the frequency of 1 by the two read buffer memories, respectively. To read only the vertical and horizontal areas required for enlargement
By controlling reading from the port memory, one-time writing and two-time reading are realized using an inexpensive general one-port memory, and the vertical area control necessary for electronic enlargement is the same. An image device with an image memory function performed by a port memory can be obtained.

Further, it is possible to obtain a video device with an image memory function for performing the cyclic noise reduction processing independently of the electronic enlarging processing using the second read signal.

In the above description, the enlargement process in the vertical direction is performed by the read start line and next line read control, and the enlargement process in the horizontal direction is performed by the read start pixel and next pixel read control. It is needless to say that a method of directly controlling can be used.

It is needless to say that the first readout signal can be used not only for electronic enlargement processing but also for camera shake correction by electronic enlargement processing and camera shake correction in a marginal pixel CCD system.

Although the write and read buffer memories perform input and output to and from the buffer memory in units of one horizontal scanning period, the buffer memory is input to the memory in units of a period shorter than one horizontal scanning period (for example, in units of eight pixels). It goes without saying that the same operation can be obtained by a method of outputting data or inputting / outputting data to / from the buffer memory in units longer than one horizontal scanning period (for example, two horizontal scanning periods).

Although the one-port memory is an external memory, it goes without saying that the same operation can be obtained even if the one-port memory is built in the LSI.

Also, the 1-port memory may be an SRAM or a DR.
AM or a derivative of DRAM may be used. In the case of DRAM, the refresh operation is also controlled.

[0118]

As described above, the present invention has the following effects, as is apparent from the various embodiments described above.

(1) Writing once to memory and 2
In order to perform reading twice, the input signal is converted into triple the frequency by the write buffer memory and written into the one-port memory, and reading from the one-port memory at the triple frequency is performed twice by the two read buffer memories. by inverse transform to the frequency, to be able to provide an image memory function imaging device for realizing the reading of one write and two times using a general 1-port memory at a low cost Tomo
Performs an electronic enlarging process using the first readout signal,
Performs cyclic noise reduction using the second read signal
Providing a video device with an image memory function that is performed independently
Advantageous effect of wear can be obtained.

[0120]

[0121]

[0122]

( 2 ) One write to memory and 2
Times, the number of data is reduced to 2 by bit operation.
The input signal is converted to a double frequency by the write buffer memory as / 3 and written to the 1-port memory, and reading of the double frequency from the 1-port memory is inversely converted to a single frequency by the two read buffer memories. Image memory function that realizes one-time writing and two-time reading while using an inexpensive general 1-port memory and suppressing the frequency of input / output to the 1-port memory by performing further bit restoration. Can provide video equipment with
Together with the electronic readout processing using the first readout signal.
No, cyclic noise reduction processing using second read signal
Video device with image memory function that performs
The advantageous effect of being able to provide is obtained.

[0124]

[0125]

[0126]

( 3 ) One write to memory and 2
In order to perform reading twice, the input signal is converted into triple the frequency by the write buffer memory and written into the one-port memory, and reading from the one-port memory at the triple frequency is performed twice by the two read buffer memories. By converting back to the frequency, and controlling the reading from the one-port memory so as to read only the vertical area required for the electronic expansion for the first read signal,
A video device with an image memory function that realizes one-time writing and two-time reading using an inexpensive general one-port memory and controls the vertical area required for electronic enlargement with the same one-port memory it is possible to provide
Performs cyclic noise reduction processing using the second readout signal.
Video device with image memory function that is performed independently of formula enlargement processing
Advantageous effect can provide can be obtained.

[0128]

( 4 ) Writing once to memory and 2
Times, the number of data is reduced to 2 by bit operation.
The input signal is converted to a double frequency by the write buffer memory as / 3 and written to the 1-port memory, and reading of the double frequency from the 1-port memory is inversely converted to a single frequency by the two read buffer memories. By further performing bit restoration, and controlling the reading of the first read signal from the one-port memory so as to read only the vertical area necessary for electronic expansion, an inexpensive general one-port memory is used. , A video device with an image memory function can be provided that realizes one write and two read operations and also performs vertical area control required for electronic enlargement using the same one-port memory.
And a cyclic noise reduction process using the second read signal.
Image memory function that performs processing independently of electronic enlargement processing
An advantageous effect that an image device can be provided is obtained.

[0130]

( 5 ) One write to memory and 2
In order to perform reading twice, the input signal is converted into triple the frequency by the write buffer memory and written into the one-port memory, and reading from the one-port memory at the triple frequency is performed twice by the two read buffer memories. In addition to the inverse conversion to the frequency, the first read signal is controlled from the one-port memory so as to read only the vertical area necessary for electronic expansion, and only the horizontal area necessary for electronic expansion is controlled. By controlling reading from the reading buffer memory so as to perform reading, one-time writing and two-time reading are realized using an inexpensive general one-port memory, and a vertical area required for electronic enlargement is realized. Control is also performed by the same one-port memory, and horizontal area control is performed by the buffer memory for reading from the one-port memory. Advantageous effect can be provided with an image memory function imaging device performed in Li is obtained.

( 6 ) Further, an advantageous effect that an image device with an image memory function for performing the cyclic noise reduction processing using the second read signal independently of the electronic enlarging processing can be provided can be obtained.

( 7 ) One Write to Memory and 2
Times, the number of data is reduced to 2 by bit operation.
The input signal is converted to a double frequency by the write buffer memory as / 3 and written to the 1-port memory, and reading of the double frequency from the 1-port memory is inversely converted to a single frequency by the two read buffer memories. Then, the bit readout is further performed, and the readout from the one-port memory is controlled so that the first readout signal is read out only in the vertical direction area necessary for electronic expansion, and the horizontal area necessary for electronic expansion is controlled. By controlling reading from the reading buffer memory so that only reading is performed, one-time writing and two-time reading are realized using an inexpensive general one-port memory, and the vertical direction necessary for electronic expansion is realized. Area control is also performed by the same one-port memory, and the area control in the horizontal direction is performed by a buffer for reading from the one-port memory. Advantageous effect can be provided with an image memory function imaging device performed in Famemori is obtained.

( 8 ) Further, an advantageous effect is obtained that an image device with an image memory function can be provided which performs the cyclic noise reduction processing using the second read signal independently of the electronic enlarging processing.

( 9 ) One Write to Memory and 2
In order to perform reading twice, the input signal is converted into triple the frequency by the write buffer memory and written into the one-port memory, and reading from the one-port memory at the triple frequency is performed twice by the two read buffer memories. By controlling the reading from the one-port memory so as to read back only the vertical and horizontal areas necessary for the electronic expansion of the first read signal while converting the frequency back to the first read signal, an inexpensive general one-port memory is used. 1 using
It is possible to provide a video device with an image memory function that realizes writing twice and reading twice, and also performs vertical area control necessary for electronic expansion with the same one-port memory, and uses a second read signal to generate cyclic noise. Reduction
With image memory function that performs processing independently of electronic enlargement processing
An advantageous effect is obtained that a video device can be provided .

[0136]

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a video device with an image memory function according to a first embodiment of the present invention;

FIG. 2 shows a one-port memory, a write buffer memory, a first read and a second memory according to the first embodiment of the present invention.
FIG. 9 is a diagram for explaining the operation of the time-division processing of the read buffer memory;

FIG. 3 is a block diagram showing a configuration of a video device with an image memory function including an electronic enlarging circuit and a cyclic noise reduction circuit according to the first embodiment of the present invention;

FIG. 4 is a block diagram showing a configuration of a video device with an image memory function according to a second embodiment of the present invention;

FIG. 5 is a diagram for explaining operations of a bit operation circuit and a bit restoration circuit according to a second embodiment of the present invention;

FIG. 6 is a block diagram showing a configuration of a video device with an image memory function including an electronic enlargement circuit and a cyclic noise reduction circuit according to a second embodiment of the present invention;

FIG. 7 is a block diagram showing a configuration of a video device with an image memory function according to a third embodiment of the present invention;

FIG. 8 is a view for explaining an operation of vertical enlargement in an electronic enlargement circuit according to a third embodiment of the present invention;

FIG. 9 is a block diagram showing a configuration of a video device with an image memory function including an electronic enlargement circuit and a cyclic noise reduction circuit according to a third embodiment of the present invention;

FIG. 10 is a block diagram illustrating a configuration of a video device with an image memory function according to a fourth embodiment of the present invention;

FIG. 11 is a block diagram showing a configuration of a video device with an image memory function including an electronic enlargement circuit and a cyclic noise reduction circuit according to a fourth embodiment of the present invention;

FIG. 12 is a block diagram illustrating a configuration of a video device with an image memory function according to a fifth embodiment of the present invention.

FIG. 13 is a diagram for explaining an enlargement method in an electronic enlargement circuit according to a fifth embodiment of the present invention;

FIG. 14 is a block diagram showing a configuration of a video device with an image memory function including an electronic enlargement circuit and a cyclic noise reduction circuit according to a fifth embodiment of the present invention.

FIG. 15 is a block diagram showing a configuration of a video device with an image memory function according to a sixth embodiment of the present invention;

FIG. 16 is a diagram for explaining a read control method of a first read control circuit according to a sixth embodiment of the present invention;

FIG. 17 is a block diagram showing a configuration of a video device with an image memory function including an electronic enlarging circuit and a cyclic noise reduction circuit according to a sixth embodiment of the present invention;

FIG. 18 is a block diagram illustrating a configuration of a video device with an image memory function according to a seventh embodiment of the present invention.

FIG. 19 is a block diagram showing a configuration of a video device with an image memory function including an electronic enlarging circuit and a cyclic noise reduction circuit according to a seventh embodiment of the present invention;

FIG. 20 is a block diagram illustrating a configuration of a conventional video device with an image memory function.

[Explanation of symbols]

 1, 101 input terminal 2 1-port memory 3 write buffer memory 4, 103 write control circuit 5 first read buffer memory 6, 104 first read control circuit 7 second read buffer memory 8, 105 second read control circuit 9, 19 , 23 Memory input / output control circuit 10 Bidirectional buffer 11, 106 Output terminal 12, 109 Synchronization signal input terminal 13 Electronic expansion circuit 14 Cyclic noise reduction circuit 15 Bit operation circuit 16, 17-bit restoration circuit 18, 20 Electronic expansion Circuits 21, 22 First read control circuit 102 Field memory 107 Read start relative address 108 Read end relative address

Continuation of the front page (51) Int.Cl. ⁷ Identification symbol FI H04N5 / 92 H04N5 / 92H (56) References JP-A-10-136316 (JP, A) JP-A-11-66289 (JP, A JP-A-8-307760 (JP, A) JP-A-11-205731 (JP, A) JP-A-11-275426 (JP, A) JP-A-6-46317 (JP, A) 325745 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H04N 5/21-5/262 H04N 5/907-5/92 G06T 1/60 450

Claims (9)

(57) [Claims] 1. A one-port memory having an image storage capacity of one field or more, m (m ≧ 1 and a natural number) write buffer memories, and writing of the m write buffer memories is controlled. M write control units, n ( n ≧ 2 and a natural number) read buffer memories, n read control units for controlling reading of the n read buffer memories, and m write operations A memory input / output control unit that controls reading of a buffer memory for writing, writing of the n buffer memories for reading, and writing and reading of a memory of one port having a storage capacity of one field or more of images. Is written to the m write buffer memories by controlling the m write control units, and the control is performed by the memory input / output control unit. The read signals from the m write buffer memories are written to a one-port memory having the image storage capacity of one field or more, and the read signals are delayed from the one-port memory having the image storage capacity of one field or more. The read signals are read and written to the n read buffer memories, reading of the n read buffer memories is controlled by the n read control units, and read signals are output as video outputs. Writing to the m write buffer memories and the n read buffer memories so that only one write or read is performed in a time-division manner with respect to a one-port memory having a storage capacity of an image equal to or more than a field. Writing at m (m + n) times or more the frequency of reading data from The memory input / output control unit controls time-division (m + n) double-speed conversion so as to perform reading of a buffer memory and writing of the n read buffer memories, and further includes at least one read buffer. A video device with an image memory function, wherein a video output of a memory is subjected to an electronic enlargement process, and a video output of at least one other read buffer memory is subjected to a noise reduction process. 2. A one-port memory having an image storage capacity of one field or more, a video signal is input at a clock having the same frequency as the input video signal, and a certain clock among the input video signals is used. The input video signal is divided and m (m) bit operations are performed to combine the video signal of the divided clock with the video signal input by another clock.
.Gtoreq.1 and a natural number) a bit operation unit, m write buffer memories for inputting the output signals of the m bit operation units, and m write buffers for controlling the writing of the m write buffer memories The control unit and n ( n ≧ 2
And a natural number) of read buffer memories, n read control units for controlling reading of the n read buffer memories, and m read buffer memories for receiving output signals of the n read buffer memories. N bit restoring units for restoring a signal subjected to bit manipulation by the bit manipulation unit; reading of the m writing buffer memories, writing of the n reading buffer memories, and image data of one field or more. A memory input / output control unit for controlling writing and reading of a one-port memory having a storage capacity, wherein the bit operation unit performs a bit operation and then controls the m writing buffers to the m writing buffer memories. A write signal under control of the memory input / output control unit and a read signal of the m write buffer memories To the one-port memory having the image storage capacity of one field or more, and reading out the delayed signals from the one-port memory having the image storage capacity of one field or more to read the n read buffers. Writing to a memory, reading the n read buffer memories under the control of the n read control units, reading out the signals by the n bit restoring units, outputting the signals as video outputs, The memory input / output control unit controls time-division pseudo (m + n) double-speed conversion so that only one write or read operation is performed in a time-division manner with respect to a one-port memory having an image storage capacity of a field or more. So that
Further, the image output of at least one bit restoration unit is subjected to electronic enlargement processing, and the image output of at least one other bit restoration unit is subjected to noise reduction processing. With video equipment. 3. A one-port memory having an image storage capacity of one field or more, m (m ≧ 1 and a natural number) write buffer memories, and writing of the m write buffer memories is controlled. M write control units, n ( n ≧ 2 and a natural number) read buffer memories, n read control units for controlling reading of the n read buffer memories, and m write operations Input / output control unit for controlling the reading of the buffer memory for writing, the writing of the n read buffer memories, and the writing and reading of a one-port memory having an image storage capacity of one field or more, and an electronic enlargement control And writing the video input to the m write buffer memories by controlling the m write control units. Under the control of the output control unit, the read signals of the m write buffer memories are written to the one-port memory having the storage capacity of the image of one field or more, and the read signal of the one having the storage capacity of the image for one field or more is written. The delayed signal is read from the port memory and written to the n read buffer memories, and the read of the n read buffer memories is controlled by the n read control units, and the read signal is output as a video output. In addition, the writing to the m writing buffer memories and the n writing to the n writing buffer memories are performed such that only one writing or reading is performed in a time-division manner with respect to the one-port memory having the image storage capacity of one field or more. (M + n) times or more of the frequency for reading data into the read buffer memory The memory input / output control unit performs time division (m + n) double-speed conversion by controlling the memory input / output control unit to perform reading of the m write buffer memories and writing of the n read buffer memories. Controlling the memory input / output control unit so that writing to at least one of the n read buffer memories is an arbitrary vertical area required for electronic enlarging processing. A video device with an image memory function, wherein the video output of at least one other read buffer memory is subjected to noise reduction processing, wherein the video output is cut out in the vertical direction. 4. A one-port memory having an image storage capacity of one field or more, a video signal is input with a clock having the same frequency as the input video signal, and a certain clock among the input video signals is used. The input video signal is divided and m (m) bit operations are performed to combine the video signal of the divided clock with the video signal input by another clock.
.Gtoreq.1 and a natural number) a bit operation unit, m write buffer memories for inputting the output signals of the m bit operation units, and m write buffers for controlling the writing of the m write buffer memories The control unit and n ( n ≧ 2
And a natural number) of read buffer memories, n read control units for controlling reading of the n read buffer memories, and m read buffer memories for receiving output signals of the n read buffer memories. N bit restoring units for restoring a signal subjected to bit manipulation by the bit manipulation unit; reading of the m writing buffer memories, writing of the n reading buffer memories, and image data of one field or more. A memory input / output control unit for controlling writing and reading of a one-port memory having a storage capacity; and an electronic enlarging control unit, wherein the bit operation unit performs a bit operation and the m write buffer memories The writing is controlled by the m write controllers, and the m write buffers are controlled by the memory input / output controller. A memory read signal is written to a one-port memory having an image storage capacity of one field or more, and a delayed signal is read from a one-port memory having an image storage capacity of one field or more, and the n signals are read out. , And the reading of the n read buffer memories is controlled and read by the n read control units, and the signals are restored by the n bit restore units and output as video outputs. At the same time, the memory input / output control unit controls so that only one write or read is performed in a time-division manner with respect to a one-port memory having a storage capacity of an image of one field or more, and a time-division pseudo (m + n) Double speed conversion is performed, and at least one of the n read buffer memories is read out by the electronic enlargement control unit. The memory input / output control unit is controlled so that writing into the buffer memory is performed in an arbitrary vertical direction necessary for the electronic enlarging process, thereby performing vertical cutting, and further, at least one other bit. A video device with an image memory function, wherein the video output of the restoration unit is subjected to a noise reduction process. 5. A one-port memory having an image storage capacity of one field or more, and m (m ≧ 1 and a natural number)
A write buffer memory and the m write buffers
M write controls to control the writing of buffer memory
Part and n (n ≧ 1 and natural number) read buffers
Memory and reading of the n read buffer memories
N read control units for controlling readout, and the m write controls
And reading of the n pieces of buffer memory
Buffer memory writing and images for one or more fields
1-port memory writing and storage with image storage capacity
Memory input / output control unit to control reading and electronic expansion
And a control unit , the video input to the m buffer memories for writing
writing by controlling with m write control units;
The m write buffers are controlled by the input / output control unit.
The read signal of the memory
Writing to a one-port memory having an image storage capacity,
One port with more than one field of image storage capacity
Reading the delayed signal from the memory and reading the n
Writing to the buffer memory for reading, and
The reading of the buffer memory is performed by the n read control units.
Output readout signal as video output
In addition, one port having an image storage capacity of one field or more is provided.
Only one write or read to the default memory
The m write buffers so that
A buffer for writing to the memory and the n read buffers
(M + n) times or more of the frequency for reading to memory
Read the m write buffer memories at the above frequency.
Reading and writing of the n read buffer memories
Control by the memory input / output control unit so that
To perform time-division (m + n) double-speed conversion, and the electronic readout control unit
To at least one read buffer memory
Writing in any vertical direction required for electronic magnification processing
The memory input / output control unit is controlled to
Make a cutout in the vertical direction, and at least one
The reading of the reading buffer memory of the
To reduce the horizontal area to any
At least one read buffer memory
One of the n read control units is controlled to perform horizontal cutting.
A video device with an image memory function, characterized in that the video device performs the output . 6. At least one other reading buffer.
The video device with an image memory function according to claim 5, wherein the video output of the memory is subjected to a noise reduction process . 7. A storage capacity of an image for one field or more.
1 port memory and the same frequency as the input video signal
The video signal is input at the clock of the wave number, and the input video
Divide the video signal input by a certain clock among the signals
Input the video signal of the divided clock with another clock
M bits (m
≧ 1 and a natural number), and the m bits
M write buffers for inputting output signals from the operation unit
Memory and the m write buffer memories
Write control units for controlling the write operation, and n write control units (n ≧ 1)
And a natural number) read buffer memory, and n
Control the reading of the read buffer memory
Read control unit and the n read buffer
The output signal of the memory is input and the m bit operation units
N bit restoration units for restoring a signal subjected to a bit operation
Reading the m write buffer memories;
Writing of the n read buffer memories and one buffer
1-port memo with image storage capacity
Memory I / O control to control writing and reading of memory
It said m after performing the control unit, and an electronic enlargement control unit, the bit manipulation by the bit manipulation unit
Write control to said write buffer memory
Write by controlling the memory input / output control unit
Read from the m write buffer memories
The signal has a storage capacity of the image of one field or more.
Write to 1 port memory, more than 1 field
Delayed from 1-port memory with storage capacity of image
Reading out a signal and reading said n readout buffer memories
And read the n read buffer memories.
The readout is controlled by controlling the readout by the n readout control units.
Then, the signal is restored by the n bit restoration units, and the image is output.
As well as one port having an image storage capacity of one field or more.
Only one write or read to the default memory
Is controlled by the memory input / output control unit so that
To perform time-division pseudo (m + n) double-speed conversion
In the large control unit, among the n read buffer memories,
Write to at least one read buffer memory
Only the vertical area required for electronic enlarging.
To control the memory input / output control unit to
Cutting out and further reading the at least one
Readout of buffer memory is required for electronic enlargement processing
At least one of the horizontal areas.
Readout corresponding to the readout buffer memories
A video apparatus with an image memory function, characterized in that a control section is controlled to cut out in a horizontal direction . 8. The image of another at least one bit restoration unit.
The video device with an image memory function according to claim 7, wherein the image output is subjected to a noise reduction process . 9. A one-port memory having an image storage capacity of one field or more, m (m ≧ 1 and a natural number) write buffer memories, and writing of the m write buffer memories is controlled. M write control units, n ( n ≧ 2 and a natural number) read buffer memories, n read control units for controlling reading of the n read buffer memories, and m write operations Input / output control unit for controlling the reading of the buffer memory for writing, the writing of the n read buffer memories, and the writing and reading of a one-port memory having an image storage capacity of one field or more, and an electronic enlargement control And writing the video input to the m write buffer memories by controlling the m write control units. Under the control of the output control unit, the read signals of the m write buffer memories are written to the one-port memory having the storage capacity of the image of one field or more, and the read signal of the one having the storage capacity of the image for one field or more is written. The delayed signal is read from the port memory and written to the n read buffer memories, and the read of the n read buffer memories is controlled by the n read control units, and the read signal is output as a video output. In addition, the writing to the m writing buffer memories and the n writing to the n writing buffer memories are performed such that only one writing or reading is performed in a time-division manner with respect to the one-port memory having the image storage capacity of one field or more. (M + n) times or more of the frequency for reading data into the read buffer memory The memory input / output control unit performs time division (m + n) double-speed conversion by controlling the memory input / output control unit to perform reading of the m write buffer memories and writing of the n read buffer memories. Controlling the memory input / output control unit so that writing to at least one of the n read buffer memories becomes an arbitrary area necessary for the electronic enlarging process, and A video device with an image memory function, wherein the video output from at least one other read buffer memory is subjected to noise reduction processing, wherein the video data is cut out in the horizontal direction.