JPH11341351A - Video magnification and reduction circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To convert resolution without damaging the image quality of an original image. SOLUTION: A sampling clock generation circuit 51 changes the frequency of a sampling clock CLK of an A/D converter 2, in accordance with a horizontal scan frequency of a signal Vin so that one line of the input video signal Vin is sampled by a standard number of pixels. A read address generation circuit 53 calculates a vertical address after expansion or reduction and reads each pixel data in lines, which are the closest and the second closest to the address from memories 3a and 3b. An interpolation operation circuit 4 performs linear interpolation operation based on two read pixel data and calculates pixel data after conversion.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus, such as a projection display apparatus, which performs an enlargement / reduction process on an input video signal different from a predetermined standard pixel number so as to match the standard pixel number. It relates to a scaling circuit.

[0002]

2. Description of the Related Art A projection display device for enlarging and projecting a computer image, a video image or the like on a screen has been known. The resolution of commercially available computers that generate input video signals for this projection type display device is various.
800 × 600 pixels, VGA (Vid
In eo Graphics Array), the size is 640 × 480 pixels. Therefore, for example, when an SVGA signal is input to a VGA projection display device and projected, the resolution is set to 6
It is necessary to convert to 40 × 480 pixels for display.

[0003]

As described above, in order to cope with various input video signals, it is necessary to convert the resolution. However, when simple thinning is performed, there is a problem in that a horizontal line having a thickness of one pixel is completely cut off, or a part of a character is missing, thereby deteriorating image quality. SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a video enlargement / reduction circuit capable of converting resolution without deteriorating the image quality of an original image.

[0004]

According to the present invention, an input video signal whose horizontal pixel number is different from a predetermined standard pixel number is expanded to match the standard pixel number. An image enlargement / reduction circuit for performing reduction processing, comprising: a low-pass filter receiving the input image signal; an A / D converter for converting an output of the low-pass filter into a digital signal in synchronization with a sampling clock; And a control circuit for changing the frequency of the sampling clock in accordance with the horizontal scanning frequency of the input video signal so that one line is sampled with the standard number of pixels. As described above, by changing the frequency of the sampling clock according to the horizontal scanning frequency of the input video signal, it is possible to perform horizontal resolution conversion. According to a second aspect of the present invention, there is provided an image enlargement / reduction circuit for performing an enlargement / reduction process on an input video signal whose number of pixels in a vertical direction is different from a predetermined standard number of pixels so as to match the standard number of pixels. A storage circuit for storing the digitized input video signal, and a vertical address after scaling based on the vertical scaling ratio. The control circuit includes a control circuit that reads out pixel data from a storage circuit, and an interpolation calculation circuit that performs a linear interpolation calculation based on two pieces of pixel data read from the storage circuit and obtains pixel data after scaling. As described above, the vertical address after scaling is obtained based on the vertical scaling ratio, and linear interpolation is performed based on each pixel data in the line closest to this address and the next line. , Vertical resolution conversion can be performed. Further, as set forth in claim 3, the storage circuit includes two memories for alternately storing the digitized input video signal line by line, and the control circuit includes the two storage devices. The pixel data is read from each memory at the same time.

[0005]

Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram of a projection display device showing an embodiment of the present invention. The projection display device according to the present embodiment includes a low-pass filter (hereinafter abbreviated as LPF) 1 that receives an input video signal Vin;
A / D converter 2 for converting the output of LPF 1 into a digital signal in synchronization with sampling clock CLK, scan conversion for generating a video signal of a frequency and timing suitable for a liquid crystal panel, which will be described later, and a resolution suitable for the liquid crystal panel. Memory 3 for performing resolution conversion for generating a video signal
a, 3b, an interpolation operation circuit 4 for performing a linear interpolation operation on the basis of two pixel data read from the memories 3a, 3b to obtain pixel data after scaling, and an input video signal Vi.
n according to the horizontal scanning frequency of the sampling clock CL.
While changing the frequency of K, a vertical address after scaling is obtained based on the vertical scaling ratio, and the pixel data in the line closest to this address and the next closest line are read from the memories 3a and 3b. Read control circuit 5
A signal processing circuit 6 for performing digital processing such as contour emphasis on the video data output from the interpolation arithmetic circuit 4, a D / A converter 7 for converting the video data output from the signal processing circuit 6 into an analog signal, , A liquid crystal projector 8 that converts a video signal output from the D / A converter 7 into optical information and projects the optical information on a screen (not shown).

The interpolation operation circuit 4 determines whether the data output from the memories 3a and 3b is to be output as it is or replaces it according to the control signal CTL, and determines from the output value of the A output terminal of the swap circuit 41 A subtracter 42 for subtracting the output value of the B output terminal, a multiplier 43 for multiplying the output value of the subtracter 42 by the interpolation operation coefficient K, and adding the output value of the B output terminal of the swap circuit 41 to the output value of the multiplier 43 And an adder 44 that performs the operation. And
The control circuit 5 includes a sampling clock generation circuit 51 for generating a sampling clock CLK and an A / D converter 2
A write address generating circuit 52 for generating a write address signal WA for writing the video data output from the memory 3a, 3b to the memories 3a, 3b, and read address signals RA1, RA2 for reading the video data from the memories 3a, 3b.
It comprises a control signal CTL and a read address generation circuit 53 for generating an interpolation operation coefficient K.

Next, the operation of such a projection type display device will be described. An input video signal (analog RGB signal) Vin output from a computer (not shown) is input to the A / D converter 2 through the LPF 1. A / D converter 2
The input video signal V is synchronized with the sampling clock CLK output from the sampling clock generation circuit 51.
in is converted to a digital signal.

At this time, the standard number of pixels in the horizontal direction, that is, the number of horizontal pixels of the liquid crystal panel used in the liquid crystal projector 8 is 640 for VGA, and the input video signal Vi
When n is the SVGA standard, the number of input pixels protrudes. Therefore, the sampling clock generation circuit 51
Is such that one horizontal line of the input video signal Vin is sampled at the standard number of pixels regardless of the number of pixels.
The frequency of the sampling clock CLK is changed according to the horizontal scanning frequency of the input video signal Vin.

When the sampling clock CLK is not synchronized with the video signal, jitter appears on the screen, making the screen very hard to see. Therefore, the sampling clock generation circuit 51 generates a sampling clock CLK by dividing the horizontal synchronization signal of the input video signal Vin by a PLL circuit (not shown), and synchronizes the sampling clock CLK with the video signal.

As described above, the horizontal resolution of the input video signal Vin can be converted so as to match the standard number of pixels. However, 800 pixels in the horizontal direction are 640
If the resolution of the original image that is sampled by pixels is high, the pixels of the input video signal Vin are thinned. Therefore, in the present embodiment, the LPF 1 is provided in a stage preceding the A / D converter 2, and as shown in FIG.
By reducing the frequency of n to some extent, a complete thinning phenomenon can be prevented.

Next, the vertical resolution conversion will be described. Since the vertical direction is not a temporally continuous signal,
The linear interpolation is performed by the memories 3a and 3b and the interpolation operation circuit 4, and the operation in real time is enabled so as to be applicable to a moving image. In this embodiment, two memories 3a and 3b are provided for this linear interpolation operation, and the write addresses generation circuit 5 is provided for the memories 3a and 3b.
2 to provide a write address signal WA,
The video data output from the / D converter 2 is stored in a memory 3a,
Write to 3b.

At this time, video data is alternately written to the memories 3a and 3b for each horizontal line by the write address signal WA. For example, if the first line is written to the memory 3a, the next line is written to the memory 3b.

Next, the read address generation circuit 53
It generates read address signals RA1 and RA2 based on the read address y as in the following equation. y = an + b (1) In equation (1), a is a vertical scaling ratio,
If the standard number of pixels in the vertical direction, that is, the number of vertical pixels of the liquid crystal panel is Mref, and the number of vertical pixels of the input video signal Vin is M, then a = M / Mref. This enlargement / reduction ratio a can take a value below the decimal point.

N is an output pixel number (horizontal line number after resolution conversion), and takes a value of 0, 1, 2,..., Mref -1. b is an output start address serving as a start value of the read address y, and is equal to the start value of the write address in the vertical direction.

The interpolation operation circuit 4 performs a linear interpolation operation as shown by the following equation on the basis of the data output from the memories 3a and 3b in accordance with the read address signals RA1 and RA2, and outputs the output data D _outn (n = 0). , 1,2, ..., Mre
f-1) is output. D _outn = (1−K) D _n + KD _{n + 1} = K (D _{n + 1} −D _n ) + D _n (2)

In the equation (2), K is a coefficient of the interpolation operation, and is a value after the decimal point of the address y obtained by the equation (1). Further, D _n is the pixel data stored memory 3a, the 3b, the vertical address is the pixel data specified by the integer value of the address y (optional horizontal address). Similarly, D _{n + 1} is the pixel data stored in the memories 3a and 3b, and the vertical address is the pixel data specified by the integer value of the address y + 1 (the horizontal address is the same as D _n). ). Note that the integer value of the address y is obtained by rounding down the decimal point of the address y.

In order to realize the interpolation operation as shown in the equation (2), the read address generation circuit 53
Control signal CTL for controlling data replacement processing by
Is output. The swap circuit 41 determines whether to output the data output from the memories 3a and 3b as they are or to replace them in accordance with the control signal CTL. At this time, the read address generation circuit 53
Pixel data D _{n + 1} from the A output terminal of 1 is output, the pixel data D _n from the B output terminal for generating a control signal CTL as output.

The subtracter 42 calculates D _{n + 1} -D _n , that is, the pixel data D output from the A output terminal of the swap circuit 41.
Subtract pixel data D _n output from the B output terminal from _{n + 1} . The multiplier 43 adds the read address generating circuit 53 to K (D _{n + 1} −D _n ), that is, the output value D _{n + 1} −D _n of the subtractor 42.
Is multiplied by the interpolation operation coefficient K output from the. The adder _{44, K (D n + 1 -D} n) + D n, i.e. the multiplier 4
The pixel data D _n output from the B output terminal of the swap circuit 41 is added to the output value K (D _{n + 1} −D _n ) of _No. 3. In this way, the linear interpolation operation of Expression (2) can be realized.

Next, an example of such a linear interpolation operation will be described with reference to FIG. In FIG. 3, D ₀ to D ₇ are pixel data written memory 3a, and 3b by the write address signal WA of the write address in the vertical direction is "0" to "7" (the pixel data D ₀ to D ₇ Horizontal position is the same). Here, it is assumed that the pixel data D ₀ in the first one line has been written to the memory 3a and the pixel data D ₁ in the next one line has been written to the memory 3b. Similarly, it is assumed that pixel data D ₂ , D ₄ , and D ₆ are written in the memory 3a, and pixel data D ₃ , D ₅ , and D ₇ are written in the memory 3b.

The white circles in FIG. 3 indicate pixel data written in the memories 3a and 3b, the black circles indicate output data D _outn after the interpolation operation, and the circles blacked out by half are black. shows both the output data D _{ou tn} memory 3a, and the pixel data written to 3b. FIG. 3 shows a case where the standard number of pixels Mref in the vertical direction is 480 pixels and the number M of vertical pixels of the input video signal Vin is 600 pixels. Therefore, the enlargement / reduction ratio a is 5/4. Also, since the start value of the vertical write address is “0”, the output start address b of the read address y
Is also “0”.

First, in the output pixel number n = 0, that is, in the first line, the read address y is (5/4) × 0 + 0 = 0, and the interpolation operation coefficient K is also 0 according to the equation (1). When the pixel data specified by the integer value of the address y is stored in the memory 3a, the read address generation circuit 53 reads the read address signal RA1 (the horizontal direction) in which the vertical address value represents the integer value of the address y. Is output to the memory 3a. Also,
A read address signal RA2 (the horizontal address is the same as RA1) whose vertical address value represents the integer value of the address y + 1 is output to the memory 3b.

Here, since the integer value of the address y is 0, the address of the memory 3a is 0 (the horizontal address is arbitrary).
, Pixel data D ₀ is read out, and pixel data D ₁ is read out from the address 1 of the memory 3b (the horizontal address is the same as the memory 3a). Subsequently, when the pixel data specified by the integer value of the address y is stored in the memory 3a, the read address generation circuit 53 sends the control signal CTL instructing the data exchange to the swap circuit 41.
Output to

In response to the control signal CTL, the swap circuit 41 interchanges the pixel data D ₀ and D ₁ , outputs the pixel data D ₁ from the A output terminal, and outputs the pixel data D ₀ from the B output terminal. The operations of the subtractor 42, the multiplier 43, and the adder 44 are as described above. Thus, the output data D _{out0 of} the output pixel number n = 0 is calculated as shown in FIG. By repeating the above-described interpolation operation for each pixel data while changing the horizontal address indicated by the read address signals RA1 and RA2, the processing of the first line is completed.

In the next one line (output pixel number n = 1), the read address y is (5/4) × 1 + 0 = 1 + (1
/ 4), and the interpolation calculation coefficient K is １ ／. When the pixel data specified by the integer value of the address y is stored in the memory 3b, the read address generation circuit 53 reads the read address signal RA2 (the horizontal direction) in which the vertical address value represents the integer value of the address y. Is output to the memory 3b. Further, a read address signal RA1 (the horizontal address is the same as RA2) in which the vertical address value represents the integer value of the address y + 1 is output to the memory 3a.

Here, since the integer value of the address y is 1, address 1 of the memory 3b (the horizontal address is arbitrary).
, The pixel data D ₁ is read out, and the pixel data D ₂ is read out from the address 2 of the memory 3a (the horizontal address is the same as the memory 3b). Subsequently, when the pixel data specified by the integer value of the address y is stored in the memory 3b, the read address generation circuit 53 sends the control signal CTL not instructing the data replacement to the swap circuit 4
Output to 1.

By the control signal CTL, the swap circuit 41 does not exchange the pixel data D ₂ and D ₁ ,
The pixel data D ₂ is output from the A output terminal, and the pixel data D ₂ is output.
₁ is output from the B output terminal. Subtractor 42, multiplier 43
The operation of the adder 44 is as described above. Thus, the output data D _{out1 of} the output pixel number n = 1 is calculated as shown in FIG.

By repeating the above-described interpolation calculation for each pixel data while changing the horizontal address indicated by the read address signals RA1 and RA2, the processing of the second line is completed. Hereinafter, in the same operation, the output data D of the output pixel number n = 2, 3,.
_outn can be obtained sequentially.

Next, the signal processing circuit 6 includes the interpolation arithmetic circuit 4
Performs digital processing such as contour emphasis on the video data output from. The D / A converter 7 converts the video data output from the signal processing circuit 6 into an analog signal, and outputs the analog signal to the liquid crystal projector 8. Thus, the liquid crystal projector 8
The video signal is converted into optical information and projected on a screen (not shown), whereby a computer image is projected on the screen.

Although the present embodiment has been described with reference to a monochrome image, the LPF 1, the A / D converter 2, the memories 3a and 3b, the interpolation operation circuit 4, the signal processing circuit 6, and the D
Needless to say, by providing the / A converter 7 for each of R, G, and B, the present invention can be applied to a color image. Further, in the present embodiment, the projection type display device is described as an example, but it goes without saying that the present invention can be applied to other than the projection type display device.

[0030]

According to the present invention, the horizontal resolution is changed by changing the frequency of the sampling clock of the A / D converter according to the horizontal scanning frequency of the input video signal. Conversion can be performed, A / D
By providing a low-pass filter before the converter,
It is possible to suppress a decrease in image quality.

According to another aspect of the present invention, a vertical address after enlargement / reduction is obtained based on a vertical enlargement / reduction ratio, and each pixel data in a line closest to this address and a line next to the address are obtained. By performing a linear interpolation operation based on the above, resolution conversion in the vertical direction can be performed while suppressing a decrease in image quality.

Further, as described in claim 3, a storage circuit is constituted by two memories for alternately storing the input video signal line by line, and two pixel data are simultaneously read out from each memory, thereby obtaining a linearity. The interpolation operation can be performed in real time.

[Brief description of the drawings]

FIG. 1 is a block diagram of a projection display device showing an embodiment of the present invention.

FIG. 2 is a diagram for explaining horizontal resolution conversion processing;

FIG. 3 is a diagram for explaining a vertical resolution conversion process;

[Explanation of symbols]

1: low-pass filter, 2: A / D converter, 3a, 3b
... memory, 4 ... interpolation operation circuit, 5 ... control circuit, 6 ... signal processing circuit, 7 ... D / A converter, 8 ... liquid crystal projector,
41: swap circuit, 42: subtractor, 43: multiplier, 4
4 ... Adder, 51 ... Sampling clock generation circuit, 5
2. Write address generation circuit 53: Read address generation circuit

Claims (3)

[Claims] 1. An image scaling circuit for scaling an input video signal whose horizontal number of pixels is different from a predetermined standard number of pixels so as to match the standard number of pixels. A low-pass filter for receiving, an A / D converter for converting an output of the low-pass filter into a digital signal in synchronization with a sampling clock, and an input video signal such that one line of the input video signal is sampled with the standard number of pixels. A control circuit for changing a frequency of the sampling clock according to a horizontal scanning frequency of a signal. 2. An image enlargement / reduction circuit for performing enlargement / reduction processing on an input image signal having a vertical pixel number different from a predetermined standard pixel number so as to match the standard pixel number. A storage circuit for storing the input video signal, and a vertical address after scaling based on the vertical scaling ratio is obtained, and each pixel data in the line closest to this address and the next closest line is read from the storage circuit. An image enlargement / reduction circuit comprising: a control circuit for reading; and an interpolation operation circuit for performing a linear interpolation operation based on two pixel data read out from a storage circuit to obtain pixel data after enlargement / reduction. 3. The video enlargement / reduction circuit according to claim 2, wherein the storage circuit comprises two memories that store the digitized input video signal alternately for each line. Is a circuit for simultaneously reading the two pixel data from each memory.