JPS61245775A - Horizontal address generating circuit of digital special effect device - Google Patents

Abstract

PURPOSE:To obtain the titled device operating address generation for horizontal time axis converting processing of a data sampled in high speed while using a low speed clock and suitable for handling the data in a high frequency rate by generating an address at a low speed in a vertical blanking period, writing it in a memory and applying high speed read when the video period starts. CONSTITUTION:A clock I produced from a clock generating circuit 12 is a clock in a sampling frequency, corresponds to a picture element of an input data, uses a 1/16 counter 13 to decrease the frequency to 1/16 to form a clock II, the result is inputted to a reference counter 7, a register 5, an address genera tor 8 and a speed conversion memory 11, and an SH being a ratio of the picture element of the original sample to after reduction (or magnification) is added by SIGMASH circuits 4, 5, the result is compared with the output of the reference counter 7, and when the value is equal, the address of the address generator 8 is revised. Then an output of a synchronous separation circuit 14 is obtained and it is written in the speed conversion memory 11 at a low speed while forming an address during the vertical blanking period.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a horizontal address generation circuit in a digital special effects device.

[Conventional technology]

With the development of digital technology, video signals are digitized, the signals are temporarily stored in memory, and after a certain period of time,
Digital special effects devices have been developed that produce special screen effects by reading this signal and converting it back to the original analog signal.

In this type of device, an image with both the horizontal and vertical components reduced or enlarged is written into the memory. Since the present invention is directed to the operation control of reduction or enlargement of the horizontal component, the following will be explained. The horizontal component reduction +C will be explained. As shown in FIG. 2, the horizontal component is reduced by a buffer memory 1, an interpolator 2, and a horizontal address generation circuit 3a. That is, the SH determined from the screen reduction ratio is based on data from the key shaver or the A/D controller for control:
(It is calculated by a computer. sH consists of an adder 4 and a register 5 and is added to the circuit. The output ΣSH of the register 5 is incremented by SH each time a match/grace is generated from the comparator 6. Comparator 6 compares the integer part of ΣSH with the output of a reference carantuff operating at standard clock speed, and when the values are equal, generates a match pulse.This match pulse is generated by the horizontal When it is necessary to create data by interpolation, the weighting factor for horizontal interpolation is the fractional part of ΣSH at that point. Each new value created by this interpolation is It is written to buffer memory 1 below the address.

At last, the coincidence signal issues a command to the address generator 8 to increment the write address in the memory 1 by 1, and holds that value until the next write.

In this way, each time a match A pulse occurs, the interpolator 2 interpolates the pixel data and writes this data to the buffer memory 1, thereby constructing a reduced image in the memory.

On the other hand, 3b in FIG. 2 is a horizontal address generation circuit on the read side, and its configuration is similar to the horizontal address generation circuit 3a on the write side. This horizontal address generation circuit 3b controls the operation of the buffer memory 1 and the interpolator 9, and when SH is 1, the stored contents of the buffer memory are read out to obtain a reduced image signal. 10 is a converter that converts an analog video signal into a digital signal. Note that in order to obtain an enlarged image, the writing side circuit 3a is
Operate with H=1, and set the circuit 3b on the reading side to S H
= Operate in a state other than 1.

[Problem that the invention seeks to solve]

The above-described conventional horizontal address generation circuit has the disadvantage that it is unsuitable for handling data at a high frequency rate because the clock for processing input data and the clock for generating addresses are the same.

The present invention solves the above-mentioned problems by writing pixel data at low speed during the vertical retrace processing period, switching to readout from the start of the video period, and reading out using the original clock. This is what we provide.

[Means for solving problems]

The present invention includes a ΣsH circuit that adds SH, which is the ratio of the position of a pixel of input data to a pixel after reduction or enlargement, and an address generator that outputs a write address for reduced or enlarged pixel data stored in a buffer memory. , summed SH
A comparator that compares the integer part of the integer with the output of the reference counter and updates the write address of the address generator when the values match, a speed conversion memory that performs writing and reading by switching the speed, and a sampling frequency command to lower the frequency to a low frequency, update the address and write to the speed conversion memory at low speed during the vertical retrace processing period, switch to readout from the time the video period starts, and read out using the standard clock. This is a horizontal address generation circuit for a digital special effects device, characterized in that it has a control section that generates a horizontal address.

〔Example〕

L-1 lower f Pvr of the 11th day of the day on the tree? - I will pay tribute to you.

In FIG. 1, 1 is a buffer memory, 2 and 9 are interpolators, and 10 is an N0 converter.

Incidentally, since the reduction/enlargement ratio of the screen is a value determined for one field (one screen), it does not change for each scanning line. Therefore, the present invention utilizes this fact to generate an address at low speed during the vertical retrace period, write it into memory, and read it at high speed at the start of the video period, thereby increasing the horizontal time of data sampled at high speed. Address generation for axis conversion processing can be calculated using a low-speed clock.

That is, the present invention provides an adder 4 that adds SH, which is the ratio of the position of a pixel of input data to that of a pixel after reduction (or enlargement).
and the register 5 (ΣSH circuit), and the address generation circuit 8 that outputs the write address of the reduced (or enlarged) pixel data stored in the buffer memory 1, the total is tL7'
a comparator 6 that compares the integer part of cSo with the output of the reference counter 7 and updates the write address of the address generator 8 when the values match;
The speed conversion memory 11 performs reading, the sampling frequency is lowered to a low frequency, the address is updated at low speed during the vertical retrace processing period, and writing is performed in the speed conversion memory 11, and at the time the video period starts. It has a control section that controls high-speed reading.

The control section includes a clock generation circuit 12 that generates a clock at a sampling frequency, and a 1/6 counter 1 that lowers this clock to a frequency of 1716 and generates a clock.
3, and a synchronization separation circuit 14 that generates horizontal, vertical, and e-ruses.
It consists of 3b' is a circuit 6 for reading out the contents stored in the buffer memory l, and its configuration is the same as the circuit 3a/ surrounded by a dotted line.

In the embodiment, the clock generated by the clock generation circuit 12 is a clock with a sampling frequency, which corresponds to a pixel of human data (original sampling), and is
The counter 13 lowers the frequency to l/16 and sets it as a clock ■. This clock ■ is input to the reference counter 7, the register 5, the address generator 8, and the speed conversion memory 11, and under this low-speed clock ■, SH which is the ratio of the pixel position after reduction (or enlargement) to the original ΣSH circuit 4,
5, the addition result is compared with the output of the reference counter 7, and when the values are equal, a coincidence pulse is generated, and the address of the address generator 8 is updated at the noculus.

Since the horizontal address obtained in this way has a reduction ratio (or enlargement ratio) of a fixed value for one field (one screen), the data does not change for each scanning line. Therefore, the output of the synchronization separation circuit 14 is obtained, and during the vertical retrace processing period, writing is performed at low speed in the speed conversion memory 11 while creating an address as described above.
At the point when the video period starts, that is, at the vertical blanking point of the synchronization separation circuit 14, the speed conversion memory 11
is switched to readout, the readout is performed using the original clock, and this is used as the address of the buffer memory 1. As a result, even if input data is sampled at high speed, arithmetic processing for address generation can be performed at low speed.

In addition, in order to obtain an enlarged image, the writing side circuit 3a is
Operate with H=1 and readout circuit 3b with S a =
Operate in a state other than 1.

〔Effect of the invention〕

As explained above, the present invention generates an address at a low speed during the vertical retrace period, writes it into the memory, and performs a high-speed readout at the beginning of the video period. This has the advantage that address generation for conversion processing can be calculated using a low-speed clock, and a device suitable for handling data at a high frequency rate can be provided.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is a block diagram showing a conventional example. l... Buffer memory, 4... Adder (Σ1 circuit)
, 5...Register (ΣSH circuit), 6...Comparator,
7... Reference counter, 8... Address generator, 11
... Speed conversion memory, 12... Clock generation circuit (control section), 13... 1716 counter (control section), 1
4...Synchronization separation circuit (control section). Patent applicant: NEC Corporation -;-1-4,2C

Claims (1)

[Claims] (1) A ΣS_H circuit that adds S_H, which is the ratio of the position of a pixel of input data to that of a pixel after reduction or enlargement, and an address generator that outputs a write address for reduced or enlarged pixel data stored in a buffer memory; Totaled S_
A comparator that compares the integer part of H with the output of the reference counter and updates the write address of the address generator when the values match, a speed conversion memory that performs writing and reading by switching speeds, and sampling. Lower the frequency to a low frequency, update the address and write to the speed conversion memory at low speed during the vertical retrace processing period, switch to read from the point at which the video period starts, and issue a command to read with the standard clock. 1. A horizontal address generation circuit for a digital special effects device, comprising a control section that generates a horizontal address.