JPH09247588A - Horizontal picture element number conversion circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a conversion circuit of a picture element number in a horizontal direction capable of A/D conversion by an almost fixed clock frequency without depending on the frequency of clocks for generating input signals. SOLUTION: The clocks of the frequency sufficiently higher than the original clocks for generating the input signals are generated, the input signals are band-limited and then A/D converted and signal processings for appropriately performing the interpolation processing of picture elements are executed by a digital LPF 15 and a peaking circuit 16. The interpolation processing between two adjacent points and the generation of the write control signals of a memory 18 are performed in an interpolation means 17 and the picture element number is converted without damaging picture quality before conversion.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to conversion of the number of pixels in electronic devices such as liquid crystal displays and plasma displays.

[0002]

2. Description of the Related Art Conventionally, when displaying a signal generated from a computer or the like as an input signal on a matrix drive type display element such as a liquid crystal panel or a plasma panel, the number of pixels of the original input signal and the display element If the number of pixels does not match, a clock having the same frequency as the clock for generating the input signal is reproduced, the input signal is A / D converted using the clock as a sampling clock, and the number of pixels is converted by digital signal processing. For the operation of converting the number of pixels, see, for example, "Electronic Display Forum 95 Lectures" edited by SEMI Japan, pages 90 to 95 (TFT LCD monitor display system / Hiroyuki Mano System Development Laboratory, Hitachi, Ltd.). The gradation integration reduction display method shown is given as an example.

A conventional horizontal pixel number conversion circuit will be described below with reference to the drawings. FIG. 7 is a circuit diagram showing the configuration of a conventional horizontal pixel number conversion circuit. P from the input signal
The LL circuit 2 is for faithfully reproducing the clock that generated the input signal (this exists inside the computer main body), and it is necessary to know the number of clocks per horizontal synchronization in advance. It is also necessary to be able to adjust the phase difference from the clock a reproduced by the PLL circuit 2. In recent years, the signals output from computers have been diversified, and the clock frequency is wide, from about 20 MHz to over 100 MHz. In addition, even if the number of effective display pixels is the same in any two computers, 1 including the blanking period is included.
The number of clocks per horizontal sync is not always the same. The frequency of the oscillation frequency of the PLL circuit 2 is determined by the fact that the person using the computer or the software for the computer outputs the signal at what clock frequency and at what number of clocks per horizontal synchronization. The number of clocks per horizontal synchronization must be wide, and there are many setting values to be stored in advance.

When the internal operation of the gradation integration display circuit 3 is expressed by a mathematical expression, Q (i) = D (i) × a + D (i + 1)
X b + D (i + 2) x c + D (i + 3)
X d. Here, Q (i) is the i-th data after pixel number conversion, D (i), and D (i + 1), D (i +
2) and D (i + 3) are the i-th before conversion and (i +
These are 1) th, (i + 2) th, and (i + 3) th data. For example, the values of a, b, c, and d in the input signal are values determined by the ratio of the number of pixels before and after conversion of the number of pixels, and are obtained by calculating the contribution rate of the data before conversion to the data after conversion. . FIG. 8 shows an example of gradation integration display when converting 5 pixels to 4 pixels. As shown in FIG. 8, the five pixels before conversion are divided into four equal parts, and the brightness values of the respective areas are integrated to obtain a new brightness value of four pixels. The information originally possessed by one pixel is reflected in one or two pixels after the conversion of the number of pixels.

[0005]

As described above, in order to faithfully reproduce the clock that generated the input signal, a high-performance PLL circuit capable of supporting a wide oscillation frequency range is required.
In addition, since the number of clocks per horizontal synchronization is also wide, the number of setting values that should be stored in advance increases, and it is almost impossible to cover all of them, so have the user adjust it. I have no choice but to take a method.

In view of the above problems, the present invention provides a horizontal pixel number conversion circuit which does not require accurate knowledge of the number of clocks per horizontal synchronization of a signal output from a computer.

[0007]

In order to solve the above-mentioned problems, the horizontal pixel number conversion circuit of the present invention uses a 1-pixel input video signal.
In order to convert the number of pixels per horizontal synchronization into a desired number of pixels, a clock having a frequency higher than the clock that generated the input video signal is used as a sampling clock of the A / D converter to change the number of pixels in the horizontal direction. The number of pixels is once increased to a desired number or more, and the number of pixels is reduced to a desired number of pixels while performing interpolation processing between pixels.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A horizontal pixel number conversion circuit according to claim 1 of the present invention generates the video signal in order to convert the number of pixels per horizontal synchronization of an input video signal into a desired number of pixels. The number of pixels in the horizontal direction is temporarily increased to the desired number of pixels or more by using a clock having a frequency higher than the clock as the sampling clock of the A / D converter, and the number of pixels is set to the desired number while performing interpolation processing between pixels. The feature is that the number of pixels is reduced, and the frequency of the clock that generates the video signal output from the computer (the number of clocks per horizontal synchronization) and its phase (phase difference from the video signal) are accurate. Since there is no need to know in advance, there is no need for pre-adjustment of circuits or prior investigation of signal systems such as computers
It is possible to realize stable pixel number conversion for any signal.

An embodiment of the present invention will be described below.
This will be described with reference to FIGS. 1, 2, 3, 4, 5, and 6.

(Embodiment 1) In FIG.
Reference numerals 2 and 13 denote low-pass filters (hereinafter referred to as LPFs) each including an analog element, and input video signals R and
It limits the G and B bands. Reference numeral 14 is for A / D converting the video signal (R2) after band limitation. Reference numeral 10 denotes a PLL circuit that generates a clock from the horizontal synchronization H, and in this embodiment, it is assumed that it oscillates at about 80 MHz. The signal that has passed through the A / D converter 14 is output with its band further limited by the digital LPF 15 (R4). The signal A is a signal for controlling the pass band of the digital LPF 15.

Therefore, the digital LPF 15 will be described with reference to FIG.
A specific circuit example and its operation will be described. In FIG. 2, only one system of the signals (R, G, B) having three systems is described for simplification, but the remaining two systems have the same circuit. FIG.
, 19, 20, 21, 22 are flip-flops, 23, 24, 25 are amplifiers, 26, 27 are adders,
28 is a selector. Flip-flops 19 and 20
When the adder 26 and the amplifier 23 are written by using z transformation, y = (1+ [z−2]) / 2 ([z−2] represents the reciprocal of the square of z. Hereinafter, a natural number n
For z, the reciprocal of the n-th power of z is written as [z−n], and the flip-flops 21 and 22, the adder 27 and the amplifiers 24 and 25 similarly have y = (1 + 2 × [ z-1] + [z-2]) /
The filter of 4 is configured. When the control signal A is at L level, only the filter after the selector 28 is effective. When the signal A is at H level, the operation of all the elements in FIG. 2 is effective, that is, y = (1 + 2 × [z−1] + 2 × [z−2] +2
The resulting LPF is x [z-3] + [z-4]) / 8. Which level the control signal A is set to depends on the conversion rate of the pixel number conversion. For example, A / D
If the ratio of the number of pixels after A / D conversion by the converter 14 and the number of pixels to be finally obtained is 2 or less, it is desirable that the control signal A be L level, and if it is 2 or more, H level. In this configuration, the band switching of the digital LPF 15 is made only in two stages for simplification, but it is of course possible to increase the number of band switching selectable within the range allowed by the circuit scale.

Reference numeral 16 in FIG. 1 is a peaking circuit for amplifying high frequency components of an image. The signal B is a signal for controlling the amplification degree of the high frequency component in the peaking circuit 16. A specific circuit example and operation of the peaking circuit 16 will be described with reference to FIG. In FIG. 3, for simplification, only one system of the signals of three systems (R, G, B) is described, but the remaining two systems have the same circuit.

In FIG. 3, 29 and 30 are flip-flops,
34 and 36 are adders, and 31, 32, 33 and 35 are amplifiers, and the signal amplification degree C by the amplifier 35 is controlled by the control signal B. A limiter 37 limits the output of the adder 36. Flip-flops 29, 3
0 and amplifiers 31, 32, 33, 35 and adder 3
4 forms a high-pass filter, which is expressed as y = (-1 + 2 * [z-1]-[z-2]) / C. A signal in which the high frequency component is amplified is obtained by adding the high frequency component and the output of the flip-flop 29 by the adder 36.

Reference numeral 17 in FIG. 1 is a circuit for interpolating between two adjacent pixels and generating a write control signal for the memory 18. A specific circuit example and operation of the interpolation means 17 will be described with reference to FIGS. FIG. 4 shows an embodiment of the interpolation means of the horizontal pixel number conversion circuit of the present invention, and FIG. 5 shows an embodiment of the coefficient generation circuit 42 used for the interpolation means. In the present embodiment, in FIG. 4 and FIG. 5, an interpolating means for performing an interpolating process between adjacent pixels and a control means for generating a write control signal for performing write control of the memory in order to make a desired number of pixels. A configuration having both functions of and will be described. Further, in FIG. 4, for simplicity, R,
Only one of the three systems of G and B is described, but the remaining two systems are the same. However, the coefficient generation circuit 4
2 may be common to 3 systems.

In FIG. 4, 38 is a flip-flop, 39 is a subtractor, 40 is a multiplier, 41 is an adder, and 42 is a multiplier 4.
0 input signal k and memory 18 write control signal W
It is a coefficient generation circuit for generating E. The multiplier 39 multiplies a 9-bit signed signal ((ba) in the figure) and an 8-bit unsigned signal (k in the figure). Although the output is 17 bits, the lower 8 bits are truncated and only the upper 9 bits are connected to the adder 41. Here, the coefficient generation circuit 42
A specific configuration example of the above will be described with reference to FIG.

In FIG. 5, 44 and 50 are flip-flops with a set, whichever the input to the flip-flop,
When the signal / RST in the figure is at L level, H level is output at the next rising edge of the clock. Reference numerals 45, 46 and 52 denote flip-flops with reset, which output L level at the next rising edge of the clock when the signal / RST in the figure is L level, regardless of the input to the flip-flop.
Reference numerals 43, 51 and 53 are selectors. 42 and 48 are adders, 42 is 2 bits and 48 is 8 bits. Four
Reference numerals 9 and 47 are NAND gates, and 55 is an AND gate. Reference numeral 54 denotes a counter, which counts clocks with the set value U as a frequency division ratio and outputs a negative signal for each frequency division ratio. H input to the AND gate is a horizontal synchronizing signal, which has a negative polarity here.

Here, a method of setting the conversion ratio of the number of pixels will be described. When the ratio of the number of pixels after A / D conversion and the number of pixels after conversion in the A / D converter 14 is before conversion: after conversion = 11: 3, the ratio 11/3 is 3.6666. Yes, the decimal part is 0.6666, and the integer part is 3. Interpolation means 1
7, the input signal M of the adder 48 of the coefficient generation circuit 42
Is set to the fractional part of the above conversion rate. Specifically, since M is an 8-bit signal, M = 0.6666 × 256 = 170.66
Since it is 66 (about 171), it is set to 171 (256 is 2 to the 8th power).
The select signal RS of the selector 53 constituting the coefficient generating circuit 42 of FIG. 5 is set to 1 when the integer part of the conversion rate is 2 or more, and is set to 0 when it is less than 2. When the number of bits of V is n, the set value V of the selector 43 is set to a value obtained by subtracting (integer part-1 of conversion rate) from 2 n. In the present configuration example, the set value V is n = 2 bits, so V = 4− (3-1) = 2. The input signal U set in the counter 54 sets a numerator value by reducing the fraction when the number of pixels before conversion is the numerator and the number of pixels after conversion is the denominator. In the present embodiment, the fraction is 11/3, which is a reduced value, so the set value U
Is 11. The counter 54 exists because the fractional part M of the conversion rate includes an error. The calculation result of the decimal part M does not always become an integer as in the above setting. Therefore, the accumulated value of the set value M formed by the flip-flop 52 and the adder 48 accumulates errors as the accumulation progresses, and an appropriate coefficient k cannot be obtained. In order to prevent such error accumulation, a counter 54 is provided to generate a signal that initializes the interpolation process at an appropriate timing.

Since it is desirable to initialize the interpolation process every horizontal synchronization, the negative horizontal synchronization signal H and the counter 54 are used.
Of the initialization signal /
RST. The operation of the circuit in such a setting will be described later with reference to the timing chart of FIG.

In FIG. 1, reference numeral 18 denotes a memory having a sufficient capacity to store pixels for one horizontal synchronization after the conversion of the number of pixels, which is written in synchronization with the clock (CLK), but the write control signal WE is It is not written at the L level.

An example of the operation of the horizontal pixel number conversion circuit having the above configuration will be described with reference to FIGS. 1, 4 and 5 which are circuit diagrams and FIGS. 6 and 7 as timing diagrams. The setting is 1 after A / D conversion of the input signal as described above.
It is assumed that the ratio of the number of pixels per horizontal synchronization and the number of pixels after the pixel number conversion operation is 11: 3. Further, the signals (for example, R and R2) in FIG. 6 indicate the signals at the locations described in FIGS. 1, 4 and 5. For simplicity, only the signal R will be described, but the same applies to the signals G and B.

CLK is a signal generated by the PLL circuit 10 in FIG. 1, and is 80 MHz in this embodiment. It is independent of the clock that originally generated the input signal R.

The input signal R is a signal input from a computer or the like, and is generally a square wave as shown in FIG. Since the signal R2 has passed through the analog LPF 11, the wide-range component of the input signal R is cut (in FIG. 6, since the input signal R is a square wave, the rising and falling edges are smooth). Has become a signal like). R3 in FIG. 6 is obtained by A / D converting R2.

R3 is input to the digital LPF 15 of FIG. Here, the signal A for controlling the digital LPF 15
In the present embodiment, the ratio of the number of pixels after A / D conversion to the pixel to be finally obtained is 11/3 = 3.6666, and the integer part is 2 or more, so it is set to H level.

Therefore, the output signal R4 of the digital LPF 15 is y = (1 + 2 × [z-1] + 2 × [z-2] +2 with respect to the signal R3.
The signal has a filter of × [z−3] + [z−4]) / 8 applied (FIG. 6).

The digital LPF 15 is an interpolating means 1 in the subsequent stage.
Since 7 is a linear interpolation between two points, it is indispensable for proper interpolation processing. However, since high frequencies are cut, when it is displayed as it is, a signal rich in high frequency components such as characters is displayed. In addition, the outline is blurred. Therefore, the peaking circuit 16 amplifies high frequency components such as the outline of characters,
Improve image quality. The signal b is a signal after the high frequency component amplification. The control signal B of the peaking circuit 16 is a signal for controlling the amplification degree of the amplifier 35 in FIG. 3, but here the amplification degree is 1 (that is, the signal passes through the amplifier 35). Therefore, the peaking circuit is a filter circuit of y = -1 + 3 * [z-1] + [z-2], and the output result b is as shown in FIG.

The signal b is input to the interpolation means 17 in FIG. The signal a is the output of the flip-flop 38 in FIG. 4 (internal configuration diagram of the interpolation means 17). (Ba) is an output obtained by subtracting the signal a from the signal b by the subtractor 39 of FIG.

The output signals k and WE of the coefficient generating circuit 42 in FIG. 4 will be described with reference to FIGS. 5 and 7. Since the conversion rate is 3.6666 (= 11/3), RS = 1, V =
2, and the frequency division ratio U of the counter 54 is set to U = 11 because 11 pixels are converted into 3 pixels. In this case, the output signal and WE are as shown in FIG. For reference, / RST is also added. Since / RST has the division ratio of the counter 54 of 11, it becomes L every 11 locks.

In FIG. 4, the multiplier 40 multiplies the output k of the coefficient generating circuit 42 and the output of the multiplier 39. The result is originally 17 bits (signed), but the lower 8 bits are truncated. In the adder 41, the signal a and the higher 9 bits of the multiplier 40 are added, and this is input to the memory 18 in FIG. 1 (signal c). Not all the signal c is written in the memory 18, but writing is performed only when the signal WE generated by the coefficient generation circuit 42 is H. Therefore, when the stored contents of the memory 18 are continuously read at the timing of the signal WE, the final result signal d is obtained. In order to make it easier to compare the digital signal d with the input signal R, a diagram with the digital value of d as the vertical axis is also shown (described below the digital signal d in FIG. 6).

With this configuration, the frequency of the sampling clock for A / D conversion can be set arbitrarily even if the number of pixels per horizontal synchronization of the video signal generated from a computer or the like is unknown. On the other hand, no ecology is required, and moreover, proper pixel number conversion can be obtained.

[0030]

As described above, according to the horizontal pixel number conversion circuit of the present invention, it is not necessary to know in advance the method of the input signal, the original clock frequency that generated the input signal, and the phase thereof, and the A / D conversion Since the sampling frequency can be set arbitrarily, the oscillation frequency of the PLL circuit can be made substantially constant, so that the horizontal pixel number conversion circuit can perform an appropriate pixel number conversion without requiring the PLL circuit to have high performance. Can be provided.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a horizontal pixel number conversion circuit according to a first embodiment of the present invention.

FIG. 2 is a digital LP according to the first embodiment of the present invention.
Circuit diagram of F

FIG. 3 is a circuit diagram of a peaking circuit according to the first embodiment of the present invention.

FIG. 4 is a circuit diagram of an interpolation unit and a control unit according to the first embodiment of the present invention.

FIG. 5 is a circuit diagram of a coefficient generation circuit according to the first embodiment of the present invention.

FIG. 6 is a timing chart showing the operation of the horizontal pixel number conversion circuit according to the first embodiment of the present invention.

FIG. 7 is a circuit diagram of a horizontal pixel number conversion circuit according to a conventional technique.

FIG. 8 is a diagram for explaining the operation of horizontal pixel number conversion in the conventional technique.

[Explanation of symbols]

10 PLL circuit 11, 12, 13 Analog LPF 14 A / D converter 18 Memory 19, 20, 21, 22, 29, 30, 38, 44, 4
5,46,50,52,56 Flip-flop 26,27,34,36,41,42,48 Adder 23,24,25,31,32,33,35 Amplifier 28,43,51,53 Selector 37 Limiter 39 Subtractor 40 Multiplier 47, 49 NAND gate 55 AND gate

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Nio Kameoka 1-1, Matsushita-cho, Ibaraki-shi, Osaka Matsushita AV Technology Co., Ltd.

Claims (4)

[Claims] 1. A clock having a higher frequency than the clock that generated the video signal is used as a sampling clock of the A / D converter in order to convert the number of pixels per horizontal synchronization of the input video signal into a desired number of pixels. Therefore, the horizontal pixel number conversion circuit is characterized in that the number of pixels in the horizontal direction is increased and the number of pixels is set to a desired number while performing interpolation processing between pixels. 2. A PLL circuit for generating a clock locked to a horizontal synchronizing signal at a frequency higher than that of a clock for generating an input video signal, and the clock from the PLL circuit for converting the input video signal into a digital signal. A
/ D converter, a memory for storing pixel data for one horizontal synchronization, an interpolating means arranged between the A / D converter and the memory for performing an interpolation process between adjacent pixels, and the number of pixels And a control means for generating a write control signal for performing write control of the memory in order to set the desired number of pixels. 3. The horizontal pixel number conversion circuit according to claim 2, further comprising a high frequency emphasizing circuit connected in front of the interpolating means in order to compensate for a high frequency component of a pixel which is damaged by the interpolation processing between pixels. 4. A counter for generating an initialization signal for initializing the interpolating means for each value of the numerator after reduction of the fraction with the number of pixels after A / D conversion as the numerator and the desired number of pixels as the denominator. The horizontal pixel number conversion circuit according to claim 2, further comprising: