JP2006003481A - Image size conversion apparatus and image pickup apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To variously convert an image size horizontally and vertically through a simple structure, in the application to an electronic still camera for example, concerning an image size conversion apparatus and an image pickup apparatus. <P>SOLUTION: Reducing an image size horizontally is accomplished by arranging a memory circuit 5 on line memories 25A-25E and a vertical filter 9 for changing the size vertically, following a horizontal filter 8 for reducing the image size horizontally. Enlarging the image size horizontally is performed by arranging the vertical filter 9 and the horizontal filter 8 in succession after the memory circuit 5. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an image size conversion device and an imaging device, and can be applied to, for example, an electronic still camera. In the present invention, in the case of reducing the image size in the horizontal direction, a horizontal circuit for reducing the image size in the horizontal direction is followed by a memory circuit using a line memory and a vertical filter for changing the size in the vertical direction. When enlarging the image size in the direction, the image size can be variously converted in the horizontal direction and the vertical direction with a simple configuration by sequentially arranging the vertical filter and the horizontal filter after the memory circuit. Like that.

  2. Description of the Related Art Conventionally, in an electronic still camera or the like, image data is converted by a so-called image size conversion circuit and image data is output so as to correspond to a liquid crystal display panel or the like that is an image output target. In such an image size conversion circuit, generally, the image data is processed by a two-dimensional filter circuit via a frame memory, thereby setting the sampling pitch of the image data to a desired sampling pitch and converting the image size. It is made to do.

  With regard to such an image size conversion circuit, for example, Japanese Patent Application Laid-Open No. 8-223479 proposes a method for enlarging and reducing the image size only in the horizontal direction. That is, in this method, when the image is reduced, the image data is interpolated by the interpolation circuit, and then the clock frequency is converted using the dual port line memory. In this method, the connection between the interpolation circuit and the line memory is switched, the clock frequency is converted in advance in the line memory, and then the image data is interpolated by the interpolation circuit.

  However, the dual port line memory has a large shape, and the configuration disclosed in Japanese Patent Laid-Open No. 8-223479 has a problem that the overall shape is increased. There is also a problem that the image size can be converted only in the horizontal direction.

In recent years, however, image sensors have been provided with various pixel numbers, and liquid crystal display panels have been provided with various pixel numbers. . Accordingly, an image size conversion device having a simple configuration capable of converting various image sizes with high image quality in the horizontal direction and the vertical direction is desired.
JP-A-8-223479

  The present invention has been made in consideration of the above points, and intends to propose an image size conversion device and an imaging device capable of converting image sizes in various directions in a horizontal direction and a vertical direction with a simple configuration. is there.

  In order to solve this problem, the invention of claim 1 is applied to an image size conversion device that converts the image size of input image data and outputs output image data, and has at least three or more line memories. The plurality of line memories are sequentially and cyclically selected and sequentially input image data is recorded in the line memory, and a plurality of lines of image data are simultaneously received from the remaining line memories of the plurality of line memories. A memory circuit that reads out and outputs in parallel, and a vertical filter that changes the image size of the image data in the vertical direction by interpolating the image data of the plurality of lines output from the memory circuit. A horizontal filter that changes the image size of the image data in the horizontal direction by outputting the image data after interpolation processing When the change in the image size by the horizontal filter is a reduction in the image size, the input image data is input to the horizontal filter, the output data of the horizontal filter is input to the memory circuit, and the output of the vertical filter circuit When data is output as the output image data, and the change in the image size by the horizontal filter is an enlargement of the image size, the input image data is input to the memory circuit, and the output data of the vertical filter is input to the horizontal filter. A switch circuit for inputting and outputting the output data of the horizontal filter as the output image data.

  According to a sixth aspect of the present invention, there is provided an imaging means for acquiring an imaging result, and changing output image data by changing an image size based on input image data obtained by the imaging means in response to an operation of an operator. The image size conversion circuit includes at least three or more line memories, and sequentially circulates the plurality of line memories. A memory circuit for recording image data selected and sequentially input in the line memory, and simultaneously reading out and outputting a plurality of lines of image data from the remaining line memories of the plurality of line memories; The image data of the plurality of lines output from the memory circuit is subjected to an interpolation calculation process, whereby the image size of the image data is set in the vertical direction. The vertical filter to be changed, the continuous image data is subjected to interpolation calculation processing and output, and the horizontal filter to change the image size of the image data in the horizontal direction, and the change in the image size by the horizontal filter In the case of reduction, the input image data is input to the horizontal filter, the output data of the horizontal filter is input to the memory circuit, the output data of the vertical filter circuit is output as the output image data, and the horizontal filter When the change in the image size is an enlargement of the image size, the input image data is input to the memory circuit, the output data of the vertical filter is input to the horizontal filter, and the output data of the horizontal filter is input to the output image data As a switching circuit.

  According to the configuration of claim 1, when applied to an image size conversion device and the change in image size by the horizontal filter is reduction of the image size, the input image data is input to the horizontal filter, and the output of the horizontal filter When the data is input to the memory circuit, the output data of the vertical filter circuit is output as the output image data, and the change in the image size by the horizontal filter is an enlargement of the image size, the input image data is input to the memory circuit. If the switch circuit for inputting the output data of the vertical filter to the horizontal filter and outputting the output data of the horizontal filter as the output image data is provided, the image size is reduced in the horizontal direction. In this case, the image data whose number of samplings per line has been reduced by reducing the image size is recorded in a memory circuit and dropped. When the image size can be enlarged by the circuit, the image size of the vertical method is changed by the memory circuit and the vertical filter before the number of sampling is increased by the enlargement of the image size, and then the image is processed by the horizontal filter. Thus, the image size can be variously enlarged and reduced by a memory circuit having a small capacity, and the image size can be converted variously in the horizontal and vertical directions with a simple configuration.

  Thus, according to the configuration of the sixth aspect of the present invention, it is possible to provide an imaging apparatus capable of variously changing the image size in the horizontal direction and the vertical direction with a simple configuration regarding the electronic zoom processing.

  According to the present invention, the image size can be variously converted in the horizontal direction and the vertical direction with a simple configuration.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings as appropriate.

(1) Configuration of Embodiment FIG. 1 is a block diagram showing an electronic still camera according to an embodiment of the present invention. The electronic still camera 1 captures a desired subject with an image sensor 2 which is a solid-state imaging device such as a CCD (Charge Coupled Device) or CMOS (Complementary Metal-Oxide Semiconductor), and monitors a moving image and a still image based on the imaging result. 3 and recorded on a recording medium (not shown). Further, the imaging result recorded in the recording medium in this way is displayed on the monitor 3. As a result, the image sensor 2 sequentially outputs imaging results under the control of a drive circuit (not shown).

  The camera signal processing circuit 4 performs analog-digital conversion processing on the imaging result and executes processing such as white balance adjustment, and then converts it into image data D1 using a luminance signal and a color difference signal and outputs the image data to the image size conversion circuit 5.

  The monitor 3 converts the image data D2 based on the luminance signal and the color difference signal output from the image size conversion circuit 5 by a data processing circuit (not shown) into image data based on the color signal, and then drives the liquid crystal display panel. Is displayed.

  The image size conversion circuit 5 variously changes the image size of the image data D2 output from the camera signal processing circuit 4 and outputs it under the control of a controller (not shown). Here, the image size conversion circuit 5 is configured to be able to change the image size conversion process in various ways so that it can be commonly used for image sensors and monitors with various numbers of pixels. The image size by the image sensor 2 is changed to an image size corresponding to the number of pixels of the monitor 3. In the electronic still camera 1, electronic zoom and H reversal processing can be executed by effectively utilizing various image size changing functions by the image size conversion circuit 5.

  Therefore, the image size conversion circuit 5 changes the image size in the horizontal direction by the horizontal filter 8, and changes the image size in the vertical direction by the memory circuit 7 and the vertical filter 9. Further, when the image size is enlarged in the horizontal direction by the switch circuit 10 and the switch circuit 11 provided on the input side of the memory circuit 7, the image data output from the camera signal processing circuit 4 is directly input to the memory circuit 7. On the contrary, when the image size is reduced in the horizontal direction, the image data output from the camera signal processing circuit 4 is input to the memory circuit 7 via the horizontal filter 8. A vertical filter 9 is provided at the output stage of the memory circuit 7. When the image size is reduced in the horizontal direction by the switch circuit 13 provided at the subsequent stage of the vertical filter 9, the output data of the vertical filter 9 is received. In contrast, when the image size is enlarged in the horizontal direction, the image data output from the vertical filter 9 is output to the monitor 3 via the horizontal filter 8.

  As a result, the image size conversion circuit 5 vertically converts the image data by a plurality of tap outputs from the memory circuit 7 as shown in FIGS. 2 (A) and 2 (B) where the image size is reduced and enlarged in the horizontal direction. When the image size is reduced in the horizontal direction by outputting to the filter 9 to change the image size in the vertical direction, the horizontal filter 8 is arranged in the preceding stage of the memory circuit 7 to set the sampling number of the image data. When the image size is reduced by the horizontal filter 8 and input to the memory circuit 7, the image size is increased in the horizontal direction. The image data is processed by the memory circuit 7 in a stage before the increase. Thereby, the image size conversion circuit 5 converts the image size in the order of the horizontal direction and the vertical direction when reducing the image size in the horizontal direction, whereas it is vertical when expanding the image size in the horizontal direction. The image size is converted in the order of the horizontal direction and the horizontal direction, and the size of the image is variously enlarged and reduced, thereby effectively avoiding an increase in the capacity of the memory circuit 7. In these cases, when the image size is enlarged in the vertical direction, a frame memory F is arranged as required or an image sensor as shown by a broken line in FIGS. 2 (A) and 2 (B). By applying CMOS to 2, it is necessary to correct the timing of each line of the image data D <b> 1 input to the memory circuit 7 so as to correspond to the interpolation processing in the vertical filter 9.

  Accordingly, the horizontal filter 8 operates in accordance with the clock of the image data input to the image size conversion circuit 5 in the horizontal direction, performs interpolation calculation processing on the sequentially input image data, and thereby changes the horizontal direction of the image data. The image size is changed to the output image data D2 and output. Specifically, for example, as shown in FIG. 3, the horizontal filter 8 weights the flip-flop circuit 13A, which is a delay circuit corresponding to the clock cycle of the input image data, and the input image data and the output data of the flip-flop circuit 13A. Multiplier circuits 14A and 14B, an adder circuit 15 that adds the output data of the multiplier circuits 14A and 14B, a flip-flop circuit 16 that temporarily holds and outputs the output data of the adder circuit 15, and multiplier circuits 14A and 14B. It is configured by an interpolation circuit such as a buffer circuit provided at the output stage of the circuit 15. The horizontal filter 8 is not limited to the interpolation circuit based on the 2-tap linear interpolation shown in FIG. 3, but uses a 4-tap or 8-tap interpolation circuit as shown in FIGS. 4 and 5 in comparison with FIG. It can be widely applied to various configurations as required.

  In the horizontal filter 8, the weighting coefficients of the multiplication circuits 14A and 14B are sequentially set by a controller (not shown) according to the sampling phase corresponding to the enlargement ratio and reduction ratio related to the change in the image size in the horizontal direction. Note that the horizontal filter 8 is arranged on the rear stage side of the vertical filter, and when the image size is expanded in the horizontal direction, the flip-flop circuit 13A corresponds to repeated image data output from the memory circuit 7 described later. Thus, the image data relating to a plurality of sampling points can be generated between sampling points adjacent in the horizontal direction of the input image data D1.

  On the other hand, the vertical filter 9 interpolates a plurality of lines of image data output simultaneously and in parallel from the memory circuit 7 in the vertical direction, whereby the vertical direction of the image data is converted into an image of the output image data D2. Change to size and output. Specifically, for example, as shown in FIG. 6, the vertical filter 9 includes multiplication circuits 20A to 20H that respectively weight the tap outputs from the memory circuit 7, and an addition circuit 21 that adds the output data of the multiplication circuits 20A to 20H. The flip-flop circuit 22 that temporarily holds and outputs the output data of the adder circuit 21, the multiplier circuits 20 </ b> A to 20 </ b> H, and an interpolation circuit such as a buffer circuit provided at the output stage of the adder circuit 21. The vertical filter 9 is not limited to the 8-tap interpolation circuit shown in FIG. 6, and in contrast to FIG. 6, when using a 2-tap, 4-tap interpolation circuit as shown in FIGS. 7 and 8, etc. Various configurations can be widely applied as necessary.

  As with the horizontal filter 8, the vertical filter 9 sequentially weights the multiplication circuits 20 </ b> A to 20 </ b> H by a controller (not shown) according to the sampling phase corresponding to the enlargement ratio and reduction ratio associated with the change in the image size in the vertical direction. Is set to be set.

  The memory circuit 7 has a memory capacity corresponding to the number of horizontal samplings of the image data D1 output from the camera signal processing circuit 4, and a plurality of line memories 25A to 25E operated by the clock of the image data D1, A selector 26 that distributes input image data to these line memories 25A to 25E, a selector 27 that distributes output image data from these line memories 25A to 25E to each tap input of the vertical filter 9, these line memories 25A to 25E, selectors 26, 27 The memory controller 28 controls the operation of The memory circuit 7 records the image data sequentially input to one of the plurality of line memories 25A to 25E, while remaining the image data of a plurality of lines related to the vertical image size change processing in the vertical filter 9. Three or more line memories 25A to 25E are provided so that the line memories 25A to 25E can simultaneously output in parallel. In this embodiment, the memory circuit 7 is provided with five line memories 25A to 25E, whereby the image size can be changed by a 4-tap process in the vertical filter 9 that continues at least. Thus, the memory circuit 7 outputs the image data by the multi-tap output corresponding to the processing of the vertical filter 9 while storing the sequentially input image data by using the line memories 25A to 25E sequentially and cyclically. Has been made.

  In these processes, the memory circuit 7 outputs from the horizontal filter 8 according to the reduction ratio when the horizontal filter 8 is arranged in the preceding stage and the image size is reduced in the horizontal direction under the control of the memory controller 28. The image data is thinned and recorded, whereby the image data is recorded by downsampling. On the other hand, when the horizontal filter 8 is disposed after the vertical filter 9 and the image size is enlarged in the horizontal direction, the image data is repeatedly output in units of pixels in accordance with the enlargement ratio. Interpolation calculation processing is performed by the clock so that the horizontal filter 8 can generate a plurality of sampling points related to the enlargement of the image size between sampling points adjacent in the horizontal direction of the input image data.

  Further, when the image size is reduced in the vertical direction by the vertical filter 9, the memory circuit 7 outputs the image data by thinning out in units of lines according to the reduction ratio, and thereby outputs the image data by downsampling. On the other hand, when the image size is enlarged in the vertical direction by the vertical filter 9, the image data is repeatedly output in units of lines during one horizontal scanning period according to the enlargement ratio. The vertical filter 9 can generate a plurality of lines related to the enlargement of the image size between adjacent lines in the vertical direction.

  As a result, the memory circuit 7 is configured to be operable with one system clock based on the clock of the input image data D1, and the line memories 25A to 25E can be configured with a single port random access memory. Can be reduced in size, and the overall configuration can be simplified.

  In these processes, the memory circuit 7 is a process related to the electronic zoom in which the image size is enlarged by the address control by the memory controller 28, and this enlargement of the image size occurs in the horizontal direction and the vertical direction. For image data not used for display, recording and output are stopped, and unnecessary processing in each unit is thereby stopped.

  The memory circuit 7 records and reproduces image data by dividing the memory space of each line memory 25A to 25E into predetermined blocks, thereby reducing the image size in the horizontal direction and reducing the number of samples per line. Therefore, the number of tap outputs to be recorded and output to the vertical filter 9 by increasing the number of lines corresponding to the number of lines is increased, thereby effectively utilizing the decrease in the amount of data in the horizontal direction. It is designed to improve image quality.

  That is, FIG. 9 is a time chart relating to the image size changing process under the control of the memory controller 28, and is a case where the image size is reduced both in the horizontal direction and in the vertical direction. In FIG. 9, for simplification of description, it is assumed that the memory circuit 7 is composed of three line memories 25A, 25B, and 25C. In the following description, it is assumed that the image size is reduced by interpolation calculation processing using taps. In FIG. 9, HD1 and HD2 (FIGS. 9A and 9E) are horizontal synchronizing signals related to the input / output of the image size conversion circuit 5, respectively, and symbols W and R are respectively sent to the line memory. The writing and reading processes are shown.

  In this case, the image size conversion circuit 5 sequentially inputs image data (FIG. 9 (F1)) in the horizontal filter 8 so that each sample of the input image data D1 is indicated by numerals 1, 2, 3,. ) And the image data (FIG. 9 (F2)) delayed by one clock cycle with respect to this image data are interpolated by the weighting coefficient based on the sampling phase for reduction, and the clock of this input image data D1 Output in sync with. In FIG. 9, as indicated by the numbers 0/1, 1/2, 2/3, the output value X related to the interpolation processing result is indicated by a combination of numbers indicating the samples to be processed (FIG. 9 (F3 )). As a result, the image size conversion circuit 5 sequentially calculates sampling values obtained by reducing the image size in the horizontal direction in synchronization with the input image data D1.

  In the memory controller 28, the line memories 25A to 25C are sequentially and cyclically selected, and the image data D3 (FIG. 9B) output from the horizontal filter 8 is supplied to the line memories 25A to 25A. 25C (FIG. 9 (C1) to (C3)). At this time, the memory controller 28 reduces the write address of each of the line memories 25A to 25C by FIG. 9 (G1) and the sample to be used for writing in FIG. 9 (G2) by comparison with FIG. 9 (F3). Image data sequentially input by downsampling according to the rate is recorded in the line memories 25A to 25C. That is, in this case, image data is selectively acquired, and sequentially input image data is selectively recorded by setting an address counter that generates a write address. Thereby, the image size conversion circuit 5 processes the input image data D1 in synchronization with the clock of the input image data D1 by down-sampling the interpolation processing result of the continuous image data, and increases the number of sampling in the horizontal direction. Even when it is variable, the image size in the horizontal direction can be changed to an image size based on a desired number of samplings.

  In addition, the image data is sequentially recorded in the line memories 25A to 25C in this way, and two continuous lines of image data are output to the vertical filter 9 from the line memory that has completed the recording of the image data (FIG. 9 (C1 ) To (C3)), the sampling value related to the reduction in the vertical direction is calculated by the interpolation processing by the vertical filter 9. Also in this reading process, the memory controller 28 outputs image data by downsampling in accordance with the reduction ratio in the vertical direction. That is, in this case, the image data is output by thinning out in units of lines according to the setting of the address counter that generates the read address. In FIG. 9, the output of two consecutive lines of image data is intermittently executed every horizontal scanning period by this downsampling. In this way, the image size conversion circuit 5 processes the input image data D1 in synchronization with the clock of the input image data D1 and sets the vertical image size even when the number of vertical samplings is greatly varied. The image size can be changed according to the desired number of samplings.

  On the other hand, FIG. 10 is a time chart showing a case where the image size is reduced and enlarged in the horizontal direction and the vertical direction, respectively, in comparison with FIG. In this case, the image size conversion circuit 5 processes the image data and records it in the memory circuit 7 as in the case of reducing the image size in both the horizontal direction and the vertical direction (FIGS. 10A and 10B). (C1) to (C3), (F1) to (F3), (G1) and (G2)). Thus, the image size conversion circuit 5 interpolates the input data in synchronization with the input image data in the horizontal filter 8 and then reduces the image size in the horizontal direction by down-sampling when writing to the memory circuit 7. Has been made. The line memories 25A to 25C are sequentially and cyclically selected, and the image data D3 (FIG. 9B) output from the horizontal filter 8 is recorded in the line memories 25A to 25C. In these processes, the image size conversion circuit 5 cancels the recording to the memory circuit 7 by thinning out a predetermined number of lines corresponding to the vertical and enlargement magnifications that are not required by enlarging the image size in the vertical direction. As a result, unnecessary processing is stopped.

  In this way, the image data is recorded in the line memories 25A to 25C, and the memory controller 28 continues 2 in units of lines within one horizontal scanning period of the input image data D1 according to the enlargement ratio in the vertical direction. The line image data is repeatedly output to the vertical filter 9 (FIG. 10 (C1) to (C3)). As a result, the image size conversion circuit 5 changes the image size in the vertical direction to the image size based on the desired number of samplings by processing synchronized with the clock of the input image data D1. In this case, one horizontal scanning period of the output image data D2 changes according to the enlargement ratio with respect to one horizontal scanning period of the input image data D1.

  On the other hand, FIG. 11 is a time chart showing a case where the image size is enlarged and reduced in the horizontal direction and the vertical direction, respectively, in comparison with FIG. In this case, the image size conversion circuit 5 stores all the image data output from the camera signal processing circuit 4 in the memory circuit 7 (FIGS. 11A, 11B, and C1 to C3). The recorded image data is output to the vertical filter 9 by 2-tap output in accordance with the reduction ratio in the vertical direction (FIG. 11 (C1) to (C3)), and the reduction in the vertical direction is performed by the interpolation processing by the vertical filter 9. The sampling value concerning is calculated.

  In this case, as in the case of reducing the image size both in the horizontal direction and in the vertical direction, the image size conversion circuit 5 outputs image data from the memory circuit 7 by downsampling according to the reduction ratio in the vertical direction. Thus, the input image data D1 is processed in synchronization with the clock of the input image data D1, and the image size in the vertical direction can be changed to an image size based on a desired number of samplings.

  Further, the image data reduced in the vertical direction in this way is expanded in the horizontal direction by the horizontal filter 8, and the image size is expanded in the horizontal direction so that a predetermined number corresponding to the left, right, and enlargement magnification becomes unnecessary. For pixels, the input to the horizontal filter 8 is stopped and the useless processing is stopped. Further, in the output of image data from the memory circuit 7, image data with the same sampling value is repeatedly output in units of pixels from the memory circuit 7 according to the enlargement ratio in the horizontal direction (FIGS. 11 (G1) to (I2)). . Thereby, the image size conversion circuit 5 processes the input image data D1 in synchronization with the clock of the input image data D1, and between the sampling points adjacent in the horizontal direction of the input image data D1, the sampling points according to the enlargement ratio. The image data according to the above is generated by the horizontal filter 8.

  On the other hand, FIG. 12 is a time chart showing a case where the image size is enlarged in both the horizontal direction and the vertical direction. In this case, the image size conversion circuit 5 stores the image data output from the camera signal processing circuit 4 in the memory circuit 7 in line units (FIGS. 12A, 12B, and C1 to C3). The recorded image data is output to the vertical filter 9 by 2-tap output according to the enlargement ratio in the vertical direction (FIG. 12 (C1) to (C3)). A sampling value for enlargement is calculated.

  In these processes, the image size conversion circuit 5 increases the image size in the vertical direction and stops recording in the memory circuit 7 for a predetermined number of lines corresponding to the up and down and magnification factors. Cancel unnecessary processing. Similarly to the case where the image size is reduced and enlarged in the horizontal direction and the vertical direction, the output of the image data to the vertical filter 9 by two lines is repeated in units of lines in accordance with the enlargement ratio within one horizontal scanning period. Similar to the case of enlarging and reducing the image size in the horizontal and vertical directions, image data with the same sampling value is repeatedly output from the memory circuit 7 in units of pixels in accordance with the enlargement ratio in the horizontal direction (FIG. 12 (G1 ) To (I2)). Also by these, the image data is processed by the clock of the input image data D1, and the image data D2 having a desired image size can be output. In this case as well, the one horizontal scanning period of the output image data D2 changes with respect to the one horizontal scanning period of the input image data D1 in accordance with the enlargement ratio in the vertical direction.

  On the other hand, FIG. 13 and FIG. 14 are time charts for explaining the H inversion processing at the time of horizontal image enlargement and reduction. The memory controller 28 sequentially reads and outputs image data from the line memories 25A to 25C in the order of writing of the image data at the time of normal enlargement / reduction, whereas in the H inversion processing, each of the line memories 25A to 25C The image data is read and output in the reverse order of the writing order.

  That is, at the time of image enlargement in the horizontal direction, when writing image data Y0, Y1,... (FIG. 13A), the generation order of the write addresses is reversed (FIG. 13B), and at the time of reading, sequentially. A read address is generated and image data is output (FIGS. 13C and 13D), whereby the image data is read and output in the reverse order of the writing order. Similarly, when the image is reduced in the horizontal direction, the generation order of the write addresses is reversed (FIGS. 14A and 14B), and at the time of reading, the read addresses are sequentially generated to output the image data. (FIGS. 14C and 14D), thereby reading out and outputting the image data in the reverse order of the writing order. At the time of horizontal reduction, the image data to be written in the memory circuit 7 with respect to the input data to the image size conversion circuit 5 is intermittently stored in memory for the downsampling related to the reduction processing using the horizontal filter 8. It is recorded in the circuit 7.

  The memory controller 28 executes such a reversal of the generation order of the write address for each line. The address is generated by decrementing sequentially from the address obtained by subtracting the value 1 from the number of pixels per line, and the H inversion process is executed.

  In this embodiment, the image data is written by sequentially using a plurality of line memories 25A to 25E, and the processing can be divided into writing and reading of the image data. The processing relating to the H inversion can be executed with a simple configuration in which the generation order of the read address and the read address is reversed.

  By the way, as in this embodiment, when the image data is processed by the vertical filter 9 after the horizontal filter 8 reduces the number of samplings in the horizontal direction to reduce the image size in the horizontal direction, the memory circuit 7, When the filter 9 is operated by the clock of the input image data D1, when the reduction ratio in the horizontal direction is increased, the time required for processing per line in the vertical filter 9 is shortened. That is, as shown in FIG. 15, an effective interval that is a time during which image data is processed effectively by the vertical filter 9 with respect to one horizontal scanning period (FIGS. 15A and 15B) of the input image data D1. Is shortened (FIG. 15 (C1) and (C2)), and accordingly, the vertical filter 9 operates wastefully outside the effective interval and consumes power. As a result, in this image size conversion circuit 5, in this case, the clock rate in the vertical filter 9 is lowered to increase the effective interval (FIGS. 15D1 and 15D2), and wasteful power consumption is prevented.

  Specifically, in this embodiment, the clock frequency of the vertical filter 9 is lowered according to the reduction ratio in the horizontal direction, and the same image is output from the memory circuit 7 in a plurality of clock cycles in conjunction with the reduction of the clock frequency. Output data repeatedly. In the image size conversion circuit 5, a clock CK synchronized with the input image data D1 is generated by a timing generator and supplied to each unit. Reduction by a horizontal filter 8 is performed by a frequency dividing circuit provided in the timing generator. In accordance with the rate, the frequency division ratio is sequentially changed stepwise by the power-frequency division ratio of 2, and the clock CK is divided by this frequency division ratio to generate the clock CK1. The image size conversion circuit 5 supplies the clock CK1 related to the frequency division to an address counter which is a read address generation circuit of the memory controller 28, and sequentially generates read addresses based on the clock CK1 related to the frequency division. The vertical filter 9 is driven by the clock CK1 related to this frequency division.

  As a result, the image size conversion circuit 5 sequentially generates write addresses in synchronization with the clock CK (FIG. 16D), and the line memories 25A and 25B are reduced by the horizontal filter 8 as shown in FIG. Image data Y1 / YO, Y3 / Y2, Y5 / Y4,... Are recorded (FIGS. 16 (A), (B1) and (B2)), and at the time of reading, for example, a clock twice this clock CK. Image data is read from these two line memories 25A and 25B (FIG. 16 (E1) and (E2)) in synchronization with the clock CK1 (FIG. 16F) according to the period, and these image data are processed by the vertical filter 9. This is done (FIG. 16G).

  FIG. 17 is a time chart showing a case where the frequency division ratio of the clock CK1 is set to a value 1 in comparison with FIG. In the image size conversion circuit 5, when the reduction ratio is smaller than the predetermined range, as shown in FIG. 17, the division ratio is set to a value 1, and the address counter related to the read address by the clock CK1 related to the division. And the vertical filter 9 are driven.

  Furthermore, in this embodiment, the memory controller 28 reduces the number of samplings per line by reducing the image size in the horizontal direction, so that the capacity of the line memories 25A to 25E has a margin, and the vertical filter is simultaneously and in parallel. The number of lines of image data to be output is increased, and thereby the image quality is improved by performing interpolation processing with a large number of taps in the vertical filter.

  Specifically, among the line memories 25A to 25E, three line memories are formed by internally connecting two middle blocks each having a capacity that is ½ of the capacity of each line memory, while remaining One line memory of the two line memories is formed by internally connecting one middle block and two small blocks having a capacity ½ of the middle block. The remaining one line block is formed by internally connecting four small blocks. In the memory circuit 5, five line memories are thus formed by the small block and the large block, and one small block is further formed. Has been made so that.

  The memory controller 28 stores the image data in each of the line memories 25A to 25E, and when the free space of 0.25 lines or more and 0.5 minutes or less is generated in each of the line memories 25A to 25E, these lines are stored. The internal connections relating to the memories 25A to 25E are switched, the number of line memories constituting the memory circuit 7 is increased from five to seven, and image data by 6 tap output is output to the vertical filter 9. Specifically, in this case, the memory circuit 7 forms each line memory by one medium block and one small block, and thereby processes the image data by the seven line memories.

  On the other hand, when image data is stored in the five line memories 25A to 25E and a free space of 0.5 lines or more is generated in each of the line memories 25A to 25E, the internal connection related to these line memories 25A to 25E , The number of line memories constituting the memory circuit 7 is increased from 5 to 9, and image data by 8 tap output is output to the vertical filter 9. Specifically, in this case, the memory circuit 7 forms seven line memories of nine line memories each by one medium block, and the remaining two line memories each by two small blocks. In this way, image data is processed by nine line memories.

  Thereby, the image size conversion circuit 5 converts the image size in the vertical direction by changing the number of taps of the vertical filter 9 as shown in FIG. 18 in accordance with the reduction ratio in the horizontal direction. In this case, the number of vertical taps may be varied according to the amount of data as shown in FIG. 19 by monitoring the amount of image data for one line in each line memory.

(2) Operation of Embodiment In the above configuration, in this electronic still camera 1 (FIG. 1), the image pickup result by the image sensor 2 is converted into image data and processed by the camera signal processing circuit 4, and then image size conversion is performed. The result is output to the monitor 3 via the circuit 5, and thereby the imaging result is monitored. In this series of processing, the image data relating to the imaging result is obtained by the image size conversion circuit 5 in which the number of pixels in the horizontal direction and the vertical direction related to the image sensor 2 is further increased or decreased by increasing or decreasing the image size in the horizontal direction. By the enlargement or reduction of the image size in the vertical direction, the number of pixels in the horizontal direction and the vertical direction of the monitor 3 is converted and output to the monitor 3, thereby causing the horizontal and vertical directions between the image sensor 2 and the monitor 3. Even if the number of pixels in the direction is different, the imaging result can be reliably monitored.

  That is, when the image size in the horizontal direction is reduced by reducing the number of pixels in the horizontal direction, the image data D1 input to the image size conversion circuit 5 is reduced in the horizontal image size by the interpolation processing by the horizontal filter 8. Thereafter, it is input to the memory circuit 7, where it is sequentially and cyclically recorded in the five line memories 25A to 25E. In addition, in this manner, the image data is sequentially and cyclically recorded in the line memories 25A to 25E, and the image data is read simultaneously and in parallel from the remaining four line memories that are not used for recording the image data D1, and the image data is read by the vertical filter 9. Here, the image size is enlarged or reduced in the vertical direction by interpolation processing of image data of a plurality of lines based on output data from the four line memories.

  On the other hand, when the image size in the horizontal direction is enlarged by increasing the number of pixels in the horizontal direction, the image data D1 input to the image size conversion circuit 5 is input to the memory circuit 7, where five lines The data is sequentially and cyclically recorded in the memories 25A to 25E. In addition, in this manner, the image data is sequentially and cyclically recorded in the line memories 25A to 25E, and the image data is read simultaneously and in parallel from the remaining four line memories that are not used for recording the image data D1, and the image data is read by the vertical filter 9. Here, the image size is enlarged or reduced in the vertical direction by interpolation processing of image data of a plurality of lines based on output data from the four line memories. The output data of the vertical filter 9 is input to the horizontal filter 8, where the image size in the horizontal direction is enlarged.

  Thus, the image size conversion circuit 5 can be applied when the image size is enlarged or reduced in the horizontal direction and the vertical direction, whereby the image size can be variously converted in the horizontal direction and the vertical direction.

  In these processes (FIG. 2), when the image size is reduced, the number of samplings in the horizontal direction is reduced by the horizontal filter 8, and then the vertical image size is converted by the memory circuit 7 and the vertical filter 9. In the case of enlarging the image size, the image size in the vertical direction is converted by the memory circuit 7 and the vertical filter 9 and then the number of sampling in the horizontal direction is increased by the horizontal filter 8 to change the image size in various ways. The configuration can be switched when the image size is enlarged or reduced in the horizontal direction so that the capacity of the memory circuit 7 can be minimized. As a result, the capacity of the memory circuit 7 can be reduced accordingly, and the overall configuration can be simplified.

  Further, when the image data is processed in this way and the memory circuit 7, the horizontal filter 8, and the vertical filter 9 are operated by the clock of the input image data D1 to reduce the image size in the horizontal direction. When the image data output from the horizontal filter is stored in the memory circuit 7 by down-sampling by thinning according to the reduction ratio and the image size is reduced in the vertical direction, the memory circuit is thinned by line-by-line according to the reduction ratio. 7 to output image data to the vertical filter 9 and when the image size is enlarged in the vertical direction, the image data is repeatedly output from the memory circuit 7 to the vertical filter 9 line by line in accordance with the enlargement ratio. When enlarging the image size in the horizontal direction, the memory circuit 7 passes through the vertical filter 9 in units of pixels according to the enlargement ratio. By outputting the image data repetitively in the horizontal filter 8, the line memory 25A~25E constituting the memory circuit 7 is operated by the single clock pulse, the image data can be processed.

  As a result, in this embodiment, the line memories 25A to 25E can be configured by a simple single-port random access memory with a simpler peripheral circuit configuration than the dual-port line memory. The image size can be enlarged and reduced in various ways with a simple configuration.

  Further, when the image size is reduced in the horizontal direction by operating with one system clock in this way, the clock frequency to the address counter for reading from the memory circuit 7 is divided in accordance with the reduction ratio. In addition, the vertical filter 9 is driven by the clock related to this frequency division, and the processing speed in the vertical filter 9 is reduced by the amount of sampling in the horizontal direction due to the reduction of the image size in the horizontal direction. Thus, power consumption can be reduced.

  Further, when the image size is reduced in the horizontal direction and the number of samplings in the horizontal direction is reduced in this way, the free space of the line memories 25A to 25E due to the decrease in the number of samplings in the horizontal direction is used, so The image data is held in the memory circuit 7, and the number of taps related to the interpolation processing of the vertical filter 9 is correspondingly increased. Accordingly, in this case, the image size can be converted with high image quality by changing the image size in the vertical direction by increasing the number of taps.

  In the electronic still camera 1, such image size conversion processing by the image size conversion circuit 5 is used to compensate for the difference in the number of pixels (image size) between the image sensor 2 and the monitor 3. In addition, the present invention is also applied to a case where an imaging result is enlarged and displayed by an electronic zoom. That is, in this case, the image size conversion circuit 5 is instructed to the reduction ratio and the enlargement ratio in response to the operation of the operation element by the user under the control of a controller (not shown), and the horizontal direction and the vertical direction are determined by the reduction ratio and the enlargement ratio according to this instruction. The image size is continuously changed.

  When H inversion is instructed, the generation order of the write addresses in the memory circuit 7 is reversed, and image data is output in line units in the reverse order from the writing. In this processing, the image size conversion circuit 5 performs down-sampling by pixel thinning and writing the image data to the memory circuit 7 when the image is reduced, and the image data related to the H inversion by changing the address on the writing side. Is output, even when the reduction ratio changes, the position of the center of the image in the horizontal direction can be prevented, and the processing relating to H inversion can be executed with a simple configuration. .

(3) Effects of the embodiment According to the above configuration, when the image size is reduced in the horizontal direction, the horizontal filter for reducing the image size in the horizontal direction is followed by the memory circuit by the line memory, the size in the vertical direction. When the vertical filter to change the image size is expanded and the image size in the horizontal direction is increased, the vertical filter and the horizontal filter are arranged in this order after the memory circuit. Various image sizes can be converted.

  In this processing, when the image size is enlarged in the vertical direction by operating the memory circuit, the horizontal filter, and the vertical filter by the clock of the input image data, a plurality of lines are extracted from the memory circuit according to the enlargement ratio. When repeatedly outputting image data in line units and enlarging the image size in the horizontal direction, when outputting the same image data repeatedly in pixel units and reducing the image size in the vertical direction according to the enlargement ratio In the case of reducing the image size in the horizontal direction by thinning out in units of lines according to the reduction rate, and reducing the image size in the horizontal direction, the image data is thinned out in units of pixels according to the reduction rate. By inputting to the memory circuit, the configuration of the peripheral circuit is simple, and the memory circuit can be configured with a small single-port random access memory. , That amount, variously larger image size with a simple structure, can be reduced.

  If the image size change due to the horizontal filter is a reduction in the image size, the operation speed of the vertical filter is reduced by reducing the clock frequency in accordance with the reduction ratio, and the memory circuit read-out is associated with this. By reducing the address generation speed, useless operations in the vertical filter can be reduced and power consumption can be reduced.

  In addition, by reversing the address generation order for writing in the memory circuit and outputting image data in units of lines in the reverse order of writing, the image center in the horizontal direction can be changed even when the reduction ratio changes variously. Thus, the process related to the H inversion can be executed with a simple configuration.

  If the image size change due to the horizontal filter is a reduction in the image size, the number of lines of image data output to the vertical filter is increased in accordance with the number of samplings per line to be reduced in accordance with the reduction magnification. By increasing the number of taps related to this interpolation processing, it is possible to improve the image quality by effectively using the free capacity of the memory circuit generated by the reduction of the image size.

  In the above-described embodiment, the case where the number of taps of the vertical filter is switched in three steps according to the reduction ratio in the horizontal direction has been described. However, the present invention is not limited to this, and for example, the comparison is made with FIG. 18 and FIG. As shown in FIG. 20 and FIG. 21, when the number of taps is switched, for example, when the number of taps is switched in two stages, various settings can be made as necessary.

  In the above-described embodiments, the case where the present invention is applied to an electronic still camera has been described. However, the present invention is not limited to this, and is widely applied to various imaging devices such as a video camera and various video devices. can do.

  The present invention can be applied to, for example, an electronic still camera.

It is a block diagram which shows the electronic still camera which concerns on the Example of this invention. FIG. 2 is a block diagram for explaining an image size conversion circuit in the electronic still camera of FIG. 1. FIG. 3 is a block diagram illustrating a horizontal filter in the image size conversion circuit of FIG. 2. FIG. 3 is a block diagram illustrating an example of a 4-tap horizontal filter in the image size conversion circuit of FIG. 2. FIG. 3 is a block diagram illustrating an example of an 8-tap horizontal filter in the image size conversion circuit of FIG. 2. FIG. 3 is a block diagram illustrating a vertical filter in the image size conversion circuit of FIG. 2. FIG. 3 is a block diagram illustrating an example of a 2-tap vertical filter in the image size conversion circuit of FIG. 2. FIG. 3 is a block diagram illustrating an example of a 4-tap vertical filter in the image size conversion circuit of FIG. 2. 3 is a time chart when the image size is reduced both in the horizontal direction and in the vertical direction in the image size conversion circuit of FIG. 2. 3 is a time chart when the image size is reduced and enlarged in the horizontal direction and the vertical direction in the image size conversion circuit of FIG. 2. 3 is a time chart when the image size is enlarged and reduced in the horizontal direction and the vertical direction in the image size conversion circuit of FIG. 2. 3 is a time chart when the image size is enlarged both in the horizontal direction and in the vertical direction in the image size conversion circuit of FIG. 2. 3 is a time chart for explaining H inversion processing in the image size conversion circuit of FIG. 2. It is a time chart used for description of H inversion processing when the image size in the horizontal direction is reduced. It is a time chart used for description of reduction of an effective section when the image size in the horizontal direction is reduced. It is a time chart with which it uses for description of the reduction | decrease of the operating speed in a vertical filter. FIG. 17 is a time chart when the reduction ratio in the horizontal direction is small in comparison with FIG. 16. It is a characteristic curve figure which shows the relationship between the reduction rate of a horizontal direction, and the number of taps of a vertical filter. It is a characteristic curve diagram showing the relationship between the amount of image data per line and the number of taps of the vertical filter in the memory circuit. It is a characteristic curve figure which shows the relationship between the reduction rate of the horizontal direction by the other Example, and the number of taps of a vertical filter. It is a characteristic curve figure which shows the relationship between the image data amount per line in the memory circuit by another Example, and the number of taps of a vertical filter.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Electronic still camera, 2 ... Image sensor, 3 ... Monitor, 5 ... Image size conversion circuit, 7 ... Memory circuit, 8 ... Horizontal filter, 9 ... Vertical filter, 25A-25E ... Line Memory, 28 ... Memory controller

Claims (6)

In an image size conversion device that converts the image size of input image data and outputs output image data,
A plurality of line memories of at least three, wherein the plurality of line memories are sequentially and cyclically selected to record sequentially input image data in the line memory, and the remaining of the plurality of line memories A memory circuit for simultaneously reading out and outputting image data of a plurality of lines from the line memory;
A vertical filter that changes the image size of the image data in a vertical direction by performing interpolation calculation processing on the image data of the plurality of lines output from the memory circuit;
A horizontal filter that changes the image size of the image data in the horizontal direction by outputting the continuous image data after performing interpolation calculation processing;
When the change in the image size due to the horizontal filter is reduction of the image size, the input image data is input to the horizontal filter, the output data of the horizontal filter is input to the memory circuit, and the output data of the vertical filter circuit Is output as the output image data,
When the change in the image size by the horizontal filter is an enlargement of the image size, the input image data is input to the memory circuit, the output data of the vertical filter is input to the horizontal filter, and the output data of the horizontal filter is An image size conversion apparatus comprising: a switch circuit that outputs the output image data. The memory circuit includes:
Recording the image data with the clock of the input image data, and outputting the image data;
When the image size is enlarged in the vertical direction by the vertical filter, the image data of the plurality of lines is repeatedly output in units of lines in one horizontal scanning period of the input image data according to the enlargement ratio.
When the image size is enlarged in the horizontal direction by the horizontal filter, the same image data is repeatedly output in units of pixels according to the enlargement ratio,
When the image size is reduced in the vertical direction by the vertical filter, the image data is output to the vertical filter by thinning out in units of lines according to the reduction ratio,
When the image size is reduced in the horizontal direction by the horizontal filter, the image data is input by thinning out in units of pixels according to the reduction ratio.
The horizontal filter and the vertical filter are:
The image size conversion apparatus according to claim 1, wherein the image size conversion apparatus operates according to a clock of the input image data and executes an interpolation calculation process. When the change in the image size by the horizontal filter is a reduction in the image size,
The vertical filter is
Reduce the operating speed by reducing the clock frequency according to the reduction rate,
The memory circuit includes:
The image size conversion apparatus according to claim 1, wherein an address generation speed related to reading is reduced so as to correspond to the reduction of the clock frequency. The memory circuit includes:
3. The image size conversion apparatus according to claim 2, wherein the address generation order for writing is reversed, and image data is output in line units in the order reverse to that at the time of writing. The memory circuit includes:
When the change in the image size by the horizontal filter is a reduction in the image size, the number of lines to be output to the vertical filter is increased according to the number of samples per line to be reduced according to the reduction magnification.
The image size conversion apparatus according to claim 1, wherein: Imaging means for obtaining imaging results;
An image pickup apparatus having an image size conversion circuit that executes processing related to electronic zoom by changing the image size based on input image data obtained by the image pickup means in response to an operation of an operator and outputting output image data Because
The image size conversion circuit includes:
A plurality of line memories of at least three, wherein the plurality of line memories are sequentially and cyclically selected to record sequentially input image data in the line memory, and the remaining of the plurality of line memories A memory circuit for simultaneously reading out and outputting image data of a plurality of lines from the line memory;
A vertical filter that changes the image size of the image data in a vertical direction by performing interpolation calculation processing on the image data of the plurality of lines output from the memory circuit;
A horizontal filter that changes the image size of the image data in the horizontal direction by outputting the continuous image data after performing interpolation calculation processing;
When the change in the image size due to the horizontal filter is reduction of the image size, the input image data is input to the horizontal filter, the output data of the horizontal filter is input to the memory circuit, and the output data of the vertical filter circuit Is output as the output image data,
When the change in the image size by the horizontal filter is an enlargement of the image size, the input image data is input to the memory circuit, the output data of the vertical filter is input to the horizontal filter, and the output data of the horizontal filter is An image pickup apparatus comprising: a switch circuit that outputs the output image data.

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