JP2001309231A - Image processing apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To display a reduced image continuously in a video camera that is provided with an solid-state imaging device having a larger number of pixels than an area that can be displayed by video. SOLUTION: Signals read from CCD solid-state imaging device 1 are split by a signal-processing unit 2 into a luminance signal and a color signal, sequentially sent to a horizontally reducing filter 3 and transformed into an image signal which has been reduced in the horizontal direction at a prescribed reduction ratio. Then, the image signal reduced in the horizontal direction is sent to a vertically reducing filter 4 to be transferred to an image reduced in a prescribed horizontal direction and stored at a dual port line memory 6. Video data for an area is obtained that is variable consecutively between a range where the entire effective range of CCD imaging device 1 is captured and a range of effective number of pixels by reading signals recorded in the dual port line memory 6 consecutively in synchronism with video clock.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an image processing technique for reducing and displaying an image in a video camera system using a solid-state image sensor.

[0002]

2. Description of the Related Art As for image processing in a video camera system using a solid-state imaging device, there are the following conventional examples as image reduction techniques. Japanese Patent Application Laid-Open No. 8-154212 discloses a technique for reducing a still image using a solid-state imaging device to which a camera shake correction area is added. Japanese Patent Application Laid-Open No. 11-53531 describes a technique for enlarging / reducing an image based on image data of four adjacent points, obtaining interpolated image data at a position between them. ing.

[0003]

However, the former technique disclosed in Japanese Patent Application Laid-Open No. 8-154212 is intended for still images, and it is difficult to adapt to moving images. There is a problem that one frame of image memory is required for image processing. Further, the latter technique disclosed in Japanese Patent Application Laid-Open No. H11-53531 has a problem that an image memory for four lines is required, and furthermore, in the case of reduction, aliasing distortion due to an arithmetic method occurs. are doing. The present invention has been made to solve such a problem, and an object of the present invention is to obtain a fine image in which a moving image is reduced to an arbitrary magnification without causing aliasing distortion with a small image memory.

[0004]

In order to achieve the above object, the present invention relates to an image processing apparatus for an image pickup apparatus using a solid-state image pickup device, wherein an output image signal of the solid-state image pickup device is read out over the entire area. By reducing the size in the horizontal and vertical directions, the captured image is reduced to an arbitrary magnification with high quality. Further, in the image processing apparatus, when reading out the output image signal of the solid-state imaging device in the entire region, a part of the region is read out by suppressing the line reading of the solid-state imaging device, and the horizontal and vertical directions are read out. Thus, the same effect as the zoom function is obtained by reducing the size to. Further, the present invention provides
In the image processing apparatus, the video signal reduced in the horizontal direction and the vertical direction is stored in a line memory, and frequency conversion is performed by reading the video signal with a clock synchronized with a video video signal different from a clock for reading a solid-state imaging device. It was made.

[0005]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of an image processing apparatus according to the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of an embodiment of an image processing apparatus according to the present invention. Reference numeral 1 denotes a CCD image pickup device having a mechanism for suppressing reading for each line; 2, a signal processing unit having a mechanism for suppressing control of processing for each line; 3, a horizontal reduction filter; Is a vertical reduction filter and 5 is AN
The D logic element 6 is a dual port memory having a capacity of several lines.

Signal 1 read from CCD image pickup device 1
The signal a is separated into a luminance signal and a chrominance signal by the signal processing unit 2 and is sent to the horizontal reduction filter 3 sequentially as a signal 2a. Note that the CCD imaging device 1 and the signal processing unit 2
It is assumed that the processing can be stopped line by line by the control signal 4c from the horizontal reduction filter 3.

FIG. 2 is a block diagram showing a configuration of a horizontal reduction filter in the image processing apparatus according to the present invention. Reference numeral 10 denotes a counter having input terminals of an operation clock input terminal 7, a horizontal synchronization signal input terminal 8, and a magnification data input terminal 9. 11 and 12 are multipliers, 13 is a one-clock delay element, 14 is a switch, 15 is an adder, and 16 is a one-clock delay element.

Generally, input signals yl, y (l + 1), y
From (l + 2),... So that no aliasing distortion occurs,
In order to calculate the data multiplied by n / M, the original data is weighted by n times (magnification: n), respectively.
It is known that an averaging may be obtained.

That is, n × yl + n × y (l + 1) +... + (Mq × n) × y
A desired value can be obtained by multiplying (l + q + 1) and the input signal by n, adding until the sum of the coefficients reaches M, and finally dividing by M. Then, (n− (M−q × n)) × y (l + q + 1) + n × y
(L + q + 2) +... In the same manner as described above,
Data reduced to a reduction ratio (n / M) can be obtained.

For example, when M = 256 and n = 88, the calculation is performed sequentially as follows: 88 × y0 + 88 × y1 + 80 × y2 8 × y2 + 88 × y3 + 88 × y4 + 72 × y5 16 × y5 + 88 × y6 + 88 × y7 + 64 × y8 Divide by 256. If M = 256 and n = 230, then 230 × y0 + 26 × y1 204 × y1 + 52 × y2 178 × y2 + 78 × y3.

The above operation is realized by the horizontal reduction filter shown in FIG. FIG. 3 is a diagram showing a timing chart of the signal value of each section of the horizontal reduction filter in the processing procedure. In the figure, each value and timing when M = 256 and n = 192 are shown. In the counter 10, the number of bits of the counter is determined by the horizontal reduction ratio (n
/ M), if the denominator M is 2 to the power of p, it is p + 1 bits. Inside the counter 10, the count value reset by the horizontal synchronizing signal input from the horizontal synchronizing signal input terminal 8 is synchronized with the clock from the operation clock input terminal 7 to reduce the count value input from the magnification data input terminal 9. It is assumed that the numerator (n) is counted up. Let the value of the lower p bits of the counted value be k.
The exclusive OR of the value of the most significant bit of the count value and the signal obtained by delaying the most significant bit by one clock is determined as h. A signal that becomes k when the value of h is 1 and becomes 0 when it is 0 is defined as a signal 10b. Signal 1 from magnification n
The value obtained by subtracting 0b is defined as a signal 10a. A signal obtained by delaying h by one clock is defined as a signal 10c. From the counter 10, the signals 10a and 10b are output as signals indicating coefficients, and the signal 10c is output as a control signal.

On the other hand, the digital video signal 2a input from the signal processing unit 2
a, the lower p bits are truncated and the signal 11
The signal is output as “a” and guided to one terminal of the adder 15. Similarly, the signal is multiplied by the signal 10b in the multiplier 12, the lower bits are discarded, and the one-clock delay element 1
3 is delayed by one clock, output as a signal 13 a, and input to the switch 14. In the switch 14, when the value of the control signal 10c is 1, the signal 13a is selected, and when the value of the control signal 10c is 0, the signal 16a to be described later is selectively switched, and is led to the other terminal of the adder 15 as the signal 14a. I will In the adder 15, the signal obtained by adding the signal 11a and the signal 14a is a one-clock delay element 1
6, after being delayed by one clock, the signal is fed back to the switch 14 as a signal 16a.
The signal is sent to the next-stage vertical reduction filter 4 as a horizontal reduction signal 3a reduced by a factor of / M. Also, the control signal 10c
Is used as a signal 3b for determining a valid signal among these signals, and a signal at a timing when the value is 1 is adopted as a valid reduced value.

FIG. 4 is a block diagram showing a configuration of a vertical reduction filter in the image processing apparatus according to the present invention. Reference numeral 21 denotes a counter, 22 denotes a T-decimal counter, each having a horizontal synchronizing signal input terminal 17, a vertical synchronizing signal input terminal 18, and a magnification data input terminal 19. The T-decimal counter 22 further includes a frequency ratio data input terminal 20. Have. 23 and 2
4 is a multiplier, 25 is a line memory, 26 is a switch, 2
7, an adder; and 28, a line memory.

Here, the frequency ratio (i) represents the ratio between the clock for driving the CCD image pickup device 1 and the line frequency of the video signal. The T-ary counter 22 calculates the frequency ratio (i) input from the frequency ratio data input terminal 20,
The count is incremented by a constant N determined by the magnification (m) input from the magnification data input terminal 19, and reset by the constant T.

For example, if the frequency ratio i is 3: 2 and the magnification m
Is 240, and the vertical reduction ratio (m / M) is 240/2.
In the case of 56, T / N = 3/2 × 240/256 = 45/32, and the counter is counted up by 32 and reset by 45.

When the T-decimal counter 22 is not reset, the signal 22a changes from 1 to 0, and as the control signal 4c, the CCD image pickup device 1, the signal processing unit 2, and the counter inside the vertical reduction filter. The operation is stopped at 21. The counter 21 resets the counter value according to the vertical synchronization signal input from the vertical synchronization signal input terminal 18, and synchronizes with the horizontal synchronization signal input from the horizontal synchronization signal input terminal 17 to change the magnification data input terminal 19.
Counts up by the magnification m set from
When the signal 22a from the T-ary counter 22 is 0, the counter value is held. Also, the signal 3a from the horizontal reduction filter 3 at that time is forcibly set to 0.

In the counter 21, the same processing as that of the counter 10 in the horizontal reduction filter 3 is performed, and the signals 10a,
Signals 21a and 21 corresponding to 10b and 10c, respectively.
b and 21c are output. The horizontal reduction signal 3a input from the horizontal reduction filter 3 is multiplied by coefficient signals 21a and 21b in multipliers 23 and 24, and output as signals 23a and 24a, respectively. The signal 23 a output from the multiplier 23 is guided to one terminal of the adder 27.

The signal 24 output from the multiplier 24
a is delayed by 1H in the line memory 25,
The signal becomes a signal 25a and is input to the switch 26. In the switch 26, when the value of the control signal 21c is 1, the signal 25a
Then, at the time of 0, a signal 28a described later is selectively switched and guided to the other terminal of the adder 27 as a signal 26a. The signal added in the adder 27 is delayed by 1H in the line memory 28,
At the same time as the signal 28a is fed back to the switch 26,
The horizontal reduction signal 3a is further reduced in the vertical direction by a reduction ratio m / M.
Is sent to the next-stage dual-port line memory 6 as a signal 4a reduced in size.

The control signal 21c is used as a signal 4b for judging a valid signal among the signals, and has a value of 1
Is used as an effective reduction value. FIG. 5 is a diagram showing a timing chart of signals of each section of the vertical reduction filter in the processing procedure.

The signals recorded in the dual port line memory 6 are continuously read out in synchronization with the video clock, so that the range of the entire effective range of the CCD image pickup device 1 can be changed from the range of the effective pixel number of the video signal. Thus, video data of an area that is continuously variable up to the time can be obtained.

[0021]

According to the present invention, the entire effective range of the solid-state image sensor can be displayed by video signals.
Further, according to the present invention, it is possible to provide a zoom function without deteriorating image quality. Furthermore, according to the present invention, it is possible to perform frequency conversion using only a few lines of memory without using a frame memory.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an embodiment of an image processing apparatus according to the present invention.

FIG. 2 is a block diagram illustrating a configuration of a horizontal reduction filter according to the image processing apparatus of FIG. 1;

FIG. 3 is a time chart showing the timing of reduction processing of the horizontal reduction filter of FIG. 2;

FIG. 4 is a block diagram illustrating a configuration of a vertical reduction filter according to the image processing apparatus of FIG. 1;

FIG. 5 is a time chart showing the timing of the reduction processing of the vertical reduction filter of FIG. 4;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... CCD image sensor, 2 ... Signal processing part, 3 ... Horizontal reduction filter, 4 ... Vertical reduction filter, 5 ... AND logic element,
6 dual port line memory 7 operating clock input terminal 8, 17 horizontal synchronization signal input terminal 9, 19
Magnification data input terminals, 10, 21, ... counter, 11, 1
2, 23, 24 ... multiplier, 13, 16 ... 1 clock delay element, 14, 26 ... switch, 15, 27 ... adder, 1
8: vertical synchronization signal input terminal, 20: frequency ratio data input terminal, 22: T-decimal counter, 25, 28: line memory.

Claims (3)

[Claims] 1. An image processing apparatus for an imaging device using a solid-state imaging device, wherein an image captured by reading an output image signal of the solid-state imaging device in an entire area and reducing the readout image signal in a horizontal direction and a vertical direction. An image processing apparatus characterized in that the image processing apparatus is reduced to an arbitrary magnification with high quality. 2. The image processing apparatus according to claim 1, wherein
When reading the output image signal of the solid-state imaging device in the entire region, by suppressing the line reading of the solid-state imaging device, a part of the region is read out and reduced in the horizontal and vertical directions, thereby providing the same effect as the zoom function. An image processing apparatus, characterized by obtaining: 3. The image processing apparatus according to claim 1, wherein the video signal reduced in the horizontal direction and the vertical direction is stored in a line memory, and the video signal is different from a clock for reading a solid-state image sensor. An image processing apparatus, wherein frequency conversion is performed by reading out a clock synchronized with the clock.