JP3810685B2 - Resolution converter and digital camera - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a resolution conversion apparatus that changes an image size of an image signal by digital processing.
[0002]
[Prior art]
In general, in an imaging device such as a digital video camera or a digital still camera, light transmitted through an optical system including a lens group and a prism is detected by an imaging sensor such as a CCD sensor or a CMOS sensor and converted into an image signal. The The image signal is A / D converted into a digital signal (original image data), and then subjected to various image processing such as pixel interpolation, color space conversion, edge enhancement, and resolution conversion. Thereafter, a liquid crystal display (EVF: Displayed on the electronic viewfinder). The imaging device compresses and encodes image data that has undergone image processing using a method such as JPEG (Joint Photographic Experts Group), Motion JPEG, or MPEG (Moving Picture Experts Group), and then writes it to a memory card such as a non-volatile memory. Or output to an external device such as a personal computer via an interface.
[0003]
In order to change the display magnification of the image displayed on the viewfinder on the EVF, there are a method of physically changing the focal length of the optical system without changing the imaging position and a method of converting the resolution of the image data by digital image processing. is there. As an image enlargement method by digital image processing, an internal division interpolation method (bilinear method) for calculating a weighted average value of a plurality of pixel data of image data, pixel data in an image, and a sinc function (sin (x) / A cubic folding interpolation method (bicubic method) for calculating a folding calculation value with x; x is a variable is known.
[0004]
[Problems to be solved by the invention]
However, the enlargement process for enlarging the image data in real time using hardware has a problem that the hardware configuration is likely to be complex and costly higher than the reduction process for reducing the image data in real time. is there. This problem will be described in detail below with reference to FIGS.
[0005]
FIG. 5 is a schematic diagram showing a main part of a conventional image processing circuit built in a digital camera. In FIG. 5, reference numeral 100 denotes a CCD image pickup device, 101 denotes an analog signal processing unit, 102 denotes an RPU (real time processing unit), 103 denotes a memory bus, 104 denotes main memory, and 106 denotes a CPU (central processing unit). Is shown. The RPU 102, the main memory 104, and the CPU 106 are connected to the memory bus 103.
[0006]
The RPU 102 is an integrated circuit having a plurality of functional blocks 107 to 111, specifically, a pixel unit processing unit 107 that processes input image data in units of pixels, and pixel interpolation that performs pixel interpolation processing and gamma correction processing. A gamma processing unit 108, a color space conversion / color suppression processing unit 109 that performs color space conversion processing and color suppression (chroma suppress) processing, and a spatial filter core that performs spatial filtering processing and coring processing The ring processing unit 110 includes a resolution conversion processing unit 111 that reduces the size of input image data within a range of 1.0 to 1/128 times. The functional blocks 107 to 111 are connected in multiple stages, can operate independently from each other, can execute processing on input data in parallel, and can pass the execution result to the next functional block.
[0007]
The operation of the image processing circuit having the above configuration is as follows. Incident light from the subject passes through an optical system (not shown) such as a lens and is received by the CCD image sensor 100. The CCD image sensor 100 photoelectrically converts incident light, generates an analog image signal, and outputs the analog image signal to the analog signal processing unit 101. The analog signal processing unit 101 sequentially performs CDS (Correlated Double Sampling) processing, AGC (Automatic Gain Control) processing, and A / D conversion processing on the input analog image signal. The obtained digital image signal (original image data) 200 is output to the RPU 102.
[0008]
The original image data 200 output from the analog signal processing unit 101 can be selectively input to either the pixel unit processing unit 107 or the pixel interpolation / gamma processing unit 108. After the original image data 200 is sequentially processed by the functional blocks 107 to 110, the pixel data 202 output from the spatial filter / coring processing unit 110 is stored in a buffer area on the main memory 104 via the memory bus 103. The main image data 112 is configured by being transferred to and stored in the main image data 112. In many digital still cameras, a main image is generated and a low-resolution thumbnail image for the heading is also generated. The thumbnail images are often helped when editing and organizing the main image. The resolution conversion processing unit 111 outputs pixel data 203 so as to reduce the size of the image data input from the spatial filter / coring processing unit 110, and the pixel data 203 is transmitted to the main memory 104 via the memory bus 103. The thumbnail image data 113 is formed by being transferred and stored in the upper buffer area.
[0009]
Further, in post-processing (post-processing), the pixel data 201 stored in the main memory 104 can be read out and transferred again to the RPU 102 via the memory bus 103 for image processing.
[0010]
The functional blocks 107 to 111 of the RPU 102 execute image processing based on a pixel clock (not shown) supplied from the outside. When the resolution conversion processing unit 111 executes an image size reduction process, the resolution conversion processing unit 111 may output one pixel data during a period in which a plurality of pixel data is input. For example, when the image data is reduced by a factor of 1/2 in the horizontal pixel direction, one pixel data may be output during the input period of two pixel data in each horizontal line. Further, when the image data is reduced by a factor of 1/2 in the vertical pixel direction, the pixel data for one line may be output during the input period of the pixel data for two lines. However, when the image size is enlarged n times (n: an integer of 2 or more), it is necessary to interpolate and output n pixel data during the input period of one pixel data. Therefore, if the resolution conversion processing unit 111 is to be provided with a function for enlarging the size of the image data, a processing speed using a clock faster than the pixel clock that regulates the overall processing speed of the RPU 102 is required. There arises a problem that the circuit configuration becomes complicated and the circuit scale increases. One method for avoiding this problem is post processing.
[0011]
FIG. 6 is a schematic diagram showing a circuit configuration example of the RPU 102 that enlarges image data twice in the vertical pixel direction using the post processing. Although not explicitly shown in FIG. 6, the original image data 200 is sequentially processed by the functional blocks 107 to 110 of the RPU 102 and then becomes main image data 112 in the same manner as the operation of the circuit shown in FIG. 5. The data is transferred to the main memory 104 via the bus 103 and stored. When the partial image data 112 a in the main image data 112 is enlarged, the pixel data 204 of the partial image data 112 a is read from the main memory 104 and transferred to the RPU 102 via the memory bus 103. Next, the pixel data 204 passes through the function blocks 107 to 111 of the RPU 102, and then the pixel data 205 and 206 whose resolution is converted according to the enlargement ratio from the resolution conversion processing unit 111 are respectively “0” of the selector 115. It is output to the side terminal and the line memory (FIFO memory) 118. The resolution conversion processing unit 111 has a function of converting the size of input image data within a range of 2.0 times to 1/128 times. In the case of this example, since the image size is doubled, the resolution conversion processing unit 111 outputs two pieces of pixel data 205 and 206 of two upper and lower lines in one cycle of the pixel clock.
[0012]
The line memory 118 has a capacity for storing pixel data for one horizontal line. The selector 115 selects the pixel data 205 to be input to the “0” terminal while the logic level of the selection signal supplied from the timing controller (not shown) is “0”, and the logic level of the selection signal In the period of “1”, the supply of the pixel clock to each of the functional blocks 107 to 111 is interrupted, and the selector 115 selects and outputs the pixel data 206 input to the “1” terminal. The logic level of the selection signal is switched from “0” to “1” or “1” to “0” and output every time pixel data for one horizontal line is output from the resolution conversion processing unit 111. The pixel data is addressed line-sequentially according to the enlargement ratio and transferred to the main memory 104. Thereby, in the case of this example, the enlarged image data 117 obtained by enlarging the image size up to twice in the vertical pixel direction can be stored in the buffer area of the main memory 104.
[0013]
However, in the circuit shown in FIG. 6, it is necessary to incorporate one line memory 118 in the RPU 102 in order to enlarge the image size up to twice. In general, when the image size is enlarged n times (n: an integer greater than or equal to 2) in the vertical pixel direction, the resolution conversion processing unit 111 has a resolution conversion function of n times at the maximum and n-1 lines. There is a problem that a memory is required, and this line memory causes an increase in circuit scale and cost.
[0014]
An object of the present invention in view of the above-described problems is to provide a low-cost resolution conversion device that can increase the image size in real time.
[0015]
[Means for Solving the Problems]
  In order to solve the above-described problem, the invention according to claim 1 is a resolution conversion device that stores in real time a converted image obtained by converting the resolution of an original image expressed by the image signal based on an image signal input in real time. A memory that stores a converted image, an image processing unit that outputs converted pixel data constituting the converted image while performing image processing on the image signal, and converted pixel data output from the image processing unit Data transfer means for storing the converted image on the memory by transferring the image to the memory, and the image processing unit is configured to store one of the reduced images obtained by reducing the original image based on the image signal. A size reduction processing unit that outputs reduced pixel data constituting a line, and a copy of the reduced pixel data output from the size reduction processing unit,A selector that outputs duplicate pixel data, and a selector that selects one of the image signal and duplicate pixel data output from the duplicate unit based on a selection signal input from outside and outputs the selected pixel data as selected pixel data And output means for outputting the selected pixel data output from the selector and the reduced pixel data output from the size reduction processing unit as converted pixel data.HaveWhen the selector selects an image signal, the data transfer means transfers the selected pixel data out of the converted pixel data output from the image processing unit to the memory as pixel data constituting one image. When storing as a main image and transferring reduced pixel data to the memory as pixel data constituting one image and storing a sub-image as a converted image, while the selector selects duplicate pixel data,The data transfer means is converted pixel data output from the image processing unit.The selected pixel data and reduced pixel data included inSpecify the write address and transfer it to the memoryThe selected pixel data and the reduced pixel dataAn enlarged image obtained by enlarging the original image is stored as a converted image by storing it as pixel data constituting one image.
[0019]
  Claim 2The invention according toClaim 1The resolution conversion apparatus according to claim 1, wherein the data transfer means is a DMA (Direct Memory Access) controller having a plurality of DMA channels for performing transfer control of converted image data output from the image processing unit, The DMA controller is characterized in that each DMA channel is assigned to each line for converted pixel data constituting a plurality of lines output from the image processing unit.
[0020]
  Claim 3The invention according to claim 1 receives an incident light transmitted through an optical system, photoelectrically converts the incident light to generate and output an analog image signal, an analog signal processing unit that converts the analog image signal into a digital image signal, andOr 2A digital camera comprising: means for inputting the digital image signal to an image processing unit of the resolution conversion apparatus according to 1).
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, various embodiments of the present invention will be described.
[0022]
Embodiment 1 FIG.
FIG. 1 is a schematic diagram showing the configuration of the main part of the resolution conversion apparatus according to Embodiment 1 of the present invention. This resolution conversion apparatus includes an RPU (Real Time Processing Unit) 12 that performs image processing on input image data in real time, a main memory 13 including SDRAM (Synchronous Dynamic Random Access Memory), and a DMA (Direct A memory access controller 14 and a CPU 15 are provided. These RPU 12, main memory 13, DMA controller 14, and CPU 15 are all connected to a memory bus 21.
[0023]
This resolution converter is incorporated in a digital camera. The digital camera includes an optical system (not shown) including a lens group, a CCD image sensor 10 that photoelectrically converts incident light transmitted through the optical system to generate and output an analog image signal, and the CCD image sensor. An analog signal processing unit 11 that sequentially performs CDS processing, AGC processing, and A / D conversion processing on an analog image signal input from 10 to generate a digital image signal (original image data) 30 and outputs the digital image signal to the RPU 12. ing.
[0024]
The DMA controller 14 arbitrates a plurality of DMA channels CH0, CH1,... For controlling data transfer via the memory bus 21 and an execution order between the DMA channels CH0, CH1,. ) And the like, and has a hardware function of directly transferring data between the RPU 12 and the main memory 13 through the memory bus 21 without using the CPU 15. When the DMA controller 14 receives the DMA request, it requests the CPU 15 to release the right to use the memory bus 21. When the CPU 15 can release the memory bus 21, it issues a permission signal for use of the memory bus 21 to the DMA controller 14. Upon receiving this permission signal, the DMA controller 14 places the memory bus 21 in a high impedance state, and in this state, the DMA channels CH0 and CH1 generate addresses of access destinations on the main memory 13 and the RPU 12 Is transferred to the main memory 13 via the memory bus 21. After the data transfer is completed, the RPU 12 returns the right to use the memory bus 21 to the CPU 15.
[0025]
The RPU 12 is an integrated circuit having a plurality of functional blocks 16, 17, 18, 19, and 20 that perform image processing. The functional blocks 16 to 20 can operate independently of each other, and execute processing on input data in parallel. Thus, it has a pipeline function capable of passing the execution result to the next function block. In the present embodiment, functional blocks of a pixel unit processing unit 16, a pixel interpolation / gamma processing unit 17, a color space conversion / color suppression processing unit 18, a spatial filter / coring processing unit 19, and a resolution conversion processing unit 20 are shown. However, it is not limited to these.
[0026]
The outline of the processing content of each functional block 16-20 is as follows. The pixel unit processing unit 16 is a functional block that processes the image signal 30 input from the analog signal processing unit 11 in units of pixels. Specifically, the pixel unit processing unit 16 performs a temporal averaging process that averages the input image signal 30 over a plurality of frames or fields, and a shading correction process that corrects light and dark unevenness in the image. be able to.
[0027]
The pixel interpolation / gamma processing unit 17 is a functional block that executes pixel interpolation processing for interpolating an insufficient color component for each pixel with reference to surrounding pixels and gamma correction processing for correcting gamma characteristics of an image. is there. The single-chip CCD image sensor 10 such as the Bayer method can obtain only a single color component for each pixel, and therefore pixel interpolation processing is performed so that each pixel has a plurality of color components with reference to peripheral pixels of the pixel to be processed. Made. For example, in the primary color single-plate CCD image sensor 10, each pixel has only one of R (red), G (green), and B (blue) color components. Using the color components, interpolation processing is executed so that each pixel has three color components of R, G, and B.
[0028]
The color space conversion / color suppression processing unit 18 executes color space conversion processing for converting the color space of the image, and color suppression processing for suppressing color development in a bright portion and a dark portion in an image in which white balance is likely to go wrong. It is a functional block. In the color space conversion process, for example, a process of converting a primary color RGB color space into a YCbCr color space or a YUV color space composed of one luminance component and two color difference components is executed.
[0029]
In addition, the spatial filter / coring processing unit 19 performs functional filtering that performs spatial filtering processing using a spatial filter (weight mask) and nonlinear processing (coring processing) that mainly suppresses high frequency components of the image signal. It is. In the spatial filtering process, a spatial filter having a coefficient value corresponding to each pixel is applied to a local area of about 5 × 5 pixels in the image signal, and each pixel data is weighted (multiplied) and added. A product-sum operation is performed. By appropriately setting the coefficient value, it is possible to emphasize lines and edge portions in the image and remove noise.
[0030]
The resolution conversion processing unit 20 is a functional block that executes processing for reducing the resolution of an image signal, that is, processing for reducing the image size and reducing the number of pixels. In order to simplify the circuit configuration, the resolution conversion processing unit 20 does not incorporate a function for enlarging the image size.
[0031]
  In post-processing, the pixel data 31 stored in the main memory 13 is read out, and the memory bus21It is also possible to transfer the image data to the RPU 12 again and perform image processing.
[0032]
The operation of the resolution conversion apparatus having the above configuration is as follows. The pixel data output from the spatial filter / coring processor 19 is duplicated and output as two pixel data 32 and 33 having the same pixel value. Although not explicitly shown in the figure, these two pieces of pixel data 32 and 33 are respectively stored in a FIFO memory circuit (not shown) before being output to the memory bus 21. The DMA controller 14 acquires the right to use the memory bus 21 from the CPU 15, and assigns DMA channels CH0 and CH1 to the two FIFO memory circuits that store the two pixel data 32 and 33, respectively. In such a state, the DMA controller 14 issues a permission signal for permitting data output to each FIFO memory circuit in a time-sharing process, and the DMA channels CH0 and CH1 cooperatively set the write address on the main memory 13. Generate sequentially in line units. Further, the pixel data is output to the main memory 13. As a result, the pixel data 32 and 33 transferred to the main memory 13 are alternately written with a shift of one line at a time in units of lines, so that the image data 22 enlarged twice in the vertical pixel direction is formed. It will be.
[0033]
Thus, according to the resolution conversion apparatus according to the first embodiment, when the pixel data output from the RPU 12 in real time is transferred to the main memory 13, the resolution is doubled and the main memory 13 is converted. Can be stored. Therefore, it is possible to realize a resolution converter with a simple configuration and low cost that can simultaneously execute high-speed and large-capacity image signal data transfer and real-time image size enlargement processing.
[0034]
In the first embodiment, the resolution of the image data is doubled in the vertical pixel direction using the two DMA channels CH0 and CH1, but the present invention is not limited to this, and n DMA channels are used. It is also possible to enlarge the resolution of the image data n times in the vertical pixel direction using channels CH0, CH1,..., CHn (n: an integer of 2 or more). In such a case, the pixel data output from the spatial filter / coring processing unit 19 is copied into n pixel data and stored in the n FIFO memory circuits, and the n FIFO memory circuits and the main memory 13 are connected. It is only necessary to assign DMA channels CH0,.
[0035]
Modification of the first embodiment.
FIG. 2 is a schematic configuration diagram showing a main part of a resolution conversion apparatus according to a modification of the first embodiment. The resolution conversion apparatus according to this modification has the same configuration and the same function as the resolution conversion apparatus shown in FIG. 1 except for the points described below. The RPU 12B of this modification includes functional blocks 16 to 19 that are the same as the functional blocks shown in FIG. 1 and a resolution conversion processing unit 20B. The resolution conversion processing unit 20B has a size reduction function for reducing the image size by reducing the resolution at a reduction ratio of 1.0 to 1/128 times in one or both of the vertical pixel direction and the horizontal pixel direction. .
[0036]
The operation of the resolution conversion apparatus according to this modification is as follows. The execution result of the spatial filter / coring processor 19 is transferred to the resolution conversion processor 20B. The resolution conversion processing unit 20B reduces the resolution of the image signal input from the spatial filter / coring processing unit 19 at a reduction rate specified by the CPU 15 or the like, and outputs the pixel data obtained as a result.
[0037]
Next, the pixel data output from the resolution conversion processing unit 20B is duplicated and output to two pixel data 34 and 35 having the same pixel value. These two pieces of pixel data 34 and 35 are each stored in a FIFO memory circuit (not shown) before being output to the memory bus 21. The DMA controller 14 obtains the right to use the memory bus 21 from the CPU 15, and assigns DMA channels CH0 and CH1 to the two FIFO memory circuits that store the two pixel data 34 and 35, respectively. In this state, the DMA controller 14 issues a permission signal for permitting data output to each FIFO memory circuit in a time-sharing process, and the DMA channels CH0 and CH1 cooperate with each other to generate the two pixel data 34, For 35, the transfer destination address on the main memory 13 is sequentially generated in units of lines. Further, the pixel data is output to the main memory 13. As a result, the pixel data 34 and 35 transferred to the main memory 13 are alternately written in line units, so that the image data 22 that is doubled in the vertical pixel direction is formed.
[0038]
As described above, in this modification, since the image size of the image signal 30 input to the RPU 12B can be reduced after being reduced, it is possible to easily obtain image data having a desired resolution. As a result, it is possible to adjust the aspect ratio of the image data in real time.
[0039]
Embodiment 2. FIG.
Next, a second embodiment of the present invention will be described. 3 and 4 are schematic configuration diagrams showing main parts of the resolution conversion apparatus according to the second embodiment. In FIG. 3 and FIG. 4, components having the same reference numerals as those shown in FIG. 1 have the same functions as the components shown in FIG.
[0040]
The RPU 12C of the resolution conversion apparatus according to the second embodiment has the same functional blocks 16 to 19 as the functional blocks of the RPU 12 of the first embodiment and 1.0 times in one or both of the vertical pixel direction and the horizontal pixel direction. A resolution conversion processing unit 20B that reduces the resolution at a reduction ratio of ˜1 / 128 times, a register 39 that holds a selection signal SC designated by the CPU 15 or the like, and a selector 36 are provided.
[0041]
  The selector 36 is a signal input to either the “0” side terminal or the “1” side terminal depending on whether the logic level of the selection signal SC supplied from the register 39 is “0” or “1”. Select to output. The pixel data output from the spatial filter / coring processing unit 19 is input to the “0” side terminal of the selector 36, and the pixel data 41 output from the resolution conversion processing unit 20B is input to the “1” side terminal.(Pixel data 38 in FIG. 4)Is typing. The selector 36 selects one of the pixel data and outputs it as pixel data 40.
[0042]
The resolution conversion apparatus according to the second embodiment simultaneously generates the first mode in which the image data whose image size has been changed is stored in the main memory 13 and the above-described main image and thumbnail image, and stores them in the main memory 13. The second mode can be switched freely. Hereinafter, the operation will be described.
[0043]
  First, in the first mode, as shown in FIG. 3, the selection signal SC having the logic level “1” is transferred from the CPU 15 to the register 39 and held.Therefore, the selector 36 selects the pixel data 41 input to the “1” terminal and outputs it as pixel data 40.At this time, the resolution conversion processing unit 20B outputs pixel data 41 with reduced resolution.ThisThese two pieces of pixel data 40 and 41 are each stored in a FIFO memory circuit (not shown) before being output to the memory bus 21. The DMA controller 14 obtains the right to use the memory bus 21 from the CPU 15, and assigns DMA channels CH0 and CH1 to the two FIFO memory circuits storing the two pixel data 40 and 41, respectively. In this state, the DMA controller 14 issues a permission signal to each FIFO memory circuit in a time-sharing process, and the DMA channels CH0 and CH1 cooperate to transfer the two pixel data 40 and 41 on the main memory 13. Addresses are generated sequentially in line units. Further, the pixel data is output to the main memory 13. As a result, the pixel data 40 and 41 transferred to the main memory 13 are alternately written in line units, so that the image data 25 enlarged twice in the vertical pixel direction is formed.
[0044]
  On the other hand, in the second mode, as shown in FIG. 4, the selection signal SC having the logic level “0” is transferred from the CPU 15 to the register 39 and held. At this time, the selector 36 selects the pixel data 37 output from the spatial filter / coring processor 19 and input to the “0” side terminal.As pixel data 40Then, the resolution conversion processing unit 20B outputs pixel data 38 with reduced resolution. Although not shown in the figure, these two pixel data38, 40 (same data as pixel data 37)Are stored in a FIFO memory circuit (not shown) before being output to the memory bus 21. The DMA controller 14 acquires the right to use the memory bus 21 from the CPU 15, and assigns DMA channels CH0 and CH1 to the FIFO memory circuit, respectively. In such a state, the DMA controller 14 issues a permission signal for permitting data output to each FIFO memory circuit in a time-sharing process, and the DMA channels CH0 and CH1 cooperate to cooperate with the two pixel data.38, 40The transfer destination address on the main memory 13 is generated so as to designate different buffer areas. As a result, two pixel data38, 40Are transferred to the main memory 13, and the main memory 13 has a high resolution.mainImage data (main image) 23 and thumbnail image data (sub-image) 24 having a low resolution are stored.
[0045]
  As described above, according to the second embodiment, pixel data output in real time from the RPU 12C can be obtained by simply controlling the logic level of the selection signal SC supplied to the selector 36. Separated into sub-images and stored in main memory 13SecondThe mode and the image size are enlarged in real time and stored in the main memory 13FirstIt is possible to freely switch to either one of the modes. Moreover, the switching can be realized with a simple circuit configuration.
[0046]
【The invention's effect】
  As described above, according to the resolution conversion apparatus of the first aspect of the present invention, when the image signal output in real time from the image processing unit is transferred to the memory, the resolution is converted to n times and stored in the memory. It is possible to memorize. Therefore, it is possible to realize a low-cost resolution conversion apparatus that has a simple configuration that increases the image size in real time.
  In addition, since the image size of the image signal input to the image processing unit can be reduced after being reduced, image data having a desired resolution can be obtained. For example, adjustment of the aspect ratio of image data can be executed in real time.
[0047]
  Claim 2 andClaim 4According to the present invention, each of the DMA channels of the DMA controller is assigned to n pixel data output from the image processing unit for each line, so that data transfer from the image processing unit to the memory and image enlargement processing are performed in real time. Can be executed efficiently.
[0049]
  Claim 3According to the first aspect, the image data output in real time from the image processing unit is stored in the memory separately into the high-resolution main image and the low-resolution sub-image only by controlling the selection signal supplied to the selector. It is possible to switch between the first mode and the second mode in which the image size of the image data is enlarged in real time and stored in the memory, and a simple configuration and low cost resolution conversion apparatus can be realized. Is possible. For example, in the first mode, a main image and its thumbnail image (sub-image) can be simultaneously created and stored in the memory.
[0050]
  Claim 5With the digital camera according to the above, it is possible to enlarge the image size in real time and store it in the memory without temporarily storing the captured image signal in the memory.
[Brief description of the drawings]
FIG. 1 is a schematic diagram showing a configuration of a main part of a resolution conversion apparatus according to Embodiment 1 of the present invention.
FIG. 2 is a schematic configuration diagram showing a main part of a resolution conversion apparatus according to a modification of the first embodiment.
FIG. 3 is a schematic configuration diagram showing a main part of a resolution conversion apparatus according to a second embodiment.
FIG. 4 is a schematic configuration diagram showing a main part of a resolution conversion apparatus according to a second embodiment.
FIG. 5 is a schematic diagram showing a conventional example of an image processing circuit built in a digital camera.
FIG. 6 is a schematic diagram showing another conventional example of an image processing circuit built in a digital camera.
[Explanation of symbols]
10 CCD image sensor
11 Analog signal processor
12 RPU
13 Main memory
14 DMA controller
15 CPU
16 pixel unit processing unit
17 Pixel interpolation / gamma processing section
18 Color space conversion / color suppression processing unit
19 Spatial filter and coring processor
20 Resolution conversion processor
21 Memory bus
23 Enlarged image data

Claims (3)

A resolution conversion device that stores in real time a converted image obtained by converting the resolution of an original image represented by the image signal based on an image signal input in real time,
A memory for storing the converted image;
An image processing unit that outputs converted pixel data constituting a converted image while performing image processing on the image signal;
Data transfer means for storing the converted image on the memory by transferring the converted pixel data output from the image processing unit to the memory;
With
The image processing unit
A size reduction processing unit that outputs reduced pixel data constituting one line of a reduced image obtained by reducing the original image based on the image signal;
A duplicating unit that duplicates the reduced pixel data output from the size reduction processing unit and outputs duplicate pixel data;
Based on a selection signal input from the outside, a selector that selects any one of the image signal and the replicated pixel data output from the replication unit and outputs the selected pixel data; and
Output means for outputting selected pixel data output from the selector and reduced pixel data output from the size reduction processing unit as converted pixel data;
Have
When the selector selects an image signal,
The data transfer means transfers selected pixel data from the converted pixel data output from the image processing unit to the memory as pixel data constituting one image and stores it as a main image, and reduces reduced pixel data. Transferring to the memory as pixel data constituting one image and storing a sub-image as a converted image;
On the other hand, when the selector selects duplicate pixel data,
The data transfer means transfers the selected pixel data and the reduced pixel data included in the converted pixel data output from the image processing unit to the memory by alternately specifying a write address in line units, and transferring the selected pixel data to the memory. A resolution conversion apparatus characterized in that an enlarged image obtained by enlarging the original image is stored as a converted image by storing the reduced pixel data as pixel data constituting one image. The resolution conversion device according to claim 1,
The data transfer means is a DMA (direct memory access) controller having a plurality of DMA channels for performing transfer control of converted pixel data output from the image processing unit,
The DMA controller
A resolution conversion apparatus, wherein a DMA channel is assigned to each line of conversion pixel data constituting a plurality of lines output from the image processing unit. An image sensor that receives incident light transmitted through the optical system, photoelectrically converts the incident light to generate and output an analog image signal;
An analog signal processing unit for converting the analog image signal into a digital image signal;
Means for inputting the digital image signal to an image processing unit of the resolution conversion apparatus according to claim 1;
A digital camera characterized by comprising:

Images