JP2002108701A - Multiport memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To secure the number of more ports than usual with simple constitution by using a single-port memory without having any complicated arbitrating means. SOLUTION: A control sequence has prescribed cycles and the timing of access to a DRAM 4 for each input/output system in one cycle of the control sequence is fixed, and serial-parallel converting circuits 1a and 1b performs serial-parallel conversion in synchronism with write request timing from outside and write buffers 2a and 2b store the outputs of serial-parallel conversion 1a and 1b in synchronism with the phase of the control sequence. A delay serial signal is outputted from the serial-parallel converting circuit 1b and inputted to the serial-parallel converting circuit 1a, and thus the serial-parallel converting circuits 1a and 1b convert serial data inputted at a double speed into parallel data in one cycle of the control sequence and write them to the DRAM 4 at a normal speed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DRAM which is used for, for example, a video camera and stores digital signals.
And the like. In particular, the present invention relates to a multiport memory device capable of simultaneously writing or reading a plurality of systems of continuous serial data such as image data simultaneously. The present invention also relates to an imaging device such as a digital video camera and a digital still camera using the memory device.

[0002]

2. Description of the Related Art As image memories used in video cameras and the like, there are a dual-port memory generally called a VRAM and a memory having a FIFO structure called a field memory.

[0003]

However, in order to realize higher functionality and higher image quality, the number of ports that can be accessed simultaneously in these image memories is limited.
There is a problem that the required number of ports cannot be secured depending on the application.

As a solution to this problem, a method of increasing the number of image memories to be used or increasing the operating frequency of the image memory to twice the data synchronizing frequency or the like to write / write data is performed.
A method of speeding up memory access by performing rate conversion in the reading portion and increasing the number of systems that can be accessed simultaneously at the same time is considered.

However, the former method has a problem that the size is increased, and the latter method has a problem that power consumption is increased.

An image memory having three or more ports can independently handle the operation clocks of each port and each image memory in order to enhance versatility, but the arbitration means for arbitrating access to the memory between ports is complicated. And it was difficult to increase the number of ports.

The present invention solves the above-mentioned problems, and provides a multi-port memory device which can secure a larger number of ports than the conventional one without using a single port memory and having a simple configuration and without complicated arbitration means. The purpose is to do.

[0008]

According to a first aspect of the present invention, there is provided a multi-port memory device, wherein serial data is converted from serial data into parallel data every predetermined number of data, and parallel data is output. Are provided at a serial data input end of at least one of a plurality of serial-parallel conversion means for outputting separately from parallel data delayed serial data obtained by time-shifting serial data by a predetermined number of delay stages. Serial data selection and output means for selecting and outputting one of serial data of external input and delayed serial data output from another serial-parallel conversion means, and temporarily outputting the outputs of a plurality of serial-parallel conversion means. Select and output the write buffer to be stored and a part of the output of the write buffer. A write data selection output means, a memory for outputting the write data selection output means is written,
A read buffer for temporarily storing data read from the memory, one or more parallel-serial converters for parallel-serial conversion of the output of the read buffer for each output system, and an output of one or more parallel-serial converters One or more delay adjusting means for delaying
The system includes a memory control unit that performs writing / reading and address control of the memory, and a sequence generation unit that generates a control sequence for each operation of the write buffer, the write data selection output unit, the read buffer, and the memory control unit.

The control sequence generated by the sequence generation means has a predetermined period, and is one of the control sequences.
The access timing and access order to the memory for each input / output system in the cycle are fixed.

The serial-to-parallel converter performs serial-to-parallel conversion in synchronization with an external write request timing.

The write buffer temporarily stores the output of the serial-parallel converter in synchronization with the phase of the control sequence output from the sequence generator.

The read buffer temporarily stores data read from the memory in synchronization with the phase of the control sequence output from the sequence generating means.

The delay adjuster delays the output of the parallel-serial converter based on the difference between the external read request timing and the phase of the control sequence so as to match the external read request timing.

When the serial data of the external input is at a normal double speed, the serial data of the external input is supplied to another serial-parallel conversion means.

The serial data selection and output means selects the delayed serial data output from another serial-parallel conversion means when the serial data of the external input is a normal double speed, and selects the serial data within one cycle of the control sequence. The operation is performed in a double speed write mode in which external input serial data is stored in a memory using an access period for two ports.

According to this configuration, the sequence of the access timing of each port of the input / output system to the memory is periodically fixed by the sequence generating means, and the write data of the input system is synchronized with the access timing. The data is temporarily stored and held in the write buffer, and the read data of the output system is read out at a fixed access timing and then delayed by the delay adjusting means so as to match the read request timing. Access arbitration is not required, the number of ports can be easily increased, and many input / output ports can be obtained.

[0017] At least one of the plurality of serial-parallel conversion means outputs, separately from the parallel data, delayed serial data obtained by time-shifting the serial data by a predetermined number of delay stages. A serial data selection output means is provided at at least one serial data input terminal of the parallel conversion means, and selects and outputs one of serial data of an external input and delayed serial data output from another serial-parallel conversion means. The serial data selection output means selects the delayed serial data output from the other serial-parallel conversion means when the serial data of the external input is the normal double speed. Input to memory using the access period of 2 ports at It is possible to operate at double speed write mode for storing the serial data.

At this time, when writing the serial data in the double speed mode to the memory, a normal speed clock can be used for both the write clock and the read clock for the circuits after the write buffer, particularly for the memory, and the serial input of the double speed input can be used. Even when data is written to the memory, power consumption does not increase.

Also, in the case of performing double-speed writing, since writing is performed using a clock at a normal speed and there is no need to switch the writing clock of the memory, it is necessary to guarantee the data stored in the memory. Can be.

In addition, both normal-speed serial data and double-speed serial data can be written in one memory.
Even when it is necessary to process both normal-speed serial data and double-speed serial data, only one multi-port memory device that operates at a normal-speed clock is required. Even when the input speed of serial data is different, image processing can be performed with only one multiport memory device, so that the configuration of the imaging device can be simplified, and miniaturization and cost reduction can be realized.

Further, when writing and processing image data having a large number of pixels such as a still image in the double speed mode, the read side of the memory can be operated at the normal speed.
The still image can be easily displayed on the monitor screen by using the display means for displaying the moving image as it is.

According to a second aspect of the present invention, there is provided an imaging apparatus comprising:
When dedicated image sensors are used for (red), G (green), and B (blue), respectively, and the pixel arrangement intervals in the horizontal and vertical directions of the image sensors are Ph and Pv, respectively, the G image sensors are R and An image pickup device of a three-chip system that performs an oblique pixel shift arrangement in which the image sensor for B is shifted by (Ph / 2 + a) and (Pv / 2 + b) (a and b are constants) in the horizontal and vertical directions, respectively. A multi-port memory device for storing pixel output signals of the R, G, and B image sensors, and a luminance signal generating unit.

The luminance signal generating means receives the pixel output signal of the image sensor for R, G, B or the output signal of the multiport memory device as an input, and outputs the pixel output signal of the image sensor for R and B, and R and B The number of pixels in the horizontal direction is twice that of the G image sensor by using the pixel output signal of the G image sensor positioned spatially nearest to the lower left or lower right of the pixels of the B image sensor. , And a pixel output signal of the R and B image sensors and a pixel output signal of the G pixel which is spatially located at the upper left nearest neighbor or the upper right nearest neighbor with respect to the pixels of the R and B image sensors. The number of pixels in the horizontal direction is twice that of the G image sensor using the pixel output signal of the image sensor of
To create a luminance signal.

The multi-port memory device is as described in claim 1, and is controlled to be in the double speed mode when storing the first and second luminance signals.

According to this configuration, the two write ports in the multiport memory device can be handled as one port, so that data at twice the memory access speed can be written. Therefore, by using this multi-port memory device as an image pickup device, the drive frequency of the memory can be set to a normal value even in a mode requiring a double-speed writing operation (for example, a still image shooting mode using a CCD shifted in pixels). It can be executed while maintaining the state, and the memory for storing two different signals (the RGB signal storage memory and the Y signal storage memory).
1, Y2, C signal storage memory) can be shared by one memory. Further, the memory drive frequency is set to 2
fs, the power consumption of the memory can be reduced as compared with the method of performing the data read operation every other clock.

[0026]

Embodiments of the present invention will be described below with reference to the drawings.

[First Embodiment] FIG. 1 is a block diagram showing the entire configuration of a multiport memory device according to an embodiment (corresponding to claim 1) of the present invention. Each of FIGS. 2 to 6 is a block diagram showing a specific configuration of a main part of the multiport memory device of FIG.

First, the configuration of a multiport memory device according to an embodiment of the present invention will be described with reference to FIGS. 1 to 6.

In FIG. 1, as an example, a four-port multiport memory device having four input / output ports, specifically, two input ports (WA port, WB port) and two output ports (RA port, RB port) Is shown. The multiport memory device includes serial-parallel conversion circuits 1a and 1b as serial-parallel conversion means for performing serial-parallel conversion, write buffers 2a and 2b for temporarily storing data, and a selector as write data selection output means. 3a, 3b, 3c and DR as a memory
AM4 and a read buffer 5a for temporarily storing data.
5b and a parallel-serial conversion circuit 6 as parallel-serial conversion means for performing parallel-serial conversion
a, 6b and a delay adjustment circuit 7a,
7b, a DRAM controller 8 as a memory control unit, a sequence generation circuit 9 as a sequence generation unit, and a selector 1 as a serial data selection output unit.
0. This multiport memory device is, for example, mixedly mounted on the same circuit board as a microprocessor, and its data bit width is 128 to
This is about 256 bits, which is larger than that of a single memory.

The above-described serial-parallel conversion circuit 1
a and 1b operate in accordance with the clock WCK, and the circuits downstream of the write buffers 2a and 2b, the DRAM controller 8 and the sequence generation circuit 9 use the clock DCK.
Works according to

FIGS. 2 to 6 show the serial-parallel conversion circuit 1a, write buffer 2a, read buffer 5a, parallel-serial conversion circuit 6a,
FIG. 3 is a block diagram showing a more detailed configuration example of a delay adjustment circuit 7a.

Here, the input data WSDA and WSDB are, for example, time-series data having a data width of 12 bits and synchronized with the clock WCK, and the access data width of the DRAM 4 is, for example, 120 bits. The bit width is not limited to these. The clock WCK is the clock D in the normal mode.
The frequency is the same as that of CK, and is twice the frequency of the clock DCK in the double speed mode.

The serial-to-parallel conversion circuit 1a has the configuration shown in FIG.
As shown in FIG. 7, external signals WSTRBA and WSTRBB are provided by a 40-stage shift register 21 and a mode switching signal MODE for switching between a normal mode and a double speed mode.
And a register 23 that performs a load and hold operation of the output of the shift register 21 using the output signal WSTRB2A of the selector 22 as a control signal. The shift register 21 and the register 23 operate according to the clock WCK. The serial-parallel conversion circuit 1a converts the serial data WSD2A input from the selector 10 into parallel data WPDA at the timing of the output signal WSTRB2A of the selector 22, and outputs the parallel data WPDA. Note that the selector 22 outputs the external signal WSTR in the normal mode.
BA is selectively output, and in the double speed mode, the external control signal WSTRBB is selectively output.

The serial-to-parallel conversion circuit 1b has the configuration shown in FIG.
As shown in the figure, a shift register 31 of forty stages and a shift register 3 using an external control signal WSTRBB as a control signal.
And a register 32 for performing a load and hold operation of the output of the register 1. The shift register 31 and the register 32 operate according to the clock WCK. The shift register 31 converts the serial data WSDB input from the outside into parallel data WPDB at the timing of the external signal WSTRBB and outputs the parallel data WPDB, and also converts the serial data WSDB from the last stage of the shift register 31 into a predetermined number of delay stages ( The delayed serial data DLYWSDB shifted in time by (in this example, 40 stages) is output and supplied to the selector 10. The above-mentioned predetermined number of delay stages is
It is equal to the number of delay stages required to convert serial data WSDB to parallel data WPDB.

The selector 10 receives the mode switching signal MODE
In normal mode (MODE = “L”),
The external input serial data WSDA is selected and supplied to the serial-parallel conversion circuit 1a. In the double speed mode (MODE = “H”), the delayed serial data DLYWSDB output from the parallel-serial conversion circuit 1b is selected.
Is supplied to the serial-parallel conversion circuit 1a.

With this configuration, in the normal mode, 40 12-bit serial input data W
The SDA is converted into 480-bit output data WPDA, output, and input to the write buffer 2a. Also,
Forty 12-bit serial input data WSDB are converted into 480-bit output data WPDB, output, and input to the write buffer 2b.

On the other hand, in the double speed mode, the clock WC
K becomes twice the frequency of the clock DCK, and the shift register 31 and the shift register 21 are cascade-connected. As a result, a shift register of 80 stages is formed by combining them. As a result, 80 serial input data WSDB of 12 bits are converted into output data WPDA and WPDB of 480 bits each and output.

As shown in FIG. 3, the write buffer 2a comprises a 480-bit register 12 that is loaded and held by a port reference signal WACTA, which is a control signal from the sequence generation circuit 9, and has a DRA.
It operates in synchronization with the operation clock DCK of M4. The register 12 includes four 120-bit registers 12 in the figure.
a, 12b, 12c, and 12d.
The data is held by 0 bits, output as 120-bit output data WDDA0 to WDDA3, and sent to the selector 3a.

The write buffer 2b is a write buffer 2
a, which is loaded by a port reference signal WACTB which is a control signal from the sequence generation circuit 9;
The hold control is performed, the operation is performed in synchronization with the operation clock DCK of the DRAM 4, and the four 120-bit output data W are output.
The data is output as DDB0 to WDDB3 and sent to the selector 3b.

The selector 3a selectively outputs the output data WDDA0 to WDDA3 of the write buffer 2a as the output data WDDA according to the write data selection signal WDSEL from the sequence generation circuit 9.

The selector 3b selectively outputs the output data WDDB0 to WDDB3 of the write buffer 2b as the output data WDDB according to the write data selection signal WDSEL from the sequence generation circuit 9.

The selector 3c converts the output data WDDA of the selector 3a and the output data WDDB of the selector 3b into a write data selection signal WP from the sequence generation circuit 9.
The data is selectively output as 120-bit output data WDD according to the SEL and sent to the DRAM 4.

DRAM 4 receives a RAS (row address strobe) control signal NRA from DRAM controller 8.
S, CAS (column address strobe) control signal NC
Write and read operations are performed in accordance with AS, a column address CAD specifying a memory address, a row address RAD, and a WE (write enable) control signal NWE indicating a write / read permission state.

As shown in FIG. 4, the read buffer 5a receives the output data RDD of the DRAM 4 as an input, and outputs read data select signals RDSELA0, RDSELA1, R
DSELA2, RDSELA3 (In FIG. 1, RDSELA
A), registers 13a, 13b, 13c, and 13d are loaded and held at different timings every 120 bits.
Each of the registers 13a, 13b, 13c, and 13d is 1
It outputs 20-bit data RPDA0 to RPDA3. Further, these data RPDA0 to RPDA3 are collected as 480-bit data RPDA and input to the parallel-serial conversion circuit 6a.

The read buffer 5b is a read buffer 5
In the same configuration as in FIG. 4A, the output data RDD of the DRAM 4 is input, and the load and the hold are controlled at different timings every 120 bits by the selection signal RDSELB.
It outputs 0-bit data RPDB and sends it to the parallel-serial conversion circuit 6b.

The parallel-to-serial conversion circuit 6a has the configuration shown in FIG.
As shown in FIG. 7, a delay circuit 14 for delaying a port reference signal RACTA which is an output signal from the sequence generation circuit 9 for a predetermined time, and an output signal RACTA 'of the delay circuit 14
A shift register 16 and a selector 15 that selectively controls the output of the preceding stage register or the output of the read buffer 5a, and operates according to the clock DCK of the DRAM 4. With this configuration, the 480-bit data RPDA is converted into 40 12-bit data RSDPA and sent to the delay adjustment circuit 7a.

The parallel-serial conversion circuit 6b has the same structure as the parallel-serial conversion circuit 6a, and outputs 480-bit data RPDB in accordance with the port reference signal RACTB output from the sequence generation circuit 9.
The data is converted to zero 12-bit data RSDPB and sent to the delay adjustment circuit 7b.

As shown in FIG. 6, the delay adjustment circuit 7a
Output data RSDP of the parallel-serial conversion circuit 6a
Dual port RA that outputs A with a desired time delay
M16 (for example, SRAM) and its write address WA
DR and an address generation circuit 17 for generating a read address RADR. By shifting the write timing and read timing of the same address, the input data RSDPA is output as data RSDA with a predetermined delay.
As a result, the output timing of the serial data matches the external read request timing.

The delay time (the number of clocks) in this case can be arbitrarily set by the delay setting value RDLYA added to the address generation circuit 17. In this case, the dual port RA
In M16, the write operation follows the clock DCK, and the read operation follows the clock RCK.

The delay adjustment circuit 7b has the same configuration as the delay adjustment circuit 7a, and delays the output data RSDPB of the parallel-serial conversion circuit 6b by a desired time according to the delay set value RDLYB and outputs the result as data RSDB.

The sequence generating circuit 9 outputs various signals WACTA, WACTB, WDSEL, WPSEL, R in accordance with the external reset signal RSTR and clocks WCK, DCK.
DSELA, RDSELB, RACTA, RACTB,
RDLYA, RDLYB, and PSEQ are output.

The DRAM controller 8 receives the external signal WS
TRBA, WSTRBB, RSTRBA, RSTRB
B, block address WADRA, WADRB, RAD
RAS control signal NRAS, CAS control signal NCAS, column address CAD, row address RAD, WE control signal NWE are output in accordance with RA, RADRB, sequence signal PSEQ of sequence generation circuit 9 and clock DCK.

The external signals WSTRBA, WS
TRBB corresponds to an external write request timing. The external signals RSTRBA and RSTRBB correspond to external read request timings. That is, the timing at which the external signals WSTRBA and WSTRBB become active corresponds to the write request timing from outside, and the external signals RSTRBA and RSTRBB
Becomes active corresponds to the read request timing from the outside.

Next, the operation of writing data of the input system to the DRAM 4 in the normal mode will be described with reference to FIGS.

FIG. 7 shows a serial-parallel conversion circuit 1.
4 is a timing chart showing a timing relationship between input and output signals in a and 1b. The clock WCK at this time
Is the same frequency as the clock DCK.

Clock WCK is applied to WA port and WB port.
, WSDA (WA1, WA2,...), WS
DB (WB1, WB2,...) Are serial-parallel converters 1a and 1b, as shown in FIG. 7, which are external signals WSTRBA, 40 having a period of 40 data synchronized with the timing of valid data. At each timing of WSTRBB, the data is converted into parallel data WPDA and WPDB in 40 data units (480 bit units). Note that the symbol X in the figure indicates an arbitrary numerical value.

FIG. 8 shows a DRAM basic cycle signal CYCLE generated by the sequence generation circuit 9 based on the external reset signal RSTR, and a sequence signal PSEQ in which the order and timing of accessing the memory of each port are fixed.
And port reference signals WACTA, WACTB, RACTA, RA indicating start timing of an allocation period for each port in the cycle of DRAM basic cycle signal CYCLE.
6 is a timing chart showing a relationship with CTB. FIG.
Also shows a clock DCK.

As shown in FIG. 8, the sequence generation circuit 9
Then, based on the external reset signal RSTR, a period of 40T (T is a period of the DRAM clock DCK; = 40DCK =
(40WCK) DRAM basic cycle signal CYCLE is generated, and a sequence signal PSEQ which defines a dedicated access period of the WA port, WB port, RA port, and RB port is generated at intervals of 6T in this cycle.

In FIG. 8, when PSEQ = 1, it is a dedicated access period for the WA port, when PSEQ = 2, it is a dedicated access period for the WB port, and when PSEQ = 3, it is R
An example is shown in which it is a dedicated access period for the A port and a dedicated access period for the RB port when PSEQ = 4.

Also, the port reference signals WACTA, WAC
TB, RACTA, and RACTB are generated in synchronization with the sequence signal PSEQ as shown in FIG.

The data WPDA and WPDB parallelized by the serial-parallel conversion circuits 1a and 1b are temporarily stored in the write buffers 2a and 2b at the timing of the port reference signals WACTA and WACTB described above. At this time, the data WPDA and WPDB are each divided into four in units of 120 bits and temporarily stored.

FIG. 9 shows the operation of the write buffers 2a and 2b and the state in which the output signals of the selectors 3a, 3b and 3c are switched based on the write data selection signals WDSEL and WPSEL generated by the sequence generation circuit 9. It is a timing chart. X in the figure indicates an arbitrary numerical value.

Sequence signal P of sequence generation circuit 9
The output data WPDA of the serial-parallel conversion circuit 1a is loaded and held in response to the port reference signal WACTA generated at the first timing of the period in which SEQ is 1, and the data WDDA0-W held thereby are held.
DDA 3 is output from write buffer 2a. Also,
The port reference signal WA generated at the first timing of the period when the sequence signal PSEQ of the sequence generation circuit 9 is 2.
The output data WPDB of the serial-parallel conversion circuit 1b is loaded and held corresponding to the CTB, and the held data WDDB0 to WDDB3 are output from the write buffer 2b.

When WDSEL = 0, the selector 3
WDDA0 and WDDB0 are respectively selected by a and 3b, and are output as data WDDA and WDDB. Also, WD
When SEL = 1, the selectors 3a, 3b use WDDA1, W
DDB1 is selected and output as data WDDA and WDDB. When WDSEL = 2, WDDA2 and WDDB2 are selected by selectors 3a and 3b, respectively.
The data is output as data WDDA and WDDB. Also, W
When DSEL = 3, the selectors 3a, 3b use WDDA3,
WDDB3 are selected, and data WDDA and WDD are selected.
Output as B.

When WPSEL = 0 (low level), the data on the WA port side (output data WDDA of the selector 3a) is selected by the selector 3c and output as the data WDD. When WPSEL = 1 (high level), W
B port side data (output data WDD of selector 3b)
B) is selected and output as data WDD.

As described above, one of the divided data
The data is selected by the selectors 3a, 3b, 3c and the DRA
M4 and output by the DRAM controller 8 to the DR
A write operation to a predetermined address of AM4 is performed.

Next, the operation of writing data of the input system to the DRAM 4 in the double speed mode will be described with reference to FIGS.

FIG. 10 shows a serial-parallel conversion circuit 1.
4 is a timing chart showing a timing relationship between input and output signals in a and 1b. The clock WCK at this time
Is twice the frequency of the clock DCK.

The WB port receives 12 clocks according to the clock WCK.
Bit time series data WSDB (WB1, WB2,...
...) Are input, the serial-parallel conversion circuit 1b delays by 40 WCK as shown in FIG. 10, and outputs delayed serial data DLYWSDB.
This is input as time-series data WSD2A via the selector 10 according to the clock WCK. At this time, W
In the P port, the subsequent 12-bit time series data WSDB (WB41, WB42,...)
Is entered. And these time series data WSDB
(WB1, WB2,..., WB41, WB42,
...) Is an external signal WSTRB2 having a cycle of 80 data synchronized with the timing of valid data.
A, 40 data units at each timing of WSTRBB (4
Parallel data WPDA, WPDB in units of 80 bits)
Is converted to Note that the symbol X in the figure indicates an arbitrary numerical value.

FIG. 11 shows a DRAM basic cycle signal CYCLE generated by the sequence generating circuit 9 on the basis of the external reset signal RSTR, and a sequence signal PSE in which the order and timing of accessing the memory of each port are fixed.
6 is a timing chart showing a relationship between Q and port reference signals WACTA and WACTB indicating start timing of an allocation period for each port within a cycle of a DRAM basic cycle signal CYCLE. FIG. 11 shows the operations of the write buffers 2a and 2b and the write data selection signals WDSEL and W generated by the sequence generation circuit 9.
The state where each output signal of the selectors 3a, 3b, 3c is switched based on the PSEL is also shown. FIG. 11 also shows clocks WCK and DCK.
X in the figure indicates an arbitrary numerical value.

As shown in FIG. 11, in the sequence generation circuit 9, 40 DC
A DRAM basic cycle signal CYCLE of K cycles (= 80 WCK cycles) is generated, and a sequence signal PSEQ that defines a dedicated access period of the WA port, WB port, RA port, and RB port is generated at intervals of 6 DCKs in this cycle.

In FIG. 11, when PSEQ = 1, it is a dedicated access period of the WA port, and when PSEQ = 2, WB
An example is shown in which a dedicated access period of a port is set, a PSEQ = 3 indicates a dedicated access period of an RA port, and a PSEQ = 4 indicates a dedicated access period of an RB port.

Also, the port reference signals WACTA, WAC
TB is generated in synchronization with the sequence signal PSEQ as shown in FIG. Port reference signal RACT
Although not shown, A and RACTB are also synchronized with the sequence signal PSEQ.

The data WPDA and WPDB parallelized by the serial-parallel conversion circuits 1a and 1b are temporarily stored in the write buffers 2a and 2b at the timings of the port reference signals WACTA and WACTB described above. At this time, the data WPDA and WPDB are each divided into four in units of 120 bits and temporarily stored.

More specifically, the output data WPDA of the serial-parallel conversion circuit 1a corresponds to the port reference signal WACTA generated at the first timing of the period when the sequence signal PSEQ of the sequence generation circuit 9 is 1.
(WB40-1) are loaded and held in the write buffer 2a, and the data WDDA held thereby is held.
0 to WDDA3 are output from the write buffer 2a.
Also, the sequence signal PSEQ of the sequence generation circuit 9
Corresponds to the port reference signal WACTB generated at the first timing of the period of 2.
b is loaded and held by the write buffer 2b, and the held data WDDB0 to WDDB3 are output from the write buffer 2b.

When WDSEL = 0, the selector 3
WDDA0 and WDDB0 are respectively selected by a and 3b, and are output as data WDDA and WDDB. Also, WD
When SEL = 1, the selectors 3a, 3b use WDDA1, W
DDB1 is selected and output as data WDDA and WDDB. When WDSEL = 2, WDDA2 and WDDB2 are selected by selectors 3a and 3b, respectively.
The data is output as data WDDA and WDDB. Also, W
When DSEL = 3, the selectors 3a, 3b use WDDA3,
WDDB3 are selected, and data WDDA and WDD are selected.
Output as B.

When WPSEL = 0 (low level), data on the WA port side (output data WDDA of the selector 3a) is selected by the selector 3c and output as data WDD. When WPSEL = 1 (high level), W
B port side data (output data WDD of selector 3b)
B) is selected and output as data WDD.

As described above, one of the divided data
The data is selected by the selectors 3a, 3b, 3c and the DRA
M4 and output by the DRAM controller 8 to the DR
A write operation to a predetermined address of AM4 is performed.

Next, the data read from the DRAM 4 by the DRAM controller 8 is transferred to the RA port, RB
The operation until output from the port will be described with reference to FIG.

FIG. 12 shows the read data selection signals RDSELA0 to RDSEA generated by the sequence generation circuit 9.
LA3, RDSELB0 to RDSELB3, and parallel output data RPDA (RPDA0 to RPDA3), RPDB of read buffers 5a, 5b controlled by the signals.
6 is a timing chart showing a relationship with (RPDB0 to RPDB3), where RPDA0 to RPDA3 in the figure are:
Registers 13a and 13 of read buffer 5a shown in FIG.
b, 13c, and 13d, each of which is a 120-bit data output. RPDB0 to RPDB3 are register outputs (not shown) inside the read buffer 5b having the same configuration. FIG. 12 also shows the sequence signal PSEQ and the port reference signals RACTA and RACTB.

As shown in FIG. 12, data RDD read from the DRAM 4 by the DRAM controller 8 in units of 120 bits is read by the read buffers 5a and 5b.
Read data selection signals RDSELA0 to RDSELA3, RDS which are control signals from the sequence generation circuit 9.
The read buffer 5a is provided by ESB0 to RDESB3.
5b is temporarily stored in each of the registers constituting the data RPDA (RPDA) from the read buffers 5a and 5b.
0 to RPDA3), RPDB (RPDB0 to RPDB)
Output as 3).

In the parallel-serial conversion circuits 6a and 6b, the output data RPDA of the read buffers 5a and 5b,
RPDB is converted into serial data by a constant delayed signal RACTA ', RACTB' (not shown) of port reference signals RACTA, RACTB output from sequence generating circuit 9 shown in FIG.
Output as PA and RSDPB. The reason why the constant delay is given here is to perform serial conversion after all the 480-bit data in the registers of the read buffers 5a and 5b are updated.

For this purpose, the port reference signals RACTA and RACTB are converted so that parallel-to-serial conversion is performed within a period from the time when the data read out by dividing into four is temporarily stored in the register to the next update. What is necessary is just to delay. For example, with a 6T delay (T is the cycle of the clock DCK), the signals RACTA 'and RACTB' are all divided into four parts at each port by the read buffer 5.
If the signal is generated immediately after the temporary storage in a and 5b, the data can be output from the read port earlier and the delay circuit can be made smaller than in the case of 7T or more.

Serialized data RSDPA, RS
The DPB is delay-adjusted by delay adjustment circuits 7a and 7b at the subsequent stage, and data RSDA and R are supplied to two output ports respectively.
Output as SDB. The delay adjustment amount here is the delay set value RDLY output from the sequence generation circuit 9.
A, RDLYB.

FIG. 13 shows a delay setting value RD which is a signal output from the sequence generation circuit 9 for the RA port.
LYA (= d: integer) and the delay adjustment circuit 7 shown in FIG.
5A is a timing chart showing the relationship between a write address WADR and a read address RADR generated by an address generation circuit 17 in FIG. FIG. 13 shows the sequence signal, port reference signal RACTA and its delay signal RACT described above.
A ′, input data RPDA to the parallel-serial conversion circuit 6a, and a clock RCK are also shown.

As shown in FIG. 13, address generation circuit 1
In No. 7, the write address WADR and the read address RADR are different from each other by the value d in conjunction with the delay setting value RDLYA, whereby the read timing can be shifted. Also, the serial data RSDA and RSDB can be output by synchronizing the clock on the read side of the dual port RAM 16 with the clock RCK having a free phase relationship with the DRAM operation clock DCK. In this case, by setting RDLYA to a value d, the read timing d clock (RC
K) Can be delayed by minutes.

Here, a cyclic operation is performed so that each of the write address WADR and the read address RADR returns to the zero address when it reaches the maximum address value. Here, the word length of the dual port RAM 16 is D
RAM operation clock DCK and read clock RCK
Are the same frequency, if there is a word number (40 words in this example) corresponding to the cycle of RACTA 'and RACTB', it is possible to adjust to an arbitrary read timing within the cycle.

Here, as shown in FIG. 8, the DRAM basic cycle signal CY is generated by the external reset signal RSTR.
Since the phase of CLE is determined and the memory access timing of each read port is determined by this, the read timing is determined by the phase of the external reset signal RSTR and the phase of the external reset signal RSTR.
Sequence generation circuit 9 for delay adjustment circuits 7a and 7b
RLDYA and RDLYB are adjusted so as to coincide with external read request timings. These delay setting values RDLYA, RDLY
B may be set, for example, by writing a register from a microcomputer.

Here, the read start timing of the valid data from the external reset signal RSTR is fixed by shifting the memory access timing of each port by 6T even if the delay setting values RDLYA and RDLYB are the same. It is output 6T earlier than the RB port. On the other hand, the delay amount of the delay circuit 14 of the parallel-serial conversion circuit 6a is set to be 6T larger than the delay amount of a similar delay circuit (not shown) for the RB port, or Set value RDLYA and delay set value R
Even if the value of DLYB is the same, the write address WADR and the read address RADR in the delay adjustment circuits 7a and 7b
The address generation circuit 17 in FIG. 6 is configured such that the difference between the two is shifted by 6 between the ports, and the delay adjustment circuit 7a for the RA port has a larger difference by 6 by delay adjustment. The correction can be made by the circuit 7a, the deviation between the read timings between the ports can be eliminated, and the read request timing from the outside and the delay set value of each port can be uniformly handled, thereby facilitating the timing control.

Next, referring to FIGS. 14 to 18, in the normal mode and the double speed mode, the data and address of each port are selected at the timing specified by the sequence generation circuit 9, and the DRAM 4 is controlled. The operation of the DRAM controller 8 will be described.

The DRAM 4 operates in accordance with the clock DCK,
RAS control signal NRAS and CAS control signal NCAS required for DRAM control output from RAM controller 8
And WE control signal N indicating write / read permission state
A write operation and a read operation are performed by WE and a row address RAD and a column address CAD that specify a memory address.

FIG. 14 shows an external reset signal RSTR and a DRAM basic cycle signal CYC in the normal mode.
LE, a clock DCK, a sequence signal PSEQ generated by the sequence generation circuit 9, and a RAS generated by the DRAM controller 8 for controlling the DRAM 4.
5 is a chart showing timing relationships among a control signal NRAS, a CAS control signal NCAS, a WE control signal NWE, a row address RAD, and a column address CAD.

FIG. 15 shows an external reset signal RSTR and a DRAM basic cycle signal CYC in the double speed mode.
LE, a clock DCK, a sequence signal PSEQ generated by the sequence generation circuit 9, and a RAS generated by the DRAM controller 8 for controlling the DRAM 4.
5 is a chart showing timing relationships among a control signal NRAS, a CAS control signal NCAS, a WE control signal NWE, a row address RAD, and a column address CAD.

In this case, for one row address setting, a page mode operation in which four consecutive column addresses can be written and read is performed. This DRA
M4 is the precharge period 1T and the row address setting period 1
Assuming that T is required, writing and reading of data of 480 pixels are realized with a total of 6T per port, together with 4T during the column address setting period.

FIG. 16 is a diagram schematically showing a memory map of the DRAM 4 when the maximum page length is 16 (16 columns).

FIG. 17 shows a case where the block address WADRA given to the conventional VRAM is externally input to the DRAM 4 shown in FIG.
Row address WR for WA port inside controller 8
A is a block diagram illustrating a configuration example of a circuit that generates a column address WCA, that is, a circuit that performs bit division of an address. In FIG. 17, reference numeral 81 denotes an input of an externally input block address WADRA, a block address WADRA 'latched by a port reference signal WAACTA serving as a reference for access start of a WA port, and a 2-bit downshift of the block address WADRA'. 2
It is a bit down circuit. 82 is a block address WA
This is a lower 2 bit extracting circuit for extracting lower 2 bits of DRA '. Reference numeral 83 denotes a 2-bit up circuit that performs a 2-bit up-shift of the output data of the lower 2-bit extraction circuit 82. A 4-bit counter 84 counts the clock DCK with the output data of the 2-bit up circuit 83 as an initial value.

FIG. 18 shows an example of the relationship between the row address WRA, column address WCA and the specific value of the externally input block address WADRA. FIG. 18 also shows the DRAM basic cycle signal CYCLE, the sequence signal PSEQ, and the external signal WSTRBA.

As shown in FIG. 18, the externally input block address WADRA is latched by a port reference signal WAACTA serving as a reference for the access start of the WA port and becomes WADRA '. The latched block address WADRA' is With such a circuit configuration,
It is converted into a row address WRA and a column address WCA.

Similarly, the WB port, RA port, and RB
Block addresses for ports WADRB, RADRA,
From RADRB, row addresses WRB, RRA, RRB and column addresses WCB, RCA, RCB are generated. These row addresses and column addresses are shown in FIG. 14 or FIG.
As shown, the DRAM basic cycle signal CYCLE
Are selected as the row address RAD and the column address RCD of the DRAM 4 at the timing determined within the cycle of
4 is output.

Here, the row address WRA and the column address W
As shown in FIG. 17, the circuit for generating the CA can be realized with a simple configuration including only the 2-bit down circuit 81, the lower 2-bit extraction circuit 82, the 2-bit up circuit 83 and the 4-bit counter 84. This is because the maximum page length of the memory is 16 (2 to the power of C, C is 2 to the power of 2) and the page length P to be used is 4 (2 to the power of 2), so that the block address is 0, 1, In the case of 2, 3, 4, 5,..., The row address WRA is 0, 0, 0, 0, 1, 1,.
The start address of the column address WCA of each port in the cycle of the basic cycle signal CYCLE is 0, 4, 8, 1
2, 0, 4,... That is, the row address WRA is a quotient obtained by dividing the block address by C, DR
The start address of the column address WCA of each port in the cycle of the AM basic cycle signal CYCLE is obtained by multiplying the remainder obtained by dividing the block address by C by P. The DRAM is set so that the values of C and P become a power of two. This is because the basic cycle is determined.

The above can be generalized as follows. That is, it is assumed that the memory has a row address and a column address, and performs a page operation in which a continuous column address can be written to and read from the row address, and one in a control sequence (one cycle of CYCLE). Assuming that the page length for the port to access the memory is P, the bit width of the serial data is S bits, the maximum page length of the memory is 2 C, and the access data width of the memory is A bits, the cycle W The clock has a relation of W = (A / S) × P with respect to the bit width S bits of serial data, the access data width A bits of the memory, and the page length P, and the values of C and P are powers of two. Thus, the sequence generating means and the memory are configured.

In the embodiment, A = 120 bits, S =
12 bits, P = 4 (= 2 ² ), and C = 16 (= 2 ⁴ ).

With the above configuration and operation, it is possible to realize a multiport memory device having a 4-port input / output system without arbitration means between the ports.

At least one of the plurality of serial-parallel conversion circuits 1a and 1b converts delayed serial data DLYWSDB obtained by time-shifting serial data WSDB by a predetermined number of delay stages into parallel data WPDB.
A selector 10 is provided at at least one of the serial data input terminals of the plurality of serial-parallel conversion circuits 1a and 1b to output the serial data WSDA of the external input and another serial-parallel conversion circuit 1b. One of the delayed serial data DLYWSDB is selected and output. When the externally input serial data WSDA is at a normal double speed, the delayed serial data output from the other serial-parallel conversion circuit 1b is selected by the selector 10. Is selected, it is possible to operate in the double-speed write mode in which the DRAM 4 stores the serial data of the external input using the access period for two ports in one cycle of the control sequence.

At this time, the serial data WS in the double speed mode
When writing the DB to the DRAM 4, the write buffer 2
For the circuits a and 2b and thereafter, particularly the DRAM 4, both the write clock and the read clock can use a normal-speed clock, and the power consumption does not increase even when writing double-speed input serial data to the memory. .

Also, in the case of double-speed writing, since writing is performed using a normal-speed clock, the write clock of the DRAM 4 is set to 2 times.
Unlike doubling, data stored in the memory can be guaranteed. In addition, both normal-speed serial data and double-speed serial data can be written to one memory.When both normal-speed serial data and double-speed serial data need to be processed, the Only one multi-port memory device that operates with a clock is required, and even if the input speed of serial data differs depending on the operation mode in an imaging device,
Image processing can be performed with only one multiport memory device, and the configuration of the imaging device can be simplified, miniaturized,
The price can be reduced.

When writing and processing image data having a large number of pixels such as still images in the double speed mode, the DRAM 4
Can be operated at the normal speed, and a still image can be easily displayed on the monitor screen by using the display means for displaying a moving image as it is.

In this embodiment, the delay adjustment circuit 7
Although a dual port RAM was used as a and 7b, DR
If the phase of the AM operation clock DCK and the phase of the read clock RCK are specified and have the same frequency, the same effect can be obtained by delay adjustment using a FIFO-RAM or a shift register and a selector configuration of each register output. It is possible.

The serial-parallel conversion circuit 1a,
1b, the write buffers 2a and 2b, and the read buffers 5a and 5b are configured as load-hold type D flip-flops in the present embodiment as a detailed configuration example. However, the present invention is not limited to this, and may have equivalent functions. Other configurations may be used.

In the present embodiment, the access timing of each port is fixed in the order of WA, WB, RA, and RB in the DRAM basic cycle. However, the order is not limited to this order, and may be arbitrarily determined. May do it. For example, R
If the access timing of the output system such as A, RB, WA, WB is fixed before the input system, the difference between the external reset signal RSTR and the access timing to the memory of the read port becomes small, and the delay amount of the read timing is reduced. (Latency) can be reduced.

In this embodiment, a DRAM having an access data width of 120 bits and a maximum page length of 16 of the DRAM 4 is used as a memory.
For example, if a DRAM having an access data width of 240 bits wider than 120 bits is used, the write buffer 2
a, 2b and the number of data divisions and selectors 3a,
Only two systems are required for input to 3b, and the selector control signal can be reduced accordingly. Also, if a DRAM having an access data width of 480 bits is used,
The selectors 3a and 3b can be omitted.

In this embodiment, two input ports,
Although two output ports are used, the present invention is not limited to this. For example, one input port and three output ports may be used. In this case, only one serial-parallel conversion circuit, write buffer, and selector for the input system may be used. Selector 3c
Is not required. Further, the read buffer, the parallel-serial conversion circuit, and the delay adjustment circuit for the output system may be increased to three systems. In the sequence generation circuit, for example, the operation of each block may be controlled by a fixed control sequence as shown in FIG. If the number of input / output ports is the same, the number of serial-parallel conversion stages does not need to be changed. In FIG. 19, a clock DCK, an external reset signal RSTR, a DRAM basic cycle signal CYCLE,
Sequence signal PSEQ and port reference signal RACT
A, RACTB, RACTC, and WACTA are shown. The number of input ports is not limited to one and two, but may be three or more. The number of output ports is not limited to two or three, but may be one or four or more.

The total number of input / output ports is not limited to four, but the required number of ports N and the specifications of the memory to be used (access data bit width A, maximum page length = 2 C-th bit, C is a power of 2) and the bit width S of the serial data of the port.
The period W of the M basic sequence is determined.

Here, the period W of the DRAM basic sequence
Is a range in which the number of input systems of the selector is determined to be a power of 2, and the condition of W ≧ n × N (where n is the number of clocks of a memory access period per port in one cycle) is satisfied. If the minimum value is determined, there will be no fraction when calculating the memory address, so that the row address generation circuit and column address generation circuit of the DRAM controller can be realized with a simple configuration by bit shifting as described above. In addition, it is possible to obtain a multi-port memory device having an optimum configuration in which an unnecessary increase in circuit size is suppressed.

Note that there is only one input port and S ×
If W = A, the selectors 3a, 3b, 3 of the present embodiment
It is needless to say that neither c is necessary, and the parallel data output from the serial-parallel conversion circuit is directly selected as write data to the DRAM.

In this embodiment, a single-port DRAM is used as a memory. However, the present invention is not limited to this, and any semiconductor memory having a row address and a column address may be used.

[Second Embodiment] Next, an embodiment corresponding to the third aspect of the present invention will be described. FIG. 20 is a block diagram illustrating an imaging apparatus according to an embodiment of the present invention. CCD 101-1-
Reference numeral 101-3 denotes an interlace (interlaced scan) CCD for R, G, and B, respectively. In the following, for simplification of description, it is assumed that the CCD does not mix vertical pixels.

FIG. 21 shows the spatial positional relationship between the pixels of the CCDs 1-1 to 1-3. The pixels G11, G12,. . .
Are pixels R11, R12,. . . And B11, B12,. . . Is shifted by 1/2 pixel in the horizontal and vertical directions in the lower right direction.

The RGB signals having the spatial positional relationship shown in FIG. 21 are output from the CCD every other pixel in the vertical direction. Taking the pixel of the G signal as an example, the vertical direction in the odd field is G11, G31,. . . , The vertical direction in the even field is G21, G41,. . . Are output in this order. R
The same applies to the signal and the B signal. That is, since all pixel data of the CCD cannot be output in one field period, it is necessary to output data over two field periods.

Therefore, these RGB signals are output from the CCDs 101-1 to 101-3 over a two-field period, and are processed by the analog processing unit 102 and the A / D converters 103-1 to 103-1.
At 103-3, analog processing and conversion into digital signals are performed, respectively, and input to the write port of the memory means 108. As a result, data for all RGB pixels is accumulated in the memory means 108.

From the read port of the memory means 108,
RGB signals are output so as to reproduce the spatial position on the CCD. Taking a G signal pixel as an example, the vertical direction is G1
1, G21, G31,. . . Are output in this order. The same applies to the R signal and the B signal. The output of the memory means 108 is output to the matrix circuit 104 which is a luminance signal creating means.
Is input to

In the matrix circuit 104, the RGB signals are converted into two Y signals and one C signal.
The operation of the matrix circuit 104 is described below.

As shown in FIG. 22, an RGB pixel signal from the memory means 8 is input to the Y1 matrix circuit 115 at a sampling frequency fs, and a G signal pixel G2
1, G22,. . . And R and B signal pixels R21,
R22,. . . And B21, B22,. . . , The pixels Y21, Y22,. . . And outputs it as a Y1 signal at a sampling frequency of 2 fs.

[0124]

(Equation 1)

Similarly, the RGB pixel signal from the memory means 108 is input to the Y2 matrix circuit 116 at the sampling frequency fs, and the G signal pixels G11, G1
2,. . . And pixels R21 and R2 of R and B signals
2,. . . And B21, B22,. . . , The pixels Y11, Y12,. . . And outputs it as a Y2 signal at a sampling frequency of 2 fs.

[0126]

(Equation 2)

The spatial positions of Y1 and Y2 are indicated by ● in FIG. By obtaining the pixel of the Y signal as described above,
A Y signal having twice as many pixels as G can be obtained in the horizontal direction, and a Y signal having twice as many pixels as G in the vertical direction can be obtained by combining the Y1 and Y2 signals. For example, if the RGB pixel signals are 768 horizontal pixels and 480 vertical pixels, the Y1 and Y2 signals are both 1536 horizontal pixels,
480 pixels vertically, and when Y1 and Y2 are combined, 15 pixels
It becomes a Y signal of 36 pixels and 960 vertical pixels. At this time,
If fs = 15.75 MHz, 2fs = 31.5M
Hz.

Further, as for the C signal, only one system is obtained as shown in Expression 3. From human visual characteristics, the C signal does not require a very high band, so one system is sufficient. The spatial position of C is the same as that of G, but is not shown for simplification of FIG.

[0129]

(Equation 3)

FIG. 22 shows the internal configuration of the matrix circuit 104.
It will be described according to. The input R and B signals are respectively 1H line memory 111 (H: horizontal scanning period),
112 and the C matrix circuit 117. 1
Outputs of the H line memories 111 and 112 are input to a matrix circuit 115 for Y1 and a matrix circuit 116 for Y2.

On the other hand, the input G signal is input to the 1H line memory 113, and the output of the 1H line memory 113 is output to the Y1 matrix circuit 115 and the C matrix circuit 1.
17 and 1H are input to the line memory 114. 1H
The output of the line memory 114 is the Y2 matrix circuit 11
6 is input.

With this configuration, the Y1 matrix circuit 115 has R21, R22,. . . , G2
1, G22,. . . , B21, B22,. . . But Y2
R21, R22,. . . ,
G11, G12,. . . , B21, B22,. . . But,
The C matrix circuit 117 has R21, R2
2,. . . , R31, R32,. . . , G21, G2
2,. . . , B21, B22,. . . , B31, B3
2,. . . Are respectively input.

The output of the matrix circuit 104 is input to the horizontal zoom circuit 105 and is converted to a square pixel. here,
The square pixel conversion will be described. In general, CCDs for digital still cameras have the same horizontal and vertical pixel spacing (square pixel array), but CCDs for video cameras have different spacings and output them as they are to the screen of a personal computer. As a result, an image that extends vertically or horizontally is obtained. Therefore, zoom processing is performed electronically in the horizontal direction, and the pixel intervals in the horizontal and vertical directions of the Y and C signals are made uniform. : 3 is required. When a Y signal of 1536 horizontal pixels and 960 vertical pixels is considered, square pixel data of 1280 horizontal pixels and 960 vertical pixels can be obtained by performing a horizontal zoom of about 0.83 times in the horizontal direction.

The output of the horizontal zoom circuit 105 is input to the write port of the memory means 108 via the selector 106. As described above, the RGB data is read from the read port of the memory means 108 at the sampling frequency fs, and the Y1, Y2, and C data from the matrix circuit 104 are input to the write port at the sampling frequency 2fs. Now, the driving frequency of the memory means 108 is f
If it is s, in order to write data at a sampling frequency of 2 fs input from the write port, it is necessary for the memory means 108 to write at twice the driving frequency.

Here, by using the multiport memory device (for example, three-port write, three-port read) described in the first embodiment as the memory means 108, data can be written at twice the driving frequency. Will be possible. As a result, Y and C signals after square pixel conversion, that is, Y1, Y2, and C signals of 1280 horizontal pixels and 480 vertical pixels are obtained in the memory unit 108.

Y from the read port of the memory means 108
The signal output starts from the spatially upper Y2 signal, and thereafter, the Y1 signal and the Y2 signal are alternately output to output the Y signal for 960 vertical pixels. The C signal output from the memory means 108 is input to the interlace correction circuit 107.

The interlace correction circuit 107 interpolates the vertical 480 pixel C signal in the vertical direction and outputs the vertical 960 pixel C signal. Interlace correction circuit 1
FIG. 24 shows the internal configuration of the module 06. The input C signal is 1
H line memory 121, adder 122, selector 124
Is input to The C signal delayed by 1H in the 1H line memory 121 is added to the input C signal in the adder 122, and after a １ ／ gain is applied in the divider 123,
The data is input to the selector 124. The selector 124 is 1H
One of the input C signal and the output signal of the dividing means 123 is selected and output every period. Interlace correction circuit 10
The output of 7 is output as a camera output. As a result, the camera output is Y, C of 1280 horizontal pixels and 960 vertical pixels.
Signal.

With the above configuration, the RGB signals stored in the memory are read out at the sampling frequency fs, and the Y signal having the sampling frequency of 2 fs is read out by the matrix circuit.
1, Y2, and C signals, and a series of processes such as re-accumulation in the memory by a double-speed writing operation can be performed while the drive frequency of the memory is kept at fs, and the RGB signal accumulation memory and the Y1, Y2 , C signal storage memory can be shared by one memory. Further, it is possible to reduce the memory power consumption as compared with a method in which the memory drive frequency is set to 2 fs and the data read operation is performed every other clock.

[0139]

As described above, according to the multiport memory device of the present invention, the sequence generation means fixes the order of access timing of each port of the input / output system to the memory to the memory periodically, and The write data is temporarily stored and held in a write buffer so as to be synchronized with the access timing, and the read data of the output system is read out at a fixed access timing and then delayed by a delay adjusting means so as to match the read request timing. In addition, the number of ports can be easily increased without the need for arbitration of memory access between ports as in the related art. Further, if this multi-port memory device is used, not only an image memory but also a large number of ports are provided, and a 1H memory (H) realized by a conventional FIFO memory or a dual-port SRAM using these ports is used. (Horizontal scanning period of a video signal) can also be realized, thereby obtaining an effect of, for example, reducing the circuit area.

Further, at least one of the plurality of serial-parallel conversion means outputs separately from the parallel data delayed serial data obtained by time-shifting the serial data by a predetermined number of delay stages. A serial data selection output means is provided at at least one serial data input terminal of the parallel conversion means, and selects and outputs one of serial data of an external input and delayed serial data output from another serial-parallel conversion means. The serial data selection output means selects the delayed serial data output from the other serial-parallel conversion means when the serial data of the external input is the normal double speed. Input to memory using the access period of 2 ports at It is possible to operate at double speed write mode for storing the serial data.

At this time, when writing the serial data in the double speed mode to the memory, a normal speed clock can be used for both the write clock and the read clock for the circuits after the write buffer, especially for the memory, and the serial input of the double speed input can be used. Even when data is written to the memory, power consumption does not increase.

Also, in the case of performing double-speed writing, since writing is performed using a normal-speed clock and there is no need to switch the memory writing clock, it is necessary to guarantee data stored in the memory. Can be.

Both normal speed serial data and double speed serial data can be written in one memory.
Even when it is necessary to process both normal-speed serial data and double-speed serial data, only one multi-port memory device that operates at a normal-speed clock is required. Even when the input speed of serial data is different, image processing can be performed with only one multiport memory device, so that the configuration of the imaging device can be simplified, and miniaturization and cost reduction can be realized.

When writing and processing image data having a large number of pixels such as still images in the double speed mode, the memory read side can be operated at the normal speed.
The still image can be easily displayed on the monitor screen by using the display means for displaying the moving image as it is.

According to the imaging apparatus of the present invention, as described above, two ports of write in a multiport memory device can be handled as one port, so that data at twice the memory access speed can be written. . Therefore, by using this multi-port memory device as an image pickup device, the drive frequency of the memory can be set to a normal value even in a mode requiring a double-speed writing operation (for example, a still image shooting mode using a CCD shifted in pixels). It can be executed while keeping the state, and the memory for storing two different systems of signals (the memory for storing RGB signals and the memory for storing Y1, Y2, and C signals) can be shared by one memory. Further, it is possible to reduce the memory power consumption as compared with a method in which the memory drive frequency is set to 2 fs and the data read operation is performed every other clock.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a multiport memory device according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a specific configuration of a serial-parallel conversion circuit.

FIG. 3 is a block diagram showing a specific configuration of a write buffer.

FIG. 4 is a block diagram showing a specific configuration of a read buffer.

FIG. 5 is a block diagram showing a specific configuration of a parallel-serial conversion circuit.

FIG. 6 is a block diagram showing a specific configuration of a delay adjustment circuit.

FIG. 7 is a timing chart showing a timing relationship of input / output signals in a normal mode in the serial-parallel conversion circuit.

FIG. 8 is a timing chart showing signals of various control sequences generated by the sequence generation circuit in the case of two input ports and two output ports in the normal mode.

FIG. 9 is a timing chart showing signals of various control sequences generated by a sequence generation circuit and an operation state of a write buffer in a normal mode.

FIG. 10 is a timing chart showing a timing relationship of input / output signals in a double speed mode in the serial-parallel conversion circuit.

FIG. 11 shows signals of various control sequences generated by the sequence generation circuit in the case of 2 input ports and 2 output ports in the double speed mode, and also shows various control sequence signals generated by the sequence generation circuit and the operation state of the write buffer. It is a timing chart.

FIG. 12 is a timing chart showing signals of various control sequences generated by a sequence generation circuit and an operation state of a read buffer.

FIG. 13 is a timing chart showing signals of various control sequences generated by the sequence generation circuit and operation states of the delay adjustment circuit.

FIG. 14 is a timing chart showing signals of various control sequences generated by a sequence generation circuit in a normal mode and an operation state of a DRAM controller.

FIG. 15 is a timing chart showing signals of various control sequences generated by the sequence generation circuit in double speed mode and the operation state of the DRAM controller.

FIG. 16 is a schematic diagram showing a memory map of a DRAM.

FIG. 17 is a block diagram showing a circuit configuration for generating a row and column address inside the DRAM controller.

FIG. 18 is a timing chart illustrating specific values of row and column addresses and block addresses of external inputs.

FIG. 19 is a timing chart showing signals of various control sequences generated by the sequence generation circuit in the case of one input port and three output ports.

FIG. 20 is a block diagram illustrating a configuration of an imaging device according to a second embodiment of the present invention using a multiport memory device.

FIG. 21 is a schematic diagram illustrating a spatial positional relationship between pixels of a CCD in the imaging apparatus.

FIG. 22 is a block diagram showing a specific configuration of the matrix circuit of FIG.

FIG. 23 is a schematic diagram showing spatial positions of Y1 and Y2.

24 is a block diagram showing a specific configuration of the interlace correction circuit in FIG.

[Explanation of symbols]

 1a, 1b Serial-parallel conversion circuit 2a, 2b Write buffer 3a, 3b, 3c selector 4 DRAM 5a, 5b Read buffer 6a, 6b Parallel-serial conversion circuit 7a, 7b Delay adjustment circuit 8 DRAM controller 9 Sequence generation circuit 10 Selector

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme coat ゛ (Reference) G11C 11/401 H04N 9/09 A H04N 9/09 9/64 R 9/64 G11C 11/34 362G 371H ( 72) Inventor Takefumi Hamasaki 1006 Kazuma Kadoma, Kadoma City, Osaka Prefecture F-term in Matsushita Electric Industrial Co., Ltd. (reference) GG29 GG30 5C066 AA01 AA11 CA01 DD01 KE04 KE08 KE09 KE11 KE16 KE19 KF05 KG01 KM02

Claims (2)

[Claims] 1. A method for serial-parallel conversion of serial data every predetermined number of data to output parallel data, wherein at least one of the plurality of the serial data is a serial data obtained by time-shifting the serial data by a predetermined number of delay stages. A plurality of serial-parallel conversion means for outputting separately from the parallel data; and an externally-input serial data provided at at least one serial data input end of the plurality of serial-parallel conversion means and another serial-parallel conversion means. Serial data selection and output means for selecting and outputting any one of the delayed serial data output from the CPU, a write buffer for temporarily storing outputs of the plurality of serial-parallel conversion means, and a part of an output of the write buffer Write data selection output means for selecting and outputting A memory to which the output of the data selection output means is written; a read buffer for temporarily storing data read from the memory; and one or more parallel-serial converters for performing parallel-serial conversion on the output of the read buffer for each output system Conversion means; one or more delay adjustment means for delaying the output of the one or more parallel-serial conversion means; memory control means for performing writing / reading and address control of the memory; Data selection output means,
The read buffer includes a sequence generation unit that generates a control sequence for each operation of the memory control unit. The control sequence generated by the sequence generation unit has a predetermined cycle, and is included in one cycle of the control sequence. The access timing and access order to the memory for each input / output system are fixed, the serial-parallel conversion means performs serial-parallel conversion in synchronization with an external write request timing, and the write buffer The output of the serial-parallel conversion means is temporarily stored in synchronization with the phase of the control sequence output from the generation means, and the read buffer is read from the memory in synchronization with the phase of the control sequence output from the sequence generation means. Temporarily stored data, and adjusts the delay. The stage delays the output of the parallel-serial conversion means to match the external read request timing based on the difference between the external read request timing and the phase of the control sequence. The serial data of the external input is supplied to the other serial-parallel conversion means when the serial data of the external input is a normal double speed. The delay serial data output from the serial-parallel conversion means is selected, and 2 in one cycle of the control sequence is selected.
A multi-port memory device, wherein the multi-port memory device is operated in a double speed write mode in which the serial data of the external input is stored in the memory using an access period for a port. 2. When dedicated image sensors are used for R (red), G (green), and B (blue), and the pixel arrangement intervals in the horizontal and vertical directions of the image sensors are Ph and Pv, respectively. The G image pickup device is horizontally and vertically (Ph / 2 + a) and (Pv / 2 +) with respect to the R and B image pickup devices.
b) An image pickup device of a three-plate type which performs oblique pixel shift arrangement in which shift is performed by (a, b are constants), wherein the multi-port memory stores pixel output signals of the R, G, and B image sensors. A pixel output signal of the image sensor for R, G, B or an output signal of the multiport memory device, and a pixel output signal of the image sensor for R and B; The number of pixels in the horizontal direction is 2 of the G image sensor by using the pixel output signal of the G image sensor that is spatially located in the lower left nearest neighborhood or the lower right nearest neighborhood with respect to the pixel of the G image sensor. Create a first luminance signal that is twice
Using the pixel output signal of the image sensor for the, and the pixel output signal of the image sensor for the G located in the upper left nearest neighbor or the upper right nearest neighbor spatially for the pixels of the R and B image sensor, The multi-port memory device includes a luminance signal generation unit that generates a second luminance signal having a horizontal pixel number twice as large as that of the G image pickup device. A plurality of serial-parallel conversion means for converting and outputting parallel data, at least one of the plurality of serial-parallel conversion means for outputting separately from the parallel data delayed serial data obtained by time-shifting the serial data by a predetermined number of delay stages, At least one serial data input terminal of the plurality of serial-parallel conversion means is provided with externally input serial data and another serial-parallel data. Serial data selection and output means for selecting and outputting one of the delayed serial data output from the serial conversion means, a write buffer for temporarily storing outputs of the plurality of serial-parallel conversion means, and an output of the write buffer Write data selection and output means for selecting and outputting a part of the data; a memory to which the output of the write data selection and output means is written; a read buffer for temporarily storing data read from the memory; One or a plurality of parallel-serial conversion means for performing parallel-serial conversion of an output for each output system; one or a plurality of delay adjustment means for delaying the output of the one or a plurality of parallel-serial conversion means; Memory control means for performing read and address control; §, the write data selection output means,
The read buffer includes a sequence generation unit that generates a control sequence for each operation of the memory control unit. The control sequence generated by the sequence generation unit has a predetermined cycle, and is included in one cycle of the control sequence. The access timing and access order to the memory for each input / output system are fixed, the serial-parallel conversion means performs serial-parallel conversion in synchronization with an external write request timing, and the write buffer The output of the serial-parallel conversion means is temporarily stored in synchronization with the phase of the control sequence output from the generation means, and the read buffer is read from the memory in synchronization with the phase of the control sequence output from the sequence generation means. Temporarily stored data, and adjusts the delay. The stage delays the output of the parallel-serial conversion means to match the external read request timing based on the difference between the external read request timing and the phase of the control sequence. The serial data of the external input is supplied to the other serial-parallel conversion means when the serial data of the external input is a normal double speed. The delay serial data output from the serial-parallel conversion means is selected, and 2 in one cycle of the control sequence is selected.
The multiport memory device is operated in a double-speed write mode in which the serial data of the external input is stored in the memory using an access period for a port, and the multiport memory device operates at a double speed when storing the first and second luminance signals. An imaging device controlled to be in a mode.