JP2005011520A - Image data storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To store two kinds of image data inputted in parallel in the form of easily used for image processing, in a single image memory. <P>SOLUTION: An image memory 40 is set as a bank dynamic RAM provided with a plurality of banks. An input data generation circuit 200 alternately time-division multiplexes two kinds of image data, and outputs the data to the image memory 40 through a FIFO 100 and a memory input control circuit 600. A memory address control circuit 700 is provided with an address counter for counting-up the image data each time the data are outputted to the image memory 40. The bank of the image memory 40 is switched to another for storing the image data based on the least significant bit of the address counter. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a technique for storing, in an image memory, a plurality of types of image data that are input at the same time, and more particularly to cost reduction thereof.

As a camera that outputs different types of image data at the same time, for example, a camera that outputs image data of even and odd fields simultaneously is known. In such a camera, image data of two adjacent lines (odd line: odd line and even line: even line) in one frame of an image are simultaneously output. As other cameras that simultaneously output different types of image data, a camera that simultaneously outputs a luminance signal: Y signal and a color difference signal: UV signal, and a camera that simultaneously outputs RGB signals are known.

  Now, taking as an example the case of storing image data from a camera that outputs image data of even and odd fields simultaneously, the configuration of an image data storage device for storing such image data is as follows. Several configurations are known.

In the configuration shown in FIG. 9A, a frame memory is prepared as an intermediate buffer,
In the input data control device, the image data of the even field and the image data of each pixel of the odd field are alternately time-division multiplexed on the output line and sequentially stored in the frame memory. Thereafter, the memory control device reads out the image data from the frame memory, and stores each image data in the image memory in a sequence according to the line in the image frame and the pixels in the line. As a result, an image frame can be reconstructed on the image memory.

Further, as shown in FIG. 9B, a technique is also known in which image data of even and odd fields that are time-divided in units of pixels is directly stored in an image memory. The configuration of the image data storage device in this case is a configuration in which the output of the input data control device is directly written in the image memory in the configuration of FIG.

  In addition to this, as shown in FIG. 9C, a configuration using a plurality of image memories, or a memory capable of accessing an arbitrary address without overhead like a static RAM as shown in FIG. 9D. The configuration to use is known.

  In the configuration using a plurality of image memories, the odd field image data and the even field image data are stored in different image memories.

Further, in the configuration using the static RAM, each image data is stored directly in the image memory in the order according to the line in the image frame and the pixels in the line.

For example, the configuration shown in FIG. 9 (a) requires a frame memory and is relatively expensive. Further, since the frame memory is once used as a buffer, it takes time until the image data is finally stored in the image memory. For this reason, a relatively large delay occurs in the image processing performed using the image data stored in the image memory. This is particularly problematic when performing high-speed image processing such as moving image processing.

  In the configuration in which image data is stored directly in one image memory as shown in FIG. 9B, the image data is not stored in the image memory in an arrangement and format suitable for image processing. And even field image data are stored in a mixed manner, it is not easy to use this image data for image processing.

  In the configuration using a plurality of image memories shown in FIG. 9C, the cost is relatively high because two image memories are required to store one image frame.

Further, when the static RAM of FIG. 9D is used, the cost is increased because the static RAM is relatively expensive and there are many signal lines necessary for accessing the static RAM. Here, in this configuration, dynamic RAM can not be used instead of static RAM.
This is because, when accessing different row addresses, a relatively large overhead time is required.

  In view of such circumstances, an object of the present invention is to realize an image data storage device that stores image data in a format that can be easily used for image processing at a relatively low cost.

  In order to achieve the above object, the present invention is an image data storage device that stores a plurality of types of image data input in parallel, and includes a plurality of continuously accessible storage areas such as a synchronous DRAM. A single image memory, means for time-division multiplexing a plurality of types of image data input in parallel so that each type of image data appears in sequence, and outputting to the image memory, and each image data to the image memory An image having address control means for generating an address in a storage area set exclusively for the type of the image data as an address of an image memory in which the image data is written in synchronization with the output A data storage device is provided.

  According to such an image data storage device, image data input in parallel can be stored in different storage areas without overhead, using an image memory such as a single synchronous DRAM. Thus, storing image data in different storage areas for each type of image data facilitates the use and management of the image data.

  Further, the memory address control means has means for converting the access address into an address for accessing an address in the storage area of the image memory in accordance with a correspondence relationship between the preset access address and the address of the image memory. It is also possible to make it possible to access the image data in the image memory in a storage space of a desired format other than a format for storing different types of image data for each storage area.

  As described above, according to the present invention, an image data storage device that stores image data in a format that can be easily used for image processing can be realized with a single image memory at a relatively low cost.

  Hereinafter, an embodiment of an image data storage device according to the present invention will be described.

  First, a case where the present embodiment is applied to storage of image data from an ODD / EVEN simultaneous capture type camera will be described. Here, the ODD / EVEN simultaneous capture type camera is a camera that simultaneously outputs the image data of the odd field and the even field of the same image frame via two signal lines, and the image data of the odd field and the even field is output. This is a camera whose screen transfer speed is twice that of a conventional video camera that outputs alternately for each field. As will be described later, in this embodiment, the image data of the odd field and the even field are simultaneously captured, and the data is sampled at a frequency more than double the frequency at which the image data is transferred on the signal line, and time division multiplexing The image data of the odd field and the even field is stored in different bank areas of the image memory adopting the bank method.

  FIG. 1 shows a configuration of an image data storage device according to the present embodiment.

In the figure, analog image data (odd field and even field image data of the same image frame) output from the imaging device 10 is converted into an A / D converter 15.
Is converted into digital image data, and the odd-numbered field and even-numbered field image data are simultaneously input to the memory control device 100 that controls the image memory 40. The A / D converter 15 also has a function of separating a synchronization signal such as a vertical synchronization signal and a horizontal synchronization signal from analog image data and outputting it to the memory control device 100.

In the memory control device 100, in order to store the data in the image memory 40 using the input image data and the synchronization signal input from the A / D converter 15, the time division multiplexing of the image data and the memory address are performed. Generation of memory access control signals such as generation and read / write.

  The image processing apparatus 30 is an apparatus that accesses image data stored in the image memory 40 and performs image processing. Here, in the present embodiment, the image processing apparatus 30 grasps the form of image data handled by the memory control apparatus 100 based on the designation from the user and performs various controls of the memory control apparatus 100 according to the form.

  The image data storage device includes a D / A 25 and an image receiving device 20. The D / A 25 converts the image data read from the image memory by the memory control device 100 into analog image data, and outputs the analog image data to the image receiving device 20. The image receiving device 20 displays an image according to the received image data.

Here, in the present embodiment, as the image memory 40, a dynamic RAM adopting a bank system such as a synchronous DRAM is used. Here, the dynamic RAM adopting the bank method has a plurality of storage areas called banks, and if the banks are different, data can be written to different row addresses without overhead.

  Hereinafter, the operation of the memory control apparatus 100 will be described with reference to FIG.

In the figure, odd field data 16 and even field data 17 input from an A / D converter 15 are time-division multiplexed and alternated by an input data generation circuit 200. At this time, the vertical synchronization signal and horizontal synchronization signal input from the A / D converter 15 are input to the input control circuit 300 to check the position of the image data on the screen. used. A valid image data area can be set in the input control circuit 300 via the bus 1 from the image processing apparatus 30. The input control circuit 300 confirms that image data in the valid area has been input in accordance with this setting. And transmitted to the memory address control circuit 700 via the valid data signal 301. The memory address control circuit 700 that has received the valid data signal 301 performs generation of a memory address and generation of a control signal necessary for storing image data in the image memory 40 based on this. The memory address control circuit 700 controls the memory input control circuit 600 so that valid image data is output to the image memory.

The flow of image data will be described in more detail with reference to FIG. 3. First, in the input data generation circuit 200, the image data 16 and 17 are time-divided so that the image data 16 and 17 appear alternately by the multiplexer 210. It is converted into multiplexed image data 201. Here, the multiplexer 210 alternately selects the input image data in synchronization with a frequency twice the sampling frequency of the A / D converter 15 to generate the image data 201. Then, the generated image data 201 is input to the FIFO 110. Only valid image data is stored in the FIFO 110 according to the valid data signal 301. The FIFO 110 is provided to absorb the speed difference when there is a difference between the operating frequency for accessing the image memory 40 and the sampling frequency of the A / D converter 15. The FIFO 110 according to the present embodiment is an alternating buffer type FIFO 110 having a minimum number of stages necessary to absorb the frequency difference. Here, by providing the alternating buffer type FIFO 110 using two sets of FIFOs 110 alternately, the memory input control circuit 600 needs to operate until the other FIFO 110 is satisfied after the image data of one FIFO 110 is processed. There is no. Accordingly, during that period, the bus 50 that is an interface with the image memory 40 can be used for another access to the image memory 40.

  The FIFO 110 is controlled by the data selection circuit 620 determining whether one of the buffers of the FIFO 110 is filled with valid image data in the memory input circuit 600, and if so, the address generated by the FIFO address generation circuit 610. Accordingly, the image data 111 is read from the filled FIFO 110 and output to the image memory 40. The determination of the data selection circuit 620 is executed by counting a signal 701 that the memory address control circuit 700 outputs according to the valid data signal 301 and indicates that valid image data has been inputted to the FIFO 110. However, the valid data signal 301 may be used instead of the signal 701.

Here, FIG. 4 shows a timing chart of outputting image data on each signal line from the A / D converter 15 to the image memory 40.

In FIG. 4, the clock of the transmission frequency of the input image data (sampling clock of the A / D converter 15) is described as CLK1, and the clock used for sampling by the multiplexer 210 is described as CLK2. In this embodiment, the odd-field image data 16 and the even-field image data 17 are converted into time-division multiplexed image data 201 (in the following diagram, the odd-field ODD data is represented by o and even-numbered data). Data for field EVEN is indicated by e). Further, the memory address control circuit 70
Address data 42 generated at 0 and applied to the image memory 40 for writing image data is controlled by a data selection signal 720 that indicates the timing at which the image data is output from the FIFO 110. The data selection signal 720 is controlled in accordance with the valid data signal 301 so as to indicate validity during a period in which image data is output from the memory input control circuit 600 to the image memory. However, the memory input control circuit 600 may supply the data selection signal 720 to the memory address control circuit 700 so as to indicate that it is valid during the period in which the image data is output to the image memory.

  In FIG. 4, for the sake of simplicity, the transfer rate of the image data 201 input to the FIFO 100 and the transfer rate of the image data output from the FIFO 110 to the image memory are shown as being equal.

  Hereinafter, the memory address of the image memory 40 generated by the memory address control circuit 700 will be described.

  First, as shown in FIG. 4 data 16 and 17 as image data forms from the image processing apparatus 30, a form in which odd field data and even field data are input in parallel is set in the memory control apparatus 100. The case will be described.

In this case, as shown in FIG. 5B, for the image data output from the memory input control circuit 600 of FIG. 2 to the image memory 40, these are the odd-field image data as shown in FIG. The memory address control circuit 700 generates a memory address so that the image data of the even field is stored in the banks A and B of the different image memories 40.

  Such a memory address is generated as follows.

  That is, the memory address control circuit 700 sets the internal column address counter to the image memory 40 during the period when the image data is output from the memory input control circuit 600 to the image memory based on the valid data signal 301. Each data output cycle counts up to twice the preset number of effective pixels in the horizontal direction of the image frame. Then, after counting up to twice the number of effective pixels in the horizontal direction of the image frame, an operation of counting up from the beginning is performed. In addition, every time the column address counter counts up to twice the number of horizontal effective pixels of the image frame, the number of effective lines of the image frame (the number of effective lines in the odd field and the even field) Count up). When the number of effective lines of the image frame is counted, an operation for counting up from the beginning is performed.

Then, the memory address control circuit shows the column address 761 counted by the column address counter and the row address 762 counted by the row address counter as shown in FIG. By converting, a column address 771 and a row address 772 used for accessing the image memory 40 are generated.

That is, assuming that the column address is represented by 10 bits and the row address is represented by 9 bits, the second to 10th bits (x0 to x8) of the column address 761 shown in FIG. The column address 771 to be given to the image memory is generated by shifting the bit by 1 bit to the 9th bit and the least significant bit y0 as the 10th most significant bit. Here, the most significant bit y0 of the column address 771 generated in this way becomes a bit 765 that designates the bank of the image memory 40.

  By such memory address conversion, the image data of the odd field and the image data of the even field are stored in different banks according to the arrangement of the pixels in the image frame, as shown in FIG.

  Next, a case where the image data stored in the image memory 40 in this way is accessed from the image processing apparatus 30 in FIG. 1 will be described.

Here, on the image processing apparatus 30, the user (user application) arranges the image data of the odd field and the even field alternately for each line in one image frame as shown in FIG. 5 (a). I manage it. In other words, one image frame is managed as a two-dimensional array of one image data without distinguishing between odd fields and even fields.

When the image processing device 30 performs read access to the image data in the image memory 40, the image processing device uses the column address and row address according to the array (user logical space) of FIG. To pass. The memory control device 100 converts the received address as described below, accesses the image data in the image memory 40, and passes the read image data to the image processing device 30. Similarly, when the image processing device 30 performs write access to the image data in the image memory 40, the image processing device also uses the memory control device to write the column address and row address according to the arrangement of FIG. Pass to 100. The memory control device 100 converts the received address as described below, accesses the image data in the image memory 40, and writes the image data received from the image processing device 30 into the image memory.

  The memory address conversion of the memory control device 100 is performed by the memory address control circuit 700 as follows.

That is, the row address 752 passed from the image processing apparatus 30 shown in FIG.
6 is removed to obtain the row address 772 to be supplied to the image memory 40 shown in FIG. 6C, and the removed lowest bit y0 is the column passed from the image processing apparatus 30 shown in FIG. This is added as the most significant bit (bank designation bit 765 of the image memory) of the address 752, and is used as the column address 771 given to the image memory 40 shown in FIG.

Of course, if the hardware configuration is advantageous, the memory address shown in FIG. 6 (a) is once converted into the memory address shown in FIG. 6 (b), and the input image data is stored in the image memory 40. In the same manner as in this case, the memory address may be converted to the memory address shown in FIG.

  Next, the memory address of the image memory 40 generated by the memory address control circuit 700 when the normal form as the form of the image data from the image processing apparatus 30 is set in the memory control apparatus 100 will be described. Here, the normal form is a form in which only one type of image data is sequentially input to the image data storage device.

In this case, in FIG. 1, the A / D converter 15 outputs the image data to only one of the signal lines 15 or 16. The input data generation circuit 200 outputs the image data received from one of the signal lines 15 or 16 to the FIFO 110 as it is. Other operations are the same as the case of the image data described above in which the odd field data and the even field data are input in parallel.

In this case, when storing input image data as the address of the image memory 40, the memory address control circuit 700 uses the column address 761 by the internal column address counter shown in FIG. 6B and the row address counter. The row address 762 is output to the image memory 49 as it is as the column address and row address of the image memory 40. When accessing the image memory from the image processing apparatus 30, the memory address control circuit 700 receives the column address 751 received from the image processing apparatus 30 shown in FIG. 6A and the image processing apparatus 30. The row address 752 is output as it is to the image memory 49 as the column address and row address of the image memory 40.

  The case where the embodiment of the present invention is applied to storage of image data from the ODD / EVEN simultaneous capture type camera has been described above.

  According to the embodiment described above, two types of image data (odd field and even field) input simultaneously can be stored in different banks of a single image memory. Therefore, there is no overhead problem in writing. Further, in the present embodiment, such input image data writing is realized by bit exchange of the count value of the address counter, and access of the image memory by the user logical space from the user application is also realized by bit exchange of the address. Therefore, a complicated circuit is not required for accessing the image memory. In addition, when the input image data is in the normal form, the user application is made aware of the form of the input image by changing the bit replacement rule according to the form, such as not performing bit replacement of the address. Similarly, the image data in the image memory can be used on the image space (user logical space) managed by the user application. Of course, the other types of image data to be input can be similarly handled by changing the bit replacement rule according to the form.

  As described above, the image data of each form can be used from the user application in the same manner in the image space (user logical space) managed by the user application, which means that the user application can easily perform various image processing. In addition, there is an advantage that the processing speed can be increased due to the ability to perform DMA transfer of image data. Further, since two types of input image data can be recorded separately in different banks, there is an advantage that it is easy to manage each image data independently.

  In the above embodiment, the case where the image data of the odd field and the even field is input to the system at the same time has been described for the ODD / EVEN simultaneous capture type camera. Even when Y data 16 (luminance data) and UV data 17 (color difference data) are input simultaneously as in a color image, the above embodiment can be similarly applied.

In this case, when the input image data is as shown in FIG. 7 (a), the image data is stored in the image memory 40 in the format shown in FIG. 7 (b).

In this case, the user application should manage the image data in the same format as in FIG. 7B, unlike the case of the odd field and even field simultaneous input shown above. In this way, the user application can easily perform image processing on luminance data and color difference data. In this case, in the memory control device 100, the column address and the row address from the image processing device 30 are not converted according to the setting from the image processing device 30.

  The above embodiments can also be applied to a case where image data of two image frames acquired by different imaging devices are input simultaneously instead of a plurality of types of image data constituting the same image frame. In this case, according to the present embodiment, the image data of each camera can be stored in different banks of the same image memory.

  As a result, acquisition of a plurality of image data at the same time can be achieved with less resources.

In the embodiment described above, two types of images are used. However, when there are three or more banks constituting the memory, three or more images are input simultaneously within the range of the number of banks or less. More than one type of image data can be stored in different banks of one image memory at the same time. For example, when inputting an RGB color image in which three types of image data of R, G, and B are input simultaneously,
The switching of the time division multiplexing in the multiplexer 210 of the input data generation circuit 200 of the memory control device 100 is set to three times the sampling frequency of each image data, and one image data is stored in the image memory 40 in the memory address control circuit 700. A column address for switching the designated bank among the three banks is generated for each cycle sent to.

In the image data storage device shown in the above embodiment, the user application manages the space (user logical space) of the image data by dividing it into pages (P00 to P13) as shown in FIG. In such a case, in the image data storage device, each page is arranged in a space (real memory space) on the image memory so that adjacent pages are not stored in the same bank of the image memory 40 as shown in FIG. It may be.

As shown in FIGS. 8C and 8D, this is because the memory control circuit 700 of the memory control device 100 uses the upper 2 bits xa from the column address 801 from the image processing device 30 according to the setting from the image processing device 30. , x9, and instead, the most significant bit y9 of the row address 802 from the image processing device 30 is set to the upper second bit, and the uppermost bit x9 of the removed column address 801 is removed from the image processing device 30. A column address 803 of the image memory 40 having a value obtained by exclusive OR with the most significant bit y9 of the row address 802 from FIG. In the image memory 40, y9 is removed and the upper 2 bits xa, x9 of the column address 801 from the image processing device 30 are added as the uppermost 2 bits of the most significant bit. It can be realized by generating a window address 804.

  Such a method is advantageous when an image larger than the bank of the image memory 40 is handled. In such a case, the input image data of the large image is subjected to memory address control according to the setting from the image processing device 30. In the circuit 700, the column address and the row address by the internal address counter are stored in the image memory by the converted address in the same manner as the conversion of the address from the image processing apparatus 30 to the address to the image memory 40. In this way, for example, when accessing one line of an image arranged across P00, P01, P10, and P11 in FIG. 8A from the image processing device 30, different rows in the same bank are accessed. Never do. Therefore, no overhead occurs and high speed processing is possible.

It is a block diagram which shows the structure of an image data storage device. It is a block diagram which shows the structure of a memory control apparatus. It is a block diagram which shows the structure of an input data generation circuit and a memory input control circuit. It is a timing chart which shows the input / output timing of each part of image data. It is the figure which showed the relationship of address space. It is the figure which showed the state of address conversion. It is the figure which showed the relationship of address space. It is the figure which showed the relationship of the address space in the case of using a page, and the way of address conversion. It is a figure which shows the prior art example of an image data storage device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Bus interface with image processing device 10 Imaging device 15 A / D converter 20 Image receiving device 25 D / A converter 30 Image processing device 40 Image memory 50 Bus interface with memory 100 Memory control device

Claims (3)

An image data storage device for storing a plurality of types of image data input in parallel,
A single image memory with a plurality of continuously accessible storage areas;
Means for time-division multiplexing a plurality of types of image data input in parallel so that each type of image data appears sequentially, and outputting to the image memory;
Address control means for generating an address in a storage area set exclusively for the type of the image data as an address of the image memory to which the image data is written in synchronization with the output of each image data to the image memory An image data storage device comprising: The image data storage device according to claim 1,
The image data storage device, wherein the image memory is a dynamic RAM having a bank configuration, and each storage area is a bank. The image data storage device according to claim 1,
Means for accepting access with an access address to the image memory;
The memory address control means has means for converting the access address into an address for accessing an address in a storage area of the image memory in accordance with a correspondence relationship between a preset access address and an address of the image memory. An image data storage device.

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