KR100238209B1 - Mosaic processing apparatus using line memory - Google Patents

Abstract

A mosaic processing apparatus using a line memory is disclosed. The mosaic processing apparatus is a mosaic processing apparatus that performs mosaic processing on input image data in accordance with predetermined vertical and horizontal mosaic block sizes (M × N, where M and N are integers) input from a microcomputer. In response to a first vertical mosaic control signal indicating the first vertical mosaic control signal, stores the input image data in units of one line and outputs the vertical mosaic control signal in response to a second vertical mosaic control signal indicating an inverted state of the first vertical mosaic control signal, A first line memory and a second line memory for outputting line-by-line data; An address counter for generating an address of the first and second line memories in response to a reference clock; A multiplexer for inputting data output from the first and second line memories and selectively outputting the data in response to a first vertical mosaic control signal; A data delay means for receiving data output from the multiplexer and outputting the data in response to a horizontal mosaic control signal; Vertical mosaic control signal generating means for outputting, as first and second vertical mosaic control signals, signals obtained by dividing a horizontal driving pulse, which is a line synchronizing signal of image data, into M magnitudes; And a horizontal mosaic control signal generating means for outputting, as a horizontal mosaic control signal, a signal obtained by dividing the reference clock by N magnitude. Therefore, the efficiency of the memory is good and the cost is reduced while achieving the same effect as the effect using the field memory.

Description

Mosaic processing device using line memory

The present invention relates to a mosaic processing apparatus which is a special effect of a video signal, and more particularly to a mosaic processing apparatus which efficiently uses a memory using two line memories.

There are generally two ways to implement mosaics using field memories. As a first method, a field memory is used for each field, and the stored image data is divided into a predetermined block size for each field, the data amount of each pixel in each block included in the same field is summed and then divided by the number of pixels The average data is obtained, and the mosaic is filled with the same average data calculated at the positions of the pixels included in each block. That is, each field data of the image data is stored in the field memory, and then the value of each pixel is read by the address control to perform arithmetic processing. In the second method, the image data of each field is divided into a predetermined block size, and a mosaic is implemented by filling the remaining pixels with data of a representative pixel of each block at each pixel position of each block. That is, only a specific pixel value is read and mosaiced.

These methods have a problem in that the memory efficiency is not good because the capacity of the memory increases and the cost is high because the method uses the field memory. In particular, the conventional method reads the value of one pixel in one block and processes it.

It is an object of the present invention to provide a vertical mosaic effect by simultaneously processing data in one line memory and data in another line memory in response to a vertical mosaic control signal using two line memories, And to provide a mosaic processing apparatus that implements a horizontal mosaic effect by sampling data output from a line memory in response to a control signal.

1 is a block diagram of a mosaic implementation system including a mosaic processing device in accordance with the present invention.

2 is a circuit diagram of a preferred embodiment of the mosaic processing apparatus according to the present invention.

3 is a timing chart for explaining a read / write operation of a normal line memory.

4 is a timing chart for explaining a vertical mosaic in the 4x4 mosaic mode.

FIG. 5 is a timing chart for explaining a horizontal mosaic in the 4x4 mosaic mode.

According to an aspect of the present invention, there is provided a mosaic processing apparatus using a line memory, the mosaic processing apparatus comprising: a mosaic processing unit for mosaicing the inputted image data in accordance with vertical and horizontal mosaic block sizes (M x N, Wherein the first vertical mosaic control signal is an inverted state of the first vertical mosaic control signal, and the second vertical mosaic control signal is an instruction for instructing a read operation, A first line memory and a second line memory for outputting data of a line unit already stored in response to the second vertical mosaic control signal; An address counter for generating an address of the first and second line memories in response to a reference clock; A multiplexer for inputting data output from the first and second line memories and selectively outputting the data in response to a first vertical mosaic control signal; A data delay means for inputting data output from a multiplexer and outputting data in response to a horizontal mosaic control signal; Vertical mosaic control signal generating means for dividing a horizontal driving pulse, which is a line synchronizing signal of image data, into M size and outputting the divided signals as first and second vertical mosaic control signals; And a horizontal mosaic control signal generating means for dividing the reference clock into N size and outputting the divided signal as a horizontal mosaic control signal.

Hereinafter, the configuration and operation of the mosaic processing apparatus of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram of a mosaic implementation system including a mosaic processing apparatus according to the present invention. The mosaic processing system 30 and the line memory 40 constitute a microcomputer 10 and a mosaic processing apparatus 20.

The mosaic processing apparatus 20 shown in FIG. 1 corresponds to the vertical and horizontal mosaic block sizes (M × N, where M and N are integers) input from the microcomputer 20 to image data input from the input terminal IN And outputs it through the output terminal OUT. The mosaic processing apparatus 20 of the present invention uses a line memory for storing image data in units of one line in order to realize a mosaic effect. For example, to implement the mosaic effect of filling one block of a predetermined size with the remaining pixels, only one line among the data lines corresponding to the M size is stored in the line memory, It is necessary to maintain only the data of one pixel out of the N-sized data, and then output the data of N pixels.

Fig. 2 is a circuit diagram of a preferred embodiment of the mosaic processing apparatus 20 of the present invention shown in Fig. 1. The first line memory LM1 41, the second line memory LM2 43, the address counter AC ) 31, a multiplexer (MUX) 33, a data delay unit (D flip-flop) 35, a vertical mosaic control signal generating unit 37 and a horizontal mosaic control signal generating unit 39.

The first line memory 41 shown in FIG. 2 responds to a first vertical mosaic control signal V1 indicating a read / write operation, and outputs data input in response to the reference clock CK when a write operation is instructed When a read operation is instructed, the data already stored is output in a line unit. In response to the second vertical mosaic control signal V2, which is the inverted state of the first vertical mosaic control signal V1, the second line memory 43 is connected to the first line memory 41, Perform the opposite task. At this time, the addresses in the first and second line memories 41 and 43 are generated in the address counter 31 in response to the reference clock CK. Since the first and second line memories 41 and 43 respond to control signals inverted from each other, the outputs of the data are alternately outputted, and the multiplexer 33 outputs the data from the first and second line memories 41 and 43 In response to the first vertical mosaic control signal. The data delay unit 35 for inputting the data output from the MUX 33 samples the data in response to the horizontal mosaic control signal H_CK.

According to the above description, the first and second line memories 41 and 43 and the multiplexer 33 respond to the vertical mosaic control signal and the data delay unit 35 responds to the horizontal mosaic control signal. The vertical mosaic control signal is generated from the vertical mosaic control signal generating unit 37. [ The first divider 7 of the vertical mosaic control generating unit 37 divides the horizontal driving pulse HD which is the line synchronizing signal of the image data into a predetermined vertical mosaic block size M inputted from the micom 20 . And outputs the divided signal as a first vertical mosaic control signal V1 which is a read / write control signal of the first line memory 41 and outputs the inverted signal of the divided signal to the read / write control As a second vertical mosaic control signal V2 which is a signal. In addition, a horizontal mosaic control signal is generated from the horizontal mosaic control signal generating unit 39 in the mosaic control signal. The second frequency divider 9 divides the reference clock CK into a predetermined horizontal mosaic block size N input from the microcomputer 20. And outputs the divided signal as a horizontal mosaic control signal H_CK, which is a clock signal of the data delay unit 35.

FIG. 3 is a timing chart for explaining a read / write operation of a conventional line memory, in which (a) shows a horizontal drive pulse HD, and FIG. 3 (b) . In order to alternately perform a line-by-line read / write operation in two line memories, the horizontal drive pulse HD is divided into two to divide the first and second vertical mosaic control signals (c) and (V1 and V2). (E), the MUX 33 responding to V1 selects and outputs the data output from the first line memory 41 when V1 is high and outputs V1 And selects and outputs the data output from the second line memory 43 when it is low. As a result, data input to the two line memories is input and selectively output.

Now, the mosaic effect is described as follows, for example, the vertical and horizontal mosaic block sizes (M × N) are 4 × 4.

FIG. 4 is a timing chart for explaining a vertical mosaic in the 4 × 4 mosaic mode, in which (a) shows a horizontal drive pulse HD, and FIG. 4 (b) . (c) is a first vertical mosaic control signal V1, which is a signal obtained by dividing the horizontal drive pulse HD by four, and (d) is a second vertical mosaic control signal V2. Here, V1 and V2 indicate a read / write operation two consecutive times. In fact, video images are composed of odd and odd fields per frame. Therefore, if the vertical mosaic block size is 4, only two lines for one field are mosaiced.

4 (c) and 4 (d), if the write operation is instructed twice consecutively, the line memory overwrites the stored first line data L1 and stores the next line data L2. That is, the line data stored first is erased. Therefore, as shown in (e) of FIG. 4, if the data stored last is held and the reading operation is instructed twice consecutively, the same line data is output twice.

FIG. 5 is a timing chart for explaining a horizontal mosaic in the case of a 4 × 4 mosaic mode, in which (a) shows a reference clock CK, and (b) shows image data D1, D2, D3. . (c) is a horizontal mosaic control signal H_CK which is a signal obtained by dividing the reference clock CK by four. Since the duty cycle of the divided signal is 25% at this time, the horizontal mosaic control signal H_CK occurs once every four periods of the reference clock CK. Accordingly, the data delay unit 35 responsive to the horizontal mosaic control signal H_CK samples the data as shown in (d) and outputs the same data for four periods of the reference clock CK.

As a result, in the present invention, the mosaic effect in the vertical direction can be realized by changing the read / write control condition of the line memory in response to the vertical mosaic control signal, and the mosaic effect in the horizontal direction can be realized by the data delay unit It can be implemented by changing the clock frequency.

As described above, the mosaic processing apparatus using the line memory according to the present invention is capable of simultaneously processing the data in one line memory and the data in the other line memory, thereby achieving the same effect as using the field memory The memory efficiency is good and the cost is reduced.

Claims (1)

A mosaic processing apparatus for mosaicing input image data in accordance with vertical and horizontal mosaic block sizes (M × N, where M and N are integers) input from a microcomputer, comprising: a first vertical mosaic control signal In response to the second vertical mosaic control signal indicating the read operation, outputs the data of one line unit already stored in response to the second vertical mosaic control signal in the inverted state of the first vertical mosaic control signal An address counter which generates an address of the first and second line memories in response to a reference clock, and a second line memory which receives data output from the first and second line memories, A multiplexer for selectively outputting in response to a first vertical mosaic control signal, And outputting data in response to a horizontal mosaic control signal; dividing the horizontally driving pulse, which is a line synchronizing signal of image data, into the M size and outputting the divided signal to the first and second vertical And a horizontal mosaic control signal generating means for dividing the vertical mosaic control signal generating means and the reference clock into the N-gray and outputting the divided signal as the horizontal mosaic control signal. Device.