KR200283945Y1 - Multi-screen splitter with picture quality protection - Google Patents

Abstract

According to the present invention, when both the multi-channel input and output signals of an imaging apparatus displaying a multi-channel video input signal divided into multiple screens on one monitor display are asynchronous, the order of even-numbered scan lines and odd-numbered scan players are reversed. The present invention relates to a multi-screen splitter capable of preventing image quality deterioration to compensate for image quality deterioration. The present invention provides an input channel for receiving a video signal from each video camera; An A / D converter converting the analog video signal received by the input channel into a digital video signal; A memory unit for temporarily storing the digital video signal in units of screens of one frame or one field; A memory controller for controlling timing of writing and reading of an output of the A / D converter to the memory to display a plurality of divided screens on one screen; A digital signal processor for compressing data stored in the memory unit; A D / A converter which reads the compressed video signal from the digital signal processor and converts the compressed video signal into an analog signal; And a display unit for displaying the output of the D / A converter on a split screen or a normal screen, the memory unit being arranged in order of generating the digital video signal in units of screens of one frame or one field to the memory unit. And a field memory unit used in a FIFO mode for temporarily storing and outputting video data in a stored order.

Description

Multi-screen splitter with picture quality protection

The present invention relates to a multi-screen splitter capable of preventing image quality deterioration, and more particularly, the multi-channel input and output signals of a video device that displays a multi-channel video input signal divided into multiple screens on one monitor display are asynchronous. In this case, the present invention relates to a multi-screen splitter capable of preventing image quality deterioration to compensate for image quality deterioration as the order of even-numbered scan lines and odd-numbered scan players change.

In general, in video equipment such as color video printers, television receivers, and video cassette records, a plurality of screens are displayed by one monitor indicator when they are displayed on a monitor by temporarily storing and compressing video signals coming from a plurality of signal input sources. can do.

1 is a system block diagram of a conventional multi-screen divider. In the present embodiment, a description will be given using a four-screen divider as an example. As shown in the figure, the conventional four-screen divider converts the input channels CH1, CH2, CH3, and CH4 that receive video signals from each video camera, and the analog video signals received by the input channels to digital video signals. A / D converters 11, 21, 31, and 41, and memory units 15, 25, 35, and 45 for temporarily storing digital video signals in units of screens of one frame or one field. Timing of writing and reading of the outputs of the A / D converters 11, 21, 31, and 41 to the memory units 15, 25, 35, and 45 in order to display a plurality of divided screens on one screen. The memory control unit 54, a digital signal processing unit 13, 23, 33, 43 for horizontally and vertically compressing the data stored in the memory unit 15, 25, 35, 45, and the digital signal processing unit A D / A converter 50 for reading out the compressed video signal from 13, 23, 33, 43 and converting it into an analog signal form; And a display unit 52 composed of a monitor for displaying the output of the D / A converter 50 on a split screen or a normal screen.

Hereinafter, an operation process of a conventional multi-screen splitter will be described with reference to the above-described configuration. That is, when power is applied, analog signals received from the input channels CH1, CH2, CH3, and CH4 are A / D converted through the A / D converters 11, 21, 31, and 41, and are output as digital video signals. . The digital video signal is 2: 1 compressed horizontally and vertically in the digital signal processing units 13, 23, 33, 43 and is transmitted to the memory units 15, 25, 35, 45. In this case, the memory controller 54 stores the odd and even fields in the memory units 15, 25, 35, and 45. The data stored in the memory units 15, 25, 35, and 45 are output by the control of the memory control unit 54 to output a multi split screen in accordance with the video synchronization signal for D / A conversion. The output video data is D / A converted to output an analog signal.

As described above, in order to match the even and odd fields, the memory controller 54 needs to designate a address when writing or reading the data of each channel, which requires a large amount of logic circuits, resulting in higher unit cost. There is a problem.

2A to 2D are exemplary diagrams illustrating a predetermined pattern of scan lines of even and odd fields in the interlaced scanning method of NTSC signals. 2A is a separate odd field, and FIG. 2B is a separate even field. FIG. 2C is a diagram in which even and odd fields are synthesized in a normal order, and FIG. 2D is a case in which even and odd fields are reversed. And the other half of the video data is inverted lines, and the vertical resolution of the screen drops sharply.

In the asynchronous multi-screen split display, this phenomenon is caused by a difference in synchronization between the input video signal and the output multi-screen split and is a problem that occurs even when the storage capacity of the intermediate memory is increased.

The present invention was devised to solve the above-mentioned problem, and the field memory which does not need address designation is used as a first-in first-out (hereinafter referred to as First-In First-Out: FIFO) mode to eliminate the number designation of the memory controller. It is an object of the present invention to provide a multi-screen divider capable of preventing image quality deterioration so that image quality does not deteriorate even if the order of even and odd fields is changed.

In order to achieve the above object, a multi-screen splitter capable of preventing image quality deterioration may include an input channel configured to receive a video signal from each video camera; An A / D converter converting the analog video signal received by the input channel into a digital video signal; A memory unit for temporarily storing the digital video signal in units of screens of one frame or one field; A memory controller for controlling timing of writing and reading of an output of the A / D converter to the memory to display a plurality of divided screens on one screen; A digital signal processor for compressing data stored in the memory unit; A D / A converter which reads the compressed video signal from the digital signal processor and converts the compressed video signal into an analog signal; And a display unit for displaying the output of the D / A converter on a split screen or a normal screen, the memory unit being arranged in order of generating the digital video signal in units of screens of one frame or one field to the memory unit. And a field memory unit used in a FIFO mode for temporarily storing and outputting video data in a stored order.

1 is a system block diagram of a conventional multi-screen splitter,

2A to 2D are exemplary diagrams illustrating a predetermined pattern of scan lines of an even field and an odd field in the interlaced scanning method of an NTSC signal;

3 is a system block diagram of a multi-screen divider of the present invention.

*** Explanation of symbols for main parts of drawing ***

CH1, CH2, CH3, CH4. Input channels,

11, 21, 31, 41, 61, 71, 81, 91.A / D converter,

13, 23, 33, 43, 63, 73, 83, 93. Digital signal processing unit,

15, 25, 35, 45. Memory section,

65, 75, 85, 95. Field memory section,

50, 100.D / A converter,

52, 102. Display,

54, 104. Memory Control

Hereinafter, a multi-screen splitter capable of preventing image quality deterioration according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

3 is a system block diagram of a multi-screen divider of the present invention. In the present embodiment, a description will be given using a four-screen divider as an example. As shown in this figure, the four-screen divider of the present invention is an input channel (CH1, CH2, CH3, CH4) for receiving a video signal from each video camera, and the analog video signal received by the input channel as a digital video signal. A / D converters 61, 71, 81, and 91 to convert the digital video signal are temporarily stored in order of occurrence in one frame or one field, and video data is stored in the stored order. Field memory section 65, 75, 85, 95 used in the FIFO mode to output, A / D to the field memory section 65, 75, 85, 95 to display a plurality of divided screens on one screen 2: 1 compression processing of the data stored in the memory control unit 104 and the field memory units 65, 75, 85, and 95 that control the writing and reading of the outputs of the converters 61, 71, 81, and 91; Digital signal processor 63, 73, 83, 93, digital signal processor 63, 73, 83, 9 3) a display unit including a D / A converter 100 that reads the compressed video signal from 3) and converts it into an analog signal form, and a monitor that displays the output of the D / A converter 100 on a split screen or a normal screen; 102).

Hereinafter, an operation process of the multi-screen divider of the present invention will be described with reference to the above-described configuration. That is, video data that is A / D converted, digital signal processed, and 2: 1 compressed horizontally and vertically are stored in order in the order in which they occur in the field memory sections 65, 75, 85, and 95. In this case, the memory controller 104 needs only write control so that video data of each input channel CH1, CH2, CH3, CH4 are stored in sequence, and the field memory units 65, 75, 85, 95 operate only in the FIFO mode. There is no need to specify a street address when writing. The field memory units 65, 75, 85, and 95 need only have a capacity for storing compressed video data in one frame consisting of two fields (odd 1 field + even 1 field). In the order of storing in the field memory sections 65, 75, 85 and 95, the odd fields are always first. When the video data stored in the field memory units 65, 75, 85, and 95 are read, the video synchronization of the output signal is faster or slower than the video synchronization input. When the output data is an odd field and the video output to the monitor stage becomes an even field, 1 H SYNC (horizontal sync signal) when the even field of the next field memory unit 65, 75, 85, 95 is read out. By controlling the memory control unit 104 to read by delaying as much as possible, it is possible to configure a normal screen except for the case of 1H at the top and the bottom. Even if the output video is an odd field and the data of the field memory units 65, 75, 85, and 95 are read even data of the even field, the data is delayed by 1 H SYNC in the next field.

The multi-screen splitter capable of preventing image quality deterioration of the present invention is not limited to the above-described embodiments, and may be modified in various ways within the range permitted by the technical idea of the present invention.

As described above, according to the multi-screen splitter capable of preventing image quality deterioration, by eliminating address designation, a large number of addressing logic circuits can be reduced in the case of multi-channel input, and the field memory unit is used in the FIFO mode to The problem of vertical resolution deterioration due to the reversed order is reduced.

Claims (1)

An input channel for receiving a video signal from each video camera; An A / D converter converting the analog video signal received by the input channel into a digital video signal; A memory unit for temporarily storing the digital video signal in units of screens of one frame or one field; A memory controller for controlling timing of writing and reading of an output of the A / D converter to the memory to display a plurality of divided screens on one screen; A digital signal processor for compressing data stored in the memory unit; A D / A converter which reads the compressed video signal from the digital signal processor and converts the compressed video signal into an analog signal; And a display unit for displaying the output of the D / A converter in a split screen or a normal screen. Preventing deterioration of image quality, characterized by using a field memory unit used in the FIFO mode to temporarily store the digital video signal in the order of generating one frame or one field and output the video data in the stored order. Available multi-screen splitter.