KR100272447B1 - Multi-picture display conteoller - Google Patents

Abstract

PURPOSE: A multiscreen divider is provided to reduce a memory capacitance by displaying many images input from many image sources on one monitor as a divided screen format. CONSTITUTION: A video decoder(21) of a multi-channel receives a video signal of asynchronous multi-channel between channels, is locked to the asynchronous video data of each channel, and outputs the video signal as a digital video data. A horizontal/vertical scaler(22) receives a digital video data from each video decoder, and is connected to each decoder so as to reduce a size of image, thereby storing the divided screen about an input signal of the multi-channel. An asynchronous buffer(23) receives a reduced image data from the horizontal/vertical scaler, and outputs a data synchronized to a main system. A memory controller determines the order of reading action of the asynchronous buffers according to a priority order of the asynchronous buffers, reads a data, writes the data in a predetermined memory address every channel, reads the divided screen data in a burst unit, and converts the divided screen data to a successive real-time image signal. 1 frame memory stores a data by the controller. A video buffer sequentially outputs the image data according to a video timing. A video encoder outputs a digital video input signal from the video buffer as analog composite image.

Description

Multi Screen Splitter

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-screen divider for displaying a plurality of images inputted from a plurality of image sources such as a video camera by dividing them into a single screen on a single monitor.

In general, the multi-screen splitter is a device for simultaneously displaying the number of split screens as many as the number of cameras on one monitor screen. 1 illustrates a structure of a periphery monitoring system including a color four-screen splitter, which is an embodiment of a multi-screen splitter, and includes four cameras for inputting video signals, a color four-screen splitter, and a monitor for displaying an input image. The operation is composed of different video signals inputted from four cameras into a color four-screen splitter, and the splitter inputted with the video signal is divided into four divided images and four video signals on one screen of the monitor. Is displayed at the same time. This device is mainly used for security equipment such as closed circuit TV for surveillance of the surroundings, so that the signals of cameras installed in each region can be monitored at the same time to monitor the four regions. The four-screen divider usually consists of four image inputs and four divided image outputs. For example, the image of the first camera 1 is on the upper left (A) of the monitor, the image of the second camera (2) is on the right (B) of the monitor, and the image of the third camera (3) is In the lower left (C), the fourth camera (4) image is displayed in the lower right (C) of the monitor is a function of the general four-screen splitter (5), and a number of other additional functions can be added to this function. Can be.

Conventionally, a black and white four screen divider has been used, but now a color four screen divider has been developed and spread. The color 4-screen splitter 5 processes color images, so that a video controller that requires a technique such as a video decoder, a video encoder, or the like is used for video processing. That is, since the video controller applied to the conventional four-screen divider uses four video memories connected to four video decoders, a large amount of memory is required.

The prior art will be described in more detail with reference to FIG.

Fig. 2 shows a conventional color four-screen image splitter, comprising four video decoders connected to respective image sources for converting an input image from four image sources, such as a video camera, into digital video data. 11, video decoder, four memories 12 connected to each decoder 11 for storing digital video data converted by the decoder 11 as described above, and images stored in the respective memories are displayed simultaneously. To this end, a memory controller 13 defining four screen positions in a monitor and a video encoder 14 for converting digital video data stored in the memory 12 into composite analog video and outputting the composite analog video to the monitor encoder).

When the color four-screen image splitter is described according to the flow of signals, the input video signal is input from the first to fourth cameras, and its characteristics may be regarded as a standard video standard. The input video signal is decoded by the video decoder 11. The decoder 11 is a generic term for various functions. The function of the decoder is to first output the YUV (luminance signal: Y, chrominance signal: U, V) digital data, which is a standard of luminance signal and chrominance signal, by componentizing the input composed of the first composite. The second function is to convert the analog video input to digital, and is done by an analog-to-digital converter, and the third is to generate a clock for digital processing. Generates a clock that is locked to the video signal. Decoder 11 outputs output by this function are clock and digital video data and video timing signals. At this time, an important point is that the outputs of the four video decoders 11 are output by a clock synchronized with each input signal. This means that the four decoder 11 outputs are not synchronized.

The output of each decoder 11 is then stored in each memory 12 which is an image storage medium. The image information stored in the memory 12 may store an entire screen or an image reduced to 1/4. Most of the memories made by IC are used to store one screen, so most of the memory is stored one screen. In this case, a memory size for storing each video signal in a 1/4 screen may be used, but there is no such memory among the currently used memories, which causes a lot of difficulties. The memory for video application consists of storing all one screen, and the general-purpose memories can use small ones, but the memory for video is inevitably used because the controller has to be designed separately for each channel. Therefore, a memory for storing one entire screen is used, and as a whole, four screens are used to store four screens 12. Although the four-screen divider has been described here, in order to display more multi-screens such as 9-split, 16-split, and n-split in real time, as much memory as the number of divided screens is required.

Next, screen output is selectively performed by the memory controller 13 among the image information stored in each memory 12. The memory controller 13 defines four screen positions according to timing information of the video encoder 14 which will be described later, and outputs one of four stored image information at a specific screen position among the four screens. That is, when the position of the output screen is located at the upper left, the memory 11 storing the input of camera 1 is transferred from the memory 11 to the video encoder 14 which will be described later, and displayed. The same is true for the input of.

The video encoder 14 then converts the digital video data input to the YUV component into composite analog video and outputs it to the monitor. The video encoder 14 is generally operated in a master mode, so that the timing of the memory controller 13 is eventually controlled by the timing information of the video encoder 14. As described above, the output of the video encoder 14 is finally output to the monitor through a process of adding an On Screen Display (OSD) or other various functions indicating a function of generating characters on the image screen.

In the above-described process, it can be seen that the memory controller 13 is responsible for the screen division function and the memory access function. Therefore, varying the functions of the memory controller 13 will eventually vary the functions of the screen divider.

As described above, the conventional color four-screen divider uses memory as many as the number of screens to be divided to store the screen. In other words, if there are n video sources, n decoders and n memories are required. Therefore, in order to manufacture the n-screen divider, the use of n memories causes not only an increase in manufacturing cost but also a complicated system, which causes a difficulty in manufacturing and increases a defective rate.

In order to solve the above-mentioned problems, the present invention significantly reduces the memory capacity by using one frame memory for storing one screen and an asynchronous buffer corresponding to the number of input image signals supporting the memory. Aims to improve productivity by lowering the cost and simplifying the system.

In order to achieve the above object, the present invention provides a multi-channel video decoder for inputting an unsynchronized multi-channel video signal between channels and locking the asynchronous video data of each channel to output digital video data. A horizontal / vertical scaler for reducing an image for split-screen storage for multi-channel input signals by inputting digital video data output from each video decoder, and at an arbitrary magnification through the horizontal / vertical scaler. Read the data by determining the reading order of the asynchronous buffers according to the read priority of the asynchronous buffers and the same number of asynchronous buffers as the input channels for inputting horizontal / vertically reduced image data and outputting the synchronized data to the main system. You can write to any memory address assigned to each channel in real time. A memory controller which reads the plurality of reduced stored split screen data in burst units and converts the data into a continuous real-time video signal, one frame memory that stores or outputs data by the controller, and the discontinuity. A video buffer that stores the image data stored in the memory read out in burst units and continuously outputs the video data according to the video timing, and the digital video input signal output from the video buffer as an analog composite image for each broadcasting method. A multi-screen splitter including an output video encoder is featured.

1 illustrates an embodiment of a system using a color four screen divider.

Fig. 2 is a block diagram showing an embodiment of a conventional color four screen divider.

3 is a block diagram showing a color four screen divider as an embodiment of a multi-screen divider in accordance with the present invention;

4 is a diagram showing the timing of an asynchronous input signal in a color four-screen divider, which is one embodiment of a multi-screen divider according to the present invention.

<Brief description of the main parts of the drawing>

1: first camera 2: second camera

3: third camera 4: fourth camera

5: 4-screen splitter 6: Monitor

A: Image of the first camera B: Image of the second camera

C: Image of third camera D: Image of fourth camera

11: video decoder 12: memory

13: Memory Controller 14: Video Encoder

21: Video decoder 22: Horizontal / Vertical Scaler

23: asynchronous buffer 24: adaptive asynchronous buffer controller

25: Real time memory write controller 26: 1 frame memory

27 real time memory read controller 28 video buffer

29 video encoder 30 memory controller

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

Fig. 3 shows a color four-screen splitter, which is an embodiment of a multi-screen splitter according to the present invention, comprising four decoders 21 for outputting video signals of each video camera as video digital data, and respective decoders 21, respectively. Four horizontal / vertical scalers 22 for reducing the image for dividing the digital video data outputted from the image) for the split screen storage, and video data reduced by the respective scalers 22 at an arbitrary magnification. Four asynchronous buffers 23 to output data synchronized to the system, and a random memory designated for each channel in real time by reading the data by determining the read order of the asynchronous buffers according to the read priority of the asynchronous buffers 23 By controlling the writing to the address, the plurality of reduced and stored split screen data are read in burst unit read and continuous real-time video scene Images stored in a memory controller 30 for controlling conversion into a memory, a 1 frame memory 26 for storing and outputting data by the controller 30, and a memory 26 read in the discrete burst unit. A video buffer 28 for storing data and continuously outputting the data according to video timing, and a video encoder 29 for outputting a digital video input signal output from the video buffer 28 as an analog composite image for each broadcasting method. It is composed of

In the above, the memory controller 30 determines the read order of the asynchronous buffers according to the read priority of the asynchronous buffers, and reads the data from the adaptive asynchronous buffer controller 24. A real-time memory write controller 25 that controls the data to be written to an arbitrary memory address designated for each channel in real time, and the plurality of reduced and stored divided screen data are read in burst units and read through the video buffer 28. It consists of a real time memory read controller 27 which controls to be converted into a continuous real time video signal. In addition, operations of the video decoder 21 and the video encoder 29 are the same as those of the video decoder 11 and the encoder 14 of the conventional color screen divider.

4 shows input timings in an asynchronous state, in which video signals inputted from different channels are shifted from each other in horizontal and vertical sync signals, and operating frequencies are input differently due to variations in the internal oscillator circuits of the respective cameras. Each of the video signals is completely asynchronous.

The asynchronous video input signal processing as described above has no problem in a system in which each independent frame memory is allocated to each channel as in the conventional four-screen divider, but the image of each channel using one memory as in the present invention. In a system configuration that reduces and stores information to 1 / n (n is the number of multi-screens), since each channel cannot be controlled at the same timing, it is impossible to implement the system by simple memory control.

Therefore, in the screen divider of the present invention, the asynchronous system is synchronized using an asynchronous buffer 23 having a small capacity (using a FIFO of 1-line video memory or less). When a small amount of memory is added to the back of the video decoder 21 in several multi-channels to write to this memory, it is controlled by the clock and data synchronized with each decoder 21. Allows control by the system clock used. By operating as described above, the processing after the asynchronous buffer 23 can be viewed as a synchronous system, and is simplified in terms of control. Subsequently, the output of the asynchronous buffer 23, one for each channel, can be controlled by the same clock or timing since it is synchronized with the main system. That is, the memory controller 30 can directly control this. The output of the asynchronous buffer 23 synchronized to the system is controlled by the memory controller 30 to store all memory such as DRAM, SDRAM, SGRAM, video RAM, etc., having a memory capacity of 1 frame (where the memory is randomly accessible). N screens are divided into 1 / n video signals, respectively, and are stored. In this case, the main memory is a memory having a capacity capable of storing all one image and should be capable of random access.

The memory controller 30 includes an adaptive asynchronous buffer controller 24 and real-time memory write / read controllers 25 and 27 to control the asynchronous buffers 23 so that input data is not lost due to overflow. And the video signal read out from the asynchronous buffer 23 at the address of the designated position for each channel of the memory, divided into a plurality of screens, and the stored video signal is read out at a predetermined constant read timing to read the video buffer 28. Through this function, the video signal is output to the video encoder 29 in real time according to the continuous video signal timing. The divided screen broadcast standardized through the video encoder 29 is displayed on a monitor or stored in a recording medium such as a VCR.

The memory controller 30 will be described in more detail. The asynchronous video signal input from the video decoder 21 is valid from the effective pixel start point of each channel by the asynchronous system frequency of each channel as shown in FIG. The effective video signal of the pixel section is written to the asynchronous buffer 23. As described above, the write start timing of the asynchronous buffer 23 is different for each channel, and the amount of data stored in the asynchronous buffer 23 is inevitably due to different fast system frequencies. 23) In order to prevent data loss due to overflow, it is impossible to control by sequential reads, and it is possible to always check the amount of data stored in the buffer and read the data in the buffer with the least amount of free space. Adaptive asynchronous buffer control is required and the block for this is the adaptive asynchronous buffer controller 24. On the other hand, the data read by the control of the adaptive asynchronous buffer controller 24 performs a write operation in accordance with the interface timing of the frame memory 26 at the address of the designated address for each channel and is inputted to the asynchronous buffer 23. The real-time memory write controller 25 is a block which allows the read data of the data to be stored in real time without loss, and also controls the real-time read operation for display of the divided image data stored in the memory 26 and the continuous video encoder 29 The real-time memory read controller 27 is a block for controlling the real-time read operation by the video encoder 29 at the rear end by controlling the video buffer 28 for outputting the video to the. The position of the frame memory 26 to be written at this time is where each channel should be displayed. If the system is set to position camera 1 on the upper left of the output screen, the asynchronous buffer 23 output of channel 1 is written to the frame memory 26 located on the upper left of the screen. The other three asynchronous buffer outputs are also written to their respective positions: upper right, lower left, lower right. In this case, the horizontal / vertical scaler 22 for the video signal for reducing and storing the four-channel video signal in the frame memory 26 having a one-frame capacity may be embedded in the video decoder 21 at the front end or an asynchronous buffer. (23) Previously, a sub-sampling block through a unique low-band filter may be implemented. In contrast to the prior art, the present invention can be referred to as a reverse order. The conventional technique selects a channel according to the output screen position from the time of outputting the image of each channel already stored to the video encoder 14, but in the present invention, the asynchronous buffer is adapted to the position of the output screen from the storage in the frame memory 26. When the memory 26 is read, the main memory data is sequentially output, converted into continuous video output timing through the video buffer 28, and sequentially output to the video encoder 29. Just do it. In this case, the video buffer 28 behind the real-time memory read controller 27 may not be necessary when using dual port memory, but in general, the image storage memory has only a single port memory. Therefore, although not limited to a specific operation of the memory, it may be slightly different depending on the memory, but the write operation is performed at a time with a plurality of bytes at a time, and then the read operation is performed at a time with a continuous timing at a time. When a memory read / write is performed by using a multibyte packed unit memory read / modified-write cycle, which collectively refers to a memory read / write operation, a plurality of bytes of information are continuously stored in the memory 26. Performs a function of converting discontinuous image information in burst units read from the memory into a continuous image output, after reading and storing a plurality of byte information information. The video buffer 28 may be embedded in the memory (eg, video RAM) or may not be embedded in the memory (eg, SGRAM, SDRAM, or DRAM) depending on the memory 26 used. In the former case, the system can be configured without a video buffer, but in the latter case, a video buffer is required as in the present invention.

The video encoder 29 converts an analog composite video signal by receiving data from a memory as in the conventional art. In addition, it is common to perform a master mode operation, so that the video timing information is transmitted to the memory controller 30 to control the access timing of the main memory 26. The reading of the memory 26 may simply be a whole reading process according to the video timing, and the reading process may be complicated depending on additional functions, but the processing is the same. This function is also the memory controller 30, the main function of the memory controller 30, along with controlling the asynchronous buffer 28 mentioned above.

As described above, the multi-screen divider of the present invention can solve the problem of the conventional screen divider that uses a large amount of memory, thereby significantly reducing the capacity of the memory, thereby reducing the manufacturing cost and additionally significantly reducing the defective rate, thereby improving productivity. Can be improved.

Claims (3)

A multi-channel video decoder which inputs an unsynchronized multi-channel video signal between each channel and locks the unsynchronized video data of each channel and outputs the digital video data; A horizontal / vertical scaler connected to each decoder to reduce an image for split screen storage for a multi-channel input signal by using digital video data outputted from the respective video decoders; The same number of asynchronous buffers as input channels for inputting horizontal / vertical scaled image data at an arbitrary magnification through the horizontal / vertical scaler and outputting data synchronized with the main system; The read order of the asynchronous buffers is determined according to the read priority of the asynchronous buffers, and the data is read and controlled to be written to an arbitrary memory address designated for each channel in real time, thereby reading the plurality of reduced and stored split screen data into burst unit read. A memory controller that controls reading and conversion into a continuous real-time video signal, 1 frame memory for storing data by the controller, A video buffer for storing image data stored in the memory read in the discrete burst unit and continuously outputting the image data according to video timing; And a video encoder for outputting an analog composite image to the digital video input signal output from the video buffer for each broadcasting method. The method of claim 1, And an asynchronous buffer for storing the multi-channel asynchronous input signal according to each channel timing and outputting data synchronized to the main system using a FIFO of 1-line video memory or less per channel. The method of claim 1, The video controller An adaptive asynchronous buffer controller for reading data by determining the read order of the asynchronous buffers according to the read priority of the asynchronous buffers; A real-time memory controller for controlling the data read by the adaptive asynchronous buffer controller to be written to a random memory address designated for each channel in real time; And a real-time memory read controller configured to read the plurality of reduced and stored split screen data in burst units of read and convert the plurality of divided stored split screen data into a continuous real-time video signal through a video buffer.