JPH01205688A - Television receiver - Google Patents

Abstract

PURPOSE:To simplify the composition of the title device by equipping the device with a first selecting means to select only a designated channel, a second selecting means to select either one out of signals outputted from first and second speed changing memory means respectively, and a third selector to switch a high grade television signal inputted independently and a converted high grade television signal. CONSTITUTION:The device is composed of a tuner 1, an A/D converter 2, a reduction circuit 3, a delaying circuit 4, speed changing memories 5a and 5b, a PLL6, a control circuit 7, selectors 8, 10, and 12, an enlargement circuit 9, and a matrix circuit 11. Thus, all the 8 channels of the NTSC signal of a conventional television can be displayed within the picture size of a high grade television HDTV, the designated channel can be enlarged to the picture size of the HDTV and displayed on a HDTV picture, further, a HDTV signal can be displayed on the whole of the HDTV picture, and it is also possible to display the 8 channels of the NTSC signal on the right side of the HDTV picture and display only (a) channel out of the 8 channel on the left side of the HDTV picture where the (a) channel is enlarged to an arbitrary size.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a television receiver, and more particularly to a television receiver capable of displaying both NTSC signals and high-definition television signals.

[Conventional technology]

In recent years, a new television system, high-definition television (HDTV), has been introduced.
) development is becoming more active. However, 1DTV is not compatible with conventional NTSC signals in terms of aspect ratio, scanning method, etc., so when watching NTSC broadcasts, use NTSC.
When watching HDTV broadcasts on an SC TV receiver, set it to H.
A DTV receiver must be prepared. This would have two television sets. The situation is shown in FIG. 1A is a front view of the NTSC television receiver, and FIG. 1B is a front view of the Hl)TV television receiver.

Therefore, there was an urgent need to develop a device that would allow viewing both NTSC and HDTV on a single television receiver.

[Problem to be solved by the invention]

As mentioned above, the conventional method has the drawback that dedicated television receivers are required for NTSC and HDTV. Another drawback was that if you wanted to have both TV sets, you had to put two TV sets in one room, and depending on the location, you had to change the viewing location each time.

[Failure to solve the problem]

The television receiver of the present invention includes a channeler that detects all video signals of each channel from an input NTSC signal, and
A PLL that generates horizontal and vertical synchronization signals and clocks from the TSC signal, A/D conversion means that converts the video signal of each channel into a digital signal, and reduction means that reduces the digital signal to a predetermined size. , a delay means for delaying each of the outputs of the reduction circuit for display in a predetermined order; a first selection means for selecting only designated channels of the digital signal; an enlargement means for enlarging the signal output from the enlargement means to the size of a high-definition television screen; a first speed conversion memory means for storing the signal output from the enlargement means and outputting the signal at the speed of the high-definition television; second speed converting memory means for storing and reading out signals at high definition television speed; a second selection means for selectively selecting the signal output from the second speed conversion memory means; a matrix circuit for converting the signal output from the selection means into a high-definition television signal; The present invention is characterized by comprising a third selector that switches between a high-definition television signal and the converted high-definition television signal.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

This example is based on Chi-Chi 1. A/D converter 2° reduction circuit 3. Delay circuit 4. Speed conversion memo IJ5a.

5b, PLL5. Control circuit 72 selector 8, 10° 12,
Enlargement circuit 9. It is composed of a matrix circuit 11.

The N T 8 C signal is input to CHI-1 and PLL6. The tuner l performs full detection of each channel from the input signal and outputs video signals 51, 52, 53 of each channel.
Output n 1. →Usually, in the Tokyo area, the contents of signals 51, 52, 53---nl are the video signals of channels 3, 4, 6, 8, 10, and 12, respectively. It is also possible to input UHF signals to this tuner 1 and output all the video signals of several channels. Here, as an example, the above 7 channels + UH
The explanation will proceed regarding the case of F1 channel. PLL6
Then, a horizontal synchronizing signal NT-H1, a vertical synchronizing signal N'l'-V, and a clock NT-CLK= of the NTSC signal are generated using a generally known technique from the input NTSC signal, and outputted to the control circuit 7.

Each input signal 51, 52, 53---nl is A/D
Converter 2 converts digital signals 54, 55, 56---n2
, and is output to the selector 8 and the reduction circuit 3, where it is reduced by the control signal 64 from the 3 control circuit 7 by generally known digital signal processing.

As shown in FIG. 2, this reduction circuit is for displaying 8 channels of NTSC signals reduced to a reduced horizontal size x and a reduced vertical size y on an HDTV size screen. Here, x and y are arbitrary, but they will be shown below as an example. The effective screen size of HDTV is approximately 1500mm horizontally.
The sample is 1040 vertical lines, so X is, for example, 3
30 and the distance between screens is 60, then (330X4)+(60X3)=1500 is sufficient. Further, y may be set to 450, for example, and the distance between the screens may be set to 140. In this way, the reduction circuit determines the size according to X and y and reduces the size.

The delay circuit 4 converts each signal horizontally and vertically into signals 58, 59, except for the upper left channel in FIG.
After delaying n3, the arrangement as shown in Fig. 2 is decided and the signal 60.
Output 6l---n4. The delay circuit 4 can be constructed using general memory elements.

Speed conversion memo IJ5b is input signal 57.6
0.6l---n4 is written to the memory at the speed of the NTSC signal by the control signal 62 from the control circuit 7, and then
The signal is read out at the speed of the H1 TV signal by the control signal 63 and converted into an 8-channel display signal 69, which is input to one side of the selector 10.

The selector 8 selects only the channel designated by the control signal 65 from the control circuit 7 from among the input digital signals 54, 55, 56---n2 of each channel, and sends it to the expansion circuit 9 as a signal 66. Output. In the enlargement circuit 9, the signal 66 is enlarged by the full control signal 64 to the HDTV screen size using generally known digital signal processing, resulting in a signal 67. The signal 67 is input to the speed conversion memory 5a, written into the memory at the speed of the NTSC signal by the control signal 62 from the control circuit 7, and then read out at the speed of the H1) TV signal by the control signal 63, and converted into an enlarged signal 68. and is input to the other side of the selector 10.

FIG. 3 shows how the image is processed and displayed using the method described above. The selector 10 switches the input enlarged signal 68, 8-channel display signal 69, and total control signal 70, and inputs the signal 71 to the matrix circuit 11.

In the matrix circuit 11, the signal 71 is converted from the NTSC signal to 几・G・B or Y.
-Cw-CN is obtained and output as a signal 73 to the selector 12. The selector 12 selects the input HDTV signal (几・G-
B or Y・C,,C,) and signal 73'lt control circuit 7
It is arbitrarily switched by the control signal 72 from the output signal and used as an output signal. Although not shown in the figure, it goes without saying that the output signal is D/A converted, passes through a television circuit, and is displayed on a cathode ray tube.

The control circuit 7 performs horizontal synchronization N of the input N'f'SC signal.
T-H, vertical synchronization NT-V, clock NT-CL K
HDTV (no horizontal sync HD-H, vertical sync HD-V1 clock HD-CL K and HDTV/N
Control signals 62 and 63 to each part by TSC mode signal
・Generate and supply 64, 65, and 72.

As a result of the above, all 8 channels of NTSC signals can be displayed within the TV screen size (as shown in Figure 2), and the designated channels can be displayed on the IDTV screen (as shown in Figure 3). It can also be enlarged and displayed. Further, as shown in FIG. 4, full-screen HDTV signal display is also possible.

Furthermore, as shown in FIG. 5, it goes without saying that it is possible to display the NTSCs channels on the right side and enlarge only the a channel to an arbitrary size on the left side.

〔Effect of the invention〕

As explained above, according to the present invention, all channels of the conventional NTSC system can be displayed in full image on one television receiver, and the selected channel can be enlarged and displayed on a high-definition television screen size. It is possible to provide a television receiver that can also be viewed by switching to a normal high-definition television screen.

[Brief explanation of the drawing]

Figure 1 is a professional diagram of an embodiment of the present invention, Figures 2 to 5 are diagrams showing screen display states in an embodiment of the present invention, and Figure 6 is a diagram showing a screen display state in a conventional example. It is a diagram. l...Cheener, 2...A/D converter, 3...Reduction circuit, 4...Delay circuit, 5...Speed Conversion memory, 6...-PL
L, 7... Control circuit, 8, 10° 12...
...Selector, 9...Enlargement circuit, 11...
・Matrix circuit.

Claims (1)

[Claims] A tuner that detects the video signal of each channel from the input NTSC signal, a PLL that generates horizontal and vertical synchronization signals and a clock from the NTSC signal, and an A/D that converts the video signal of each channel into a digital signal.
converting means; reducing means for reducing the digital signal to a predetermined size; delay means for delaying each of the outputs of the reduction circuit for displaying in a predetermined order; a first selection means for selecting only selected channels; an enlargement means for enlarging the signal selected by the selection means to the size of a high-definition television screen; a first speed conversion memory means for reading out the signal at a speed of a high-definition television; and a second speed conversion memory means for storing the signal output from the reduction means and reading it out at a high-definition television speed;
a second selection means for selectively selecting the signal output from the first and second speed conversion memory means; a matrix circuit for converting the signal output from the selection means into a high-definition television signal; A television receiver comprising a third selector that switches between a separately input high-definition television signal and the converted high-definition television signal.