JPH01157180A - Scan converter - Google Patents

Abstract

PURPOSE:To decrease memory capacity by writing a next interlace image to a frame memory part, to which a reading is complete, or moving a raster in a line memory part to the frame memory part to which the reading is executed. CONSTITUTION:The frame memory part, which can hold the interlace image equivalent to one picture, and the line memory part, which can hold an image for one raster part, are allocated to the RAM part of a dual port memory 2. The control of the dual port memory 2 is executed by an address reading and writing control means. Then, each time one raster part is read from the frame memory part, the next interlace image is written per raster to a memory area, in which the reading is completed, or, after the next interlace image is written per raster to the line memory part, the image equivalent to one raster is read from the frame memory part and the raster in the line memory part is moved to a storing area in which the reading is executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a scan converter for converting an interlaced image into a non-interlaced image.

[Background of the invention and its problems]

Conventional scan converters are non-interlaced.
It has a memory for one image screen, and a 640 x 400 x 24 bit image requires 6 Mbit memory. Furthermore, since the scan converter needs to generate images in real time, it requires a high-speed memory IC, and a large amount of expensive memory ICs must be used.

[Purpose of the invention]

This invention was devised to solve these conventional problems, and its purpose is to provide a scan converter that can configure a circuit with about half the memory capacity of a non-interlaced image and can operate at a sufficiently high speed. shall be.

[Summary of the invention]

The scan converter according to the present invention uses a memory having a frame memory section that can hold one frame of an interlaced image and a line memory section that can hold one raster, and each time one raster is read from the frame memory section, the reading is completed. After writing the next interlaced image one raster at a time to the line memory area, or writing the next interlaced image one raster at a time to the line memory area, read the image for one raster from the frame memory area, and store the read data. This is to move the raster in the line memory section to the area.

[Embodiments of the invention]

Next, an embodiment of the scan converter according to the present invention will be described based on the drawings.

In FIG. 1, the scan converter is FIFol, dual port memory 2. Equipped with a D/A converter 3, FIF
In OI, interlaced No. 11a S is inputted and outputted on a first-in first-out basis, and an image captured at an interlaced timing is outputted at a non-interlaced timing. The image output from the FIFOI is input to the D/A converter u3 while being written to the SAM of the dual port memory. The D/A converter 3 converts the non-interlaced image into analog using the scan converter.

The RAM section of the dual port memory 2 is allocated with a frame memory section that can hold one screen worth of interlaced images and a line memory section that can hold one raster section of images. Here, the addresses for holding each raster in the frame memory section are designated as 0 to 255, and the address in the line memory section is indicated by "x".

An interlaced image is either an image consisting of odd-numbered rasters in a non-interlaced image or an image consisting of even-numbered rasters, and the control of the dual port memory differs depending on which image is output from the FIFOI. Control of the dual port memory is performed by an address, read/write control means (not shown).

Figure 2 shows the case where an interlaced image of even-numbered rasters is output from FIRFO (A) and the case where an interlaced image of odd-numbered rasters is output from FIFO (A).
B) shows the timing and address for reading and writing to and from.

Now, the even-numbered raster interlaced image is output from the FIFOI, and the 0 of the dual port memory 2 ORAM section is output.
Assuming that the interlaced image of the previous odd-numbered raster is already stored at address ~255, first
One raster image from address 0 of the section is transferred to the SAM section,
Thereafter, each pixel is sent to the D/A converter 3. followed by 0
One raster image is again transferred from the address to the SAM unit, but this is a dummy image. Next, one raster image is sent from the FIFOI pixel by pixel to the D/A converter 3, and simultaneously written to the SAM section of the dual port memory 2.

The image written to the SAM section at the following timing is RA
Transferred to address O of M. At this point, the address of the dual port memory 2 has been outputted, and then the next even-numbered raster is output from the FIFOI, and the image of that raster is stored at address 1 in the RAM section. By repeating this operation, you can generate a non-interlaced image while
It is possible to replace the image of the odd-numbered raster at addresses O to 255 in the RAM section with the image of the next even-numbered raster.

In this way, when even-numbered raster images are held in the RAM section, odd-numbered raster images are output from the FIFOI. The first raster image output from the FIFOI is sent to the D/A converter 3 and input to the QSAM section of the dual port memory 2, and the image held in the SAM section is transferred to the line memory section of the RAM. Next, the image at address 0 in the RAM section is transferred to the SAM section, and outputted pixel by pixel to the D/A converter N3. Here, the image in the line memory section is once transferred to the SAM section, and then output pixel by pixel to address 0 of the RAM section. This raster image is sent to the D/A converter, stored in the SAM section, and then transferred to the line memory section. Here, the raster of the address counter is transferred to the SAM section and output pixel by pixel, and then the image in the line memory section is transferred to the SAM section and then transferred to address 1.

By repeating this operation, it is possible to replace the even-numbered raster image at addresses O to 255 in the RAM section with the next odd-numbered raster image while generating a non-interlaced image.

As is clear from the waveform diagram in FIG. 2, the reading of the dual port memory is indicated by R. ), write (indicated by W)
R2 times and W2 times occur alternately in any raster image, and the next address is from FIFO to g
When outputting the image of the 4th raster, it is the same in one cycle of reading and writing, and when outputting the image of the odd numbered raster from FIFO, the first R and the first W are at the same address, and the second The R of the first time and the W of the second time are connected to the address of the line memory section.

Therefore, the read and write control signals can be made common to both screens, and when specifying an address, when outputting an odd-numbered raster image from the FIFO, a fixed address is used instead of the output of the address counter at the second R and W. You can use . This allows the control section that controls the dual port memory to have an extremely simple configuration.

Furthermore, data transfer between the SAM section and the RAM section is performed in units of one raster, and writing to and reading from the SAM section is performed in one clock, so the input/output speed is sufficient to generate non-interlaced images in real time. It is reasonably fast.

FIG. 3 shows a second embodiment of the present invention, in which a normal RAM 5 and a serial/parallel/serial converter 5 are used instead of the dual port memory. Conversion M
5 temporarily holds the serial output from FIFOI and then transfers it to RAM as parallel data, or
Read the data of M as parallel data and output it serially.

The combination of RAM4 and variable IJj[5 functions in the same way as a dual port memory, and addressing, reading, and writing are controlled in the same way.

〔Effect of the invention〕

As mentioned above, the scan converter according to this invention is
Using a memory that has a frame memory section that can hold one frame of an interlaced image and a line memory section that can hold one raster, each time one raster is read from the frame memory section, the next interlaced image is stored in the read memory area. After writing the image one raster at a time, or writing the next interlaced image one raster at a time to the line memory section, read the image for one raster from the frame memory section, and write the line to the Ifi area where the reading was completed 4'i. Since the rasters in the memory section are moved, the circuit has the advantage of being able to be configured with about half the memory capacity of a non-interlaced image and operating at a sufficiently high speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of a scan converter according to the present invention, FIG. 2 is a waveform diagram showing memory addresses and read/write control signals in the same embodiment, and FIG. 3 shows a second embodiment. It is a block diagram. 1...PIFo, 2...Dual port memory, 3
...D/A converter, 4...RAM, 5...serial/parallel/serial conversion base.

Claims (4)

[Claims] (1) A memory having a frame memory section that can hold one frame of an interlaced image and a line memory section that can hold one raster, and an interlaced image corresponding to an odd numbered raster in a non-interlaced image is stored in the frame memory section. When data is stored, each time an image in memory is read out in raster order, an image corresponding to the next even-numbered raster is written in the memory area that has been read out, one raster at a time in raster order. When the interlaced image corresponding to the raster is held in the frame memory section, the image corresponding to the next odd-numbered raster is
A scan converter comprising address/read/write control means for writing raster by raster into the line memory section and moving the image in the line memory section to the read memory area every time one raster of the image in the frame memory section is read out. (2) The scan converter according to claim 1, wherein the memory comprises a RAM and a serial/parallel/serial converter. (3) The scan converter according to claim 1, wherein the memory is a dual port memory. (4) When the frame memory section holds an interlaced image corresponding to an odd-numbered raster in the non-interlaced image, the address/read/write control means reads two or more of the same addresses in the frame memory section.
Repeat the operation of incrementing the address after writing twice, and if the interlaced image corresponding to the even-numbered raster in the non-interlaced image is held in the frame memory section, write the corresponding one to the line memory section and write to the frame memory section. 4. The scan converter according to claim 2, wherein the operation of incrementing the address of the frame memory is repeated after reading the frame memory, reading the line memory, and writing to the frame memory.