JPS6211380A - Converting method for picture signal - Google Patents

Converting method for picture signal

Info

Publication number
JPS6211380A
JPS6211380A JP60150811A JP15081185A JPS6211380A JP S6211380 A JPS6211380 A JP S6211380A JP 60150811 A JP60150811 A JP 60150811A JP 15081185 A JP15081185 A JP 15081185A JP S6211380 A JPS6211380 A JP S6211380A
Authority
JP
Japan
Prior art keywords
memory
image signal
interlace
noninterlace
converter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60150811A
Other languages
Japanese (ja)
Inventor
Keiichirou Katayama
圭一朗 片山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
IIZERU KK
Original Assignee
IIZERU KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by IIZERU KK filed Critical IIZERU KK
Priority to JP60150811A priority Critical patent/JPS6211380A/en
Publication of JPS6211380A publication Critical patent/JPS6211380A/en
Pending legal-status Critical Current

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  • Television Systems (AREA)

Abstract

PURPOSE:To improve the picture quality by so forming the titled method that an interlace/noninterlace picture signal is written in a memory in which picture information are writable according to their time sequences, and read out in accordance with the time sequence of either interlace/noninterlace picture signal to convert them. CONSTITUTION:A memory element M is composed of plural memory elements m1-mn. The first picture signal S1 (interlace or noninterlace) is written in the said element M via a serial-parallel converting part SP. The information is read out from the element M via a parallel-serial converting part PS< and the information is made to be the second picture information S2 (noninterlace or interlace). A write address generating part WA, a read address generating part RA are connected to the element M via a read/write exchange part EX. And the exchange part EX, according to the read/write timings, timely inputs respective addresses from the parts WA and RA in the memory M to switch between the respective pictures. In such way, the quality of the pictures is improved.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は、インターレース画像信号をノンインターレ
ース画像信号に変換し、あるいはその逆の変換を行なう
ための画像信号変換方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an image signal conversion method for converting an interlaced image signal into a non-interlaced image signal or vice versa.

〔発明の背景とその問題点〕[Background of the invention and its problems]

〔発明の目的〕 〔発明の概要〕 〔発明の実施例〕 つぎにこの発明に係る画像信号変換方法の一実施例を、
図面に基るようになっている。
[Object of the invention] [Summary of the invention] [Embodiments of the invention] Next, an embodiment of the image signal conversion method according to the invention will be described.
It is based on drawings.

第5図には画像情報を画素単位で模式的に示しであるが
(実際に報1画面分を記憶し得る。そして読書き切り換
え部Exは、各メモリー素子!111〜mf1に並列に
接続され、任意の画素のnビット情報を一度に読書きし
得る。
FIG. 5 schematically shows image information in pixel units (actually, one screen worth of information can be stored).The read/write switching unit Ex is connected in parallel to each memory element !111 to mf1. , n-bit information of any pixel can be read and written at once.

シリアル・パラレル変換部SP、パラレル・シリアル変
換部PSは画像信号がシリアルで転送される場合に有効
であり、シリアル・パラレル変換部SPにおいてシリア
ルな1言号Slをnビットパラレルの信号に変換し、逆
に、パラレル・シリアル変換部PSにおいてRビットパ
ラレル信号をシリアルな信号S2に変換する。
The serial/parallel converter SP and the parallel/serial converter PS are effective when image signals are transferred in serial, and the serial/parallel converter SP converts one serial word Sl into an n-bit parallel signal. , Conversely, the parallel-to-serial converter PS converts the R-bit parallel signal into a serial signal S2.

第3図は以上の実施例をインターレース・ノンインター
レース双方向変換に応用した例を示すものであり、画像
信号変換部の入力端子■、出力端子0(第1図、第2図
のSl、S2が表示された部分に対応)にはそれぞれA
/D変換器、D/A変換器が接続されている。ここに映
像信号はアナミグ信号であることが多く、画像信号変換
部の入力端子、出力端子にはこのようにA/D変換器、
D/A変換器が接続されることが多い。A/D変換器に
は入力側の映像信号力の映像信号をSlまたはS2に切
り換え、かつクロック切り換えスイッチSWCによって
A/D変換器、D/A変換器のクロックをCLI、Cl
3のいずれかに切り換え得る。
FIG. 3 shows an example in which the above embodiment is applied to interlace/non-interlace bidirectional conversion. (corresponding to the part where is displayed) is A.
/D converter and D/A converter are connected. Here, the video signal is often an analog signal, and the input terminal and output terminal of the image signal converter are connected to an A/D converter,
A D/A converter is often connected. The video signal on the input side of the A/D converter is switched to Sl or S2, and the clock of the A/D converter and D/A converter is switched to CLI or Cl using the clock changeover switch SWC.
It is possible to switch to any one of 3.

Slをインターレース映像信号とし、S2をノンインタ
ーレースの映像信号とし、それぞれの同期クロックをC
LI、Cl3とするとき、SlをA/D変換器に接続す
るとともに、クロックCLIをA/D変換器に人力し、
S2をD/A変換器に接続するとともにクロックCL2
をD/A変換器に入力すれば、インターレース映像信号
をノンインターレース映像信号に変換できる。またS2
をA/D変換器に接続するとともに、クロックCL2を
A/D変換器に人力し、SlをD/A変換器に接続する
とともにクロックCLIをD/A変換器に入力すれば、
ノンインターレース映像信号をインターレース映像信号
に変換し得る。すなわち、最小限の構成によりインター
レース、ノンインターレース双方向変換が可能となる。
Sl is an interlace video signal, S2 is a non-interlace video signal, and their synchronization clocks are C.
When setting LI and Cl3, connect Sl to the A/D converter, and manually input the clock CLI to the A/D converter.
Connect S2 to the D/A converter and clock CL2
By inputting this into a D/A converter, an interlaced video signal can be converted into a non-interlaced video signal. Also S2
If you connect S1 to the A/D converter, input the clock CL2 to the A/D converter, connect Sl to the D/A converter, and input the clock CLI to the D/A converter,
A non-interlaced video signal may be converted to an interlaced video signal. That is, interlace and non-interlace bidirectional conversion is possible with a minimum configuration.

〔発明の効果〕〔Effect of the invention〕

以上のようにこの発明に係る画像信号変換方法は、画像
情報を記憶し得るメモリー上に、インターレース画像信
号をその時系列に従って書込み、かつノンインターレー
ス画像信号の時系列に従ってこターレース画像信号に変
換し得るという優れた効果を有する。
As described above, the image signal conversion method according to the present invention is capable of writing an interlaced image signal in a memory that can store image information according to its time series, and converting a non-interlaced image signal into an interlaced image signal according to its time series. It has this excellent effect.

【図面の簡単な説明】[Brief explanation of the drawing]

第3図は同実施例の応用例を示すブロック図、第4図は
書込み、読出し周期を示す波形図である。 ml、m2.、、、+ mn    メモリー素子M 
             メモリーSl、S2   
       映像信号CT            
   サイクルタイム。 米31Xl −N (1) CA 手続補正書く方式) 昭和60年//月22日
FIG. 3 is a block diagram showing an application example of the embodiment, and FIG. 4 is a waveform diagram showing write and read cycles. ml, m2. ,,,+ mn memory element M
Memory Sl, S2
Video signal CT
Cycle time. US 31Xl -N (1) CA procedure amendment writing method) 1985//Month 22nd

Claims (4)

【特許請求の範囲】[Claims] (1)画像情報を記憶し得るメモリーを用意しておき、
インターレース画像信号に対応した画像情報をインター
レース画像信号の時系列に従って、前期メモリーに書込
み、ノンインターレース画像信号の時系列に従って、前
期メモリーから画像情報を読み出す、画像信号変換方法
(1) Prepare a memory that can store image information,
An image signal conversion method that writes image information corresponding to an interlaced image signal into a first-term memory according to the time series of the interlaced image signal, and reads out image information from the first-term memory according to the time series of a non-interlaced image signal.
(2)メモリーの書込みと読出しとの間に、メモリーの
サイクルタイム以上の時間差を設けることを特徴とする
、特許請求の範囲第1項記載の画像信号変換方法。
(2) The image signal conversion method according to claim 1, characterized in that a time difference greater than the memory cycle time is provided between memory writing and reading.
(3)画像情報を記録し得るメモリーを用意しておき、
ノンインターレース画像信号に対応した画像情報を、ノ
ンインターレース画像信号の時系列に従って前期メモリ
ーに書込み、インターレース画像信号の時系列に従って
、前期メモリーから画像情報を読み出す画像信号変換方
法。
(3) Prepare memory that can record image information,
An image signal conversion method that writes image information corresponding to a non-interlaced image signal into a first-term memory according to the time series of the non-interlaced image signal, and reads out image information from the first-term memory according to the time series of the interlaced image signal.
(4)メモリーの書込みと読出しとの間に、メモリーの
サイクルタイム以上の時間差を設けることを特徴とする
、特許請求の範囲第3項記載の画像信号変換方法。
(4) The image signal conversion method according to claim 3, characterized in that a time difference greater than the cycle time of the memory is provided between writing and reading of the memory.
JP60150811A 1985-07-09 1985-07-09 Converting method for picture signal Pending JPS6211380A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60150811A JPS6211380A (en) 1985-07-09 1985-07-09 Converting method for picture signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60150811A JPS6211380A (en) 1985-07-09 1985-07-09 Converting method for picture signal

Publications (1)

Publication Number Publication Date
JPS6211380A true JPS6211380A (en) 1987-01-20

Family

ID=15504933

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60150811A Pending JPS6211380A (en) 1985-07-09 1985-07-09 Converting method for picture signal

Country Status (1)

Country Link
JP (1) JPS6211380A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63250688A (en) * 1987-03-27 1988-10-18 インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン Display adaptor
JPH01169492A (en) * 1987-05-29 1989-07-04 Commodore Electron Ltd Highly resolving video output frame generation system
JPH07282006A (en) * 1994-04-14 1995-10-27 Bandai Co Ltd Character message communication device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63250688A (en) * 1987-03-27 1988-10-18 インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン Display adaptor
JPH01169492A (en) * 1987-05-29 1989-07-04 Commodore Electron Ltd Highly resolving video output frame generation system
JPH07282006A (en) * 1994-04-14 1995-10-27 Bandai Co Ltd Character message communication device

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