JPH02254883A - Non-interlace reduced display converter - Google Patents

Abstract

PURPOSE:To obtain a clear reduced picture by writing/reading the picture data of input picture signals into a memory without thinning them, and reduction- displaying them. CONSTITUTION:First and second field memory parts 1 and 2 receives digital input picture signals 10 in an interlace system respectively, writes or reads the signals according to switching signals 101 and 102 from a memory control part 3, when either one of the parts 1 or 2 writes the signals, the other reads them, and thus the switching signals 101 and 102 controls the first and second field memory parts 1 and 2 so as to alternately write or read the signals at every field. When picture signals (a), (b), (c),... of read output picture signals 11 are successively displayed in the 1/2 horizontal scanning cycle of the input picture signals, the picture signals for one field can be displayed in the upper half part of the display screen, and the picture reduced to half in the longitudinal direction can be obtained.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a non-interlace reduction display converter, and particularly to a non-interlace reduction display converter that converts an interlaced television image signal to a non-interlaced one and reduces and displays it. Relating to an interlaced reduction display converter.

[Conventional technology]

Generally, when converting an interlaced television image signal to a non-interlaced television image signal, the digitalized image signal is written into a memory and read-out is controlled.

Since the number of horizontal scanning lines in one field in the interlaced system is half of the number of horizontal scanning lines in one frame,
In order to convert to a non-interlaced format and display an image, the number of horizontal scanning lines in one frame during the vertical scanning period of one field in the interlaced format is twice the number of horizontal scanning lines in one field. The image signal must be read out. Therefore, the horizontal scanning period of the non-interlaced method is reduced to half that of the interlaced method to increase the scanning speed, and when reading the image signal from the memory, the horizontal scanning period is The same image signal is read out twice in succession and displayed as an image.

When displaying a displayed image vertically reduced to 1/2, when writing the input image signal to memory, the horizontal scanning lines for one field are further thinned out to 1/2, then written and read. When outputting the image, the same image signal is read out twice for each horizontal scanning line in the same way as when the image is not reduced, thereby obtaining a non-interlaced image reduced in half in the vertical direction.

[Problem to be solved by the invention]

In the conventional non-interlace reduction display converter mentioned above,
If you want to reduce the display image to half in the vertical direction, when writing the input image signal to memory, thin out the horizontal scanning lines for one field so that they are further reduced to half. This has the disadvantage that the amount of image data is small and clear reduced images cannot be obtained.

SUMMARY OF THE INVENTION An object of the present invention is to provide a non-interlaced reduction display converter that eliminates the drawbacks of the prior art by writing and reading an input image signal into a memory without thinning it out.

[Means to solve the problem]

The non-interlaced reduction display converter of the present invention writes an interlaced input image signal to a memory field by field, reads out the written image signal from the memory, and converts it into a non-interlaced output image signal. In a non-interlaced reduction display converter that reduces a display image to half in the vertical direction, the input image signal for one field of the interlaced method is sequentially processed without being thinned out at the same period as the horizontal scanning period of the input image signal. The image forming apparatus includes a writing means for writing into the memory, and a reading means for sequentially reading out the image signals written by the writing means from the memory at a period of one half of the horizontal scanning period.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a non-interlaced reduction display converter of the present invention. In the figure, the non-interlaced reduction/display converter converts one of the input image signals 10
A first field memory section 1 and a second field memory section 2 that store image signals for fields, and a synchronization signal 12 separated from an interlaced television signal to control the field memory section. It is composed of a memory control section 3 that generates and outputs signals.

A first field memory section 1 and a second field memory section 2 each receive a digitized interlaced input image signal 10, and perform writing or reading according to switching signals 101 and 102 from a memory control section 3. When either one is writing, the other is reading, and a switching signal is sent so that the first and second field memory sections 1-2 alternately write or read for each field. 101 and 102.

The field memory unit that performs a write operation sets a write address according to a write address synchronization signal 103 and writes the input image signal 10 into the memory.

Further, the field memory section that performs the read operation sets a subsequent address in accordance with the read address synchronization signal 104, reads the image signal from the memory, and outputs the output image signal 11.

FIG. 2 is a time chart showing signal timing for explaining the operation of the non-interlaced reduction display converter of the present invention. In the figure, an input image signal 10 indicates image signals a, b, c, etc. for each scanning period of each horizontal scanning line, and a write address synchronization signal 103 indicates that the input image signal 10 is stored in a memory. This shows a synchronization signal that sets the address for writing to. Further, the successive address synchronization signal 104 indicates a synchronization signal for setting an address for reading out an image signal from the memory for each horizontal scanning line, and
The output image signal 11 is the image signal a of the input image signal 10,
The states of the output image signals corresponding to b, c, . . . are shown, respectively.

When writing input image signal 10 to memory, switching signal 10
The field memory unit instructed to write by 1 and 102 sets a write address for each horizontal scanning line in accordance with a write address synchronization signal 103, and sequentially writes the input image signal 10 to the memory.

When reading the image signal from the memory, the switching signal 101.1
The field memory unit, which is instructed to read by 02, sets a read address for each horizontal scanning line in response to a read address synchronization signal 104, and sequentially reads image signals from the memory.

In this case, the same image signal is not read twice in succession as in the conventional case, but is read out sequentially while setting a read address for each horizontal scanning line as shown in the output image signal 11.

The image signals a, b, c, . . . of the output image signal 11 read out in this way are
If the image signal is sequentially displayed at 1/2, one field's worth of image signals can be displayed in the upper half of the display screen, resulting in an image reduced to 1/2 in the vertical direction.

Note that if the period of the read address synchronization signal 104 is doubled to make it the same as the period of the write address synchronization signal 103,
It is possible to display normal, unreduced images.

〔Effect of the invention〕

As explained above, according to the non-increment reduction display converter of the present invention, the image data of the input image signal is written to and read out from the memory and displayed in a reduced size without being thinned out, so that a clear reduced image can be obtained. .

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the non-increment reduction display converter of the present invention, and FIG. 2 is a time chart showing signal timing for explaining the operation. DESCRIPTION OF SYMBOLS 1... First field memory section, 2... First field memory section, 3... Memory control section, 10...
Input image signal, 11... Output image signal, 12... Synchronization signal, 101.102... Switching signal, 103...
Write address synchronization signal, 104... Read address synchronization signal.

Claims (1)

[Claims] Writes an interlaced input image signal to the memory field by field, reads the written image signal from the memory, converts it to a non-interlaced output image signal, and reduces the displayed image to half in the vertical direction. In the non-interlaced reduction display converter, one of the interlaced methods is used.
writing means for sequentially writing input image signals for fields into the memory without thinning out at the same period as the horizontal scanning period of the input image signal; A non-interlaced reduction display converter comprising: reading means for sequentially reading data from the memory at a cycle of 1/1.