JPH06149194A - Image display device - Google Patents

Abstract

PURPOSE:To accurately display image data from the outside in the state of maintaining high horizontal resolution by reading out line data at every one scanning line from an image storage part at a higher frequency than a write frequency and inserting interpolation line data into between mutual line data at every a fixed period. CONSTITUTION:An inputted image signal (a) is converted into digital image data by a reference clock signal (b) and written in the image storage part 5. The image data stored in the image storage part 5 are read out as the line data at every one scanning line by a display clock signal faster than the reference clock signal (b). Then, the same line data are read out as the interpolation line data whenever the fixed number of line data are read out, and are inserted into between mutual line data and displayed. Then, the number of scanning lines existing in a vertical synchronizing interval is increased in pseudo. Thus, the aspect ratio of respective pixels displayed are set to 1:1 in the state that the high horizontal resolution is maintained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display apparatus for temporarily storing an input image signal in an image storage unit, reading it from the image storage unit, and displaying it two-dimensionally on a display unit.

[0002]

2. Description of the Related Art Currently, NT is the commercial TV signal system.
The SC method, the PAL method, and the SECAM method are adopted. As is well known, this TV signal is a composite signal including not only an image signal but also a vertical synchronizing signal and a horizontal synchronizing signal.

In recent years, after converting the analog image signal into digital image data and temporarily storing it in an image storage unit, the image data is read from the image storage unit and displayed two-dimensionally on a display unit such as a CRT display device. Display devices have been proposed. As described above, once the image data is stored in the image storage unit, various image processing is performed on the stored image data under the control of, for example, an external computer, and then a CRT display device as a processed composite image. It is possible to display.

The horizontal resolution of the display screen in this case is determined by the number of pixels of line data forming one scanning line, that is, the sampling frequency corresponding to the number of samplings in one horizontal synchronizing period.

For example, in an NTSC system TV signal having 525 scanning lines, the number of effective scanning lines is 480, and as shown in FIG. 8A, the aspect ratio of the display screen is 3: 4. Therefore, in order to satisfy the condition that the aspect ratio of one pixel is 1: 1, the number of effective pixels in the horizontal direction is 640.

In theory, the horizontal resolution increases as the number of pixels in the horizontal direction increases, but in the NTSC system, the maximum number of pixels in the horizontal direction is 720 due to the limitation of the frequency bandwidth. Therefore, the number of pixels in the horizontal direction is 7
If you set the sampling frequency to 20,
The horizontal resolution has the highest value.

[0007]

As described above, NT
According to the SC method, since the number of effective scanning lines is 480, as shown in FIG. 8B, the number of pixels in the horizontal direction is 720.
When set to individual pieces, one screen is composed of 720 × 480 pixels.

However, the ratio of 480: 720 does not become 3: 4 which is the aspect ratio of the display screen. As a result, when these 720 × 480 pixels are displayed on a 3: 4 display screen, the aspect ratio of one pixel is 1: 0.87. Thus, if the aspect ratio of each pixel is not 1: 1, T
When a circular image created by an external computer or the like is overlaid on the circular image displayed by the V signal, the overlaid circle is transformed into an ellipse. Therefore, the image of the TV signal and the image created by the computer cannot be displayed at the same time. Of course, the computer-generated image cannot be displayed correctly.

The present invention has been made in view of the above circumstances, and reads line data for each scanning line at a frequency higher than the writing frequency from the image storage unit, and at the same time, interpolates line data at fixed intervals. It is an object of the present invention to provide an image display device capable of accurately displaying image data from the outside while maintaining a high horizontal resolution by inserting line data between each other.

[0010]

In order to solve the above-mentioned problems, according to the present invention, an image signal inputted from the outside is once stored in an image storage unit, then read out from this image storage unit and displayed on a display unit. In the image display device,

Image signal processing means for sampling an input image signal with a reference clock signal to convert it into digital image data, and writing control means for writing this digital image data in an image storage section in synchronization with the reference clock signal. And in synchronization with the display clock signal faster than the reference clock signal,
Pixel data reading means for reading line data consisting of pixel data for each scanning line from the image storage section, interpolation data reading means for reading the same line data as interpolation line data every time a fixed number of line data is read, and pixels Display control means for inserting interpolated line data between the line data sequentially read by the data reading means at a constant period and displaying the data on the display unit.

[0012]

In the thus constructed image display device, the input image signal is converted into digital image data by the reference clock signal and written in the image storage section. Therefore, when the image signal is a TV signal, the image data for one screen is stored in the image storage unit within one vertical synchronization period.

The image data stored in the image storage unit has a display clock signal which is faster than the reference clock signal.
It is read as line data for each scanning. in this case,
Since the reading frequency is higher than the writing frequency, when one screen of image data is read at this speed, there is a vacant time within the vertical synchronization period. Therefore, every time a fixed number of line data is read, the same line data is read as interpolated line data and displayed between the line data.

With such a configuration, the number of scanning lines existing in a pseudo vertical synchronization period increases. Therefore,
For example, even if the frequency of the reference clock signal when converting an image signal into digital image data is set higher than the frequency (number of pixels in the horizontal direction) determined by the aspect ratio of the display screen and the specified number of scanning lines, The ratio can be maintained at 1: 1. Therefore, an image input from the outside such as a computer can be accurately displayed while maintaining a high horizontal resolution.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic diagram showing a schematic configuration of the entire image display apparatus of the embodiment, and FIG. 2 is a detailed circuit block diagram. In this embodiment, a case where an NTSC color TV signal is color-displayed on a display unit such as a CRT display device will be described.

In FIG. 1, an NTSC TV signal a as an image signal input from the outside is input to the image signal processing unit 1. The TV signal a input to the image signal processing unit 1 is separated into a luminance signal Y and a color image signal C by the Y / C separation circuit 1a. The luminance signal Y is input to the sync separation circuit 1b. This sync separation circuit 1b has a luminance signal Y.
A vertical synchronizing signal V and a horizontal synchronizing signal H are extracted from The extracted horizontal synchronizing signal H is input to the PLL circuit 1c. The PLL circuit 1c outputs a reference clock signal b synchronized with the input horizontal synchronizing signal H.

When a horizontal effective pixel is sampled at the frequency f _S of the reference clock signal b, it becomes 720 pixels,
It is a value that can obtain the maximum horizontal resolution in the above-mentioned NTSC system. The reference clock signal b output from the PLL circuit 1c is input to the write control unit 2 and also applied to the clock terminal of the A / D converter 1d.

The color image signal C output from the Y / C separation circuit 1a is converted into image signals R, G,
Signal processing units 4a, 4b,
4c is input. Each signal processing unit 4a, 4b. Since 4c has the same configuration, here, the red (R) signal processing unit 4a is used.
Will be described only.

The red image signal R input to the signal processor 4a
Is sampled by the A / D converter 1d at the frequency f _S of the reference clock signal b described above, converted into digital image data composed of a plurality of bits, and input to the next image storage unit 5.

In the image storage unit 5, as shown in FIG.
An odd-numbered memory 5a for storing each odd-numbered line data consisting of 720 pixel data respectively constituting each odd-numbered scanning line on the display screen of the display unit 6 and each even-numbered line constituting each even-numbered scanning line It is composed of an even-numbered memory 5b for storing data, and an interpolation memory 5c for storing line data at fixed intervals among the line data read from the memories 5a, 5b as interpolation line data.

The write control unit 2 is supplied with the vertical synchronizing signal V, the horizontal synchronizing signal H, and the reference clock signal b of the frequency f _S output from the sync separating circuit 1b. When the first line of effective pixel data is input and then the first horizontal synchronizing signal H is input, the write control unit 2 outputs the digital image data output from the A / D converter 1d to the odd number memory 5
Start writing to a. Then, when the effective pixel data of the second line is input, the digital image data is transferred to the even memory 5b.
Start writing to. When writing each pixel data to each of the memories 5a and 5b, the address is not designated for each pixel data, and the pixel data is written in the input order.

That is, each of the 240 line data belonging to the odd number of the 480 line data consisting of 720 pixel data forming each of the 480 effective scanning lines forming one screen is the odd number memory 5a. Each of the 240 line data belonging to the even number is stored in the even number memory 5b.

As shown in FIG. 1, the readout display unit 6 has a display frequency f higher than the frequency f _S of the reference clock signal b.
A display clock generator 6a for outputting a display clock signal d having _D, and a sync signal generator for outputting a horizontal sync signal Ha and a clock signal for display in synchronization with the vertical sync signal V output from the sync separation circuit 1b. The circuit 6b, a read control unit 6c for reading the image data stored in the image storage unit 5, and a D / A converter 6d for converting each read line data into each analog run signal e are basically included. Is configured.

Display frequency f _D of the display clock signal d
Is determined by the following procedure. As described above, each line data stored in the image storage unit 5 is composed of 720 pixel data. In order to display this pixel data on a display screen having an aspect ratio of 3: 4 with an aspect ratio of 1: 1 for each pixel, it is necessary to set the number of vertical scanning lines to 585. The effective number of scanning lines with respect to the number of 585 scanning lines is 540, as shown in FIG.

Since the period T _V (= 60 Hz) of the vertical synchronizing signal V is unchanged, the period T _Ha of the horizontal synchronizing signal Ha for displaying an image in the state shown in FIG. 3 is the horizontal pottery of the input TV signal a. Compared to the period T _{H of the} signal H, it is 525/585 times shorter. 72 for one line within the effective display period of this cycle T _Ha
In order to read 0 pixel data, the display frequency f _D of the display clock signal d becomes the frequency corresponding to the cycle obtained by dividing the effective display period by 720.

Further, in the actual circuit, in addition to the circuits 6a to 6d described above, as shown in FIG. 2, the display clock signal d output from the display clock generator 6a is set to 1
It is composed of a frequency divider 6e that divides the frequency by 2/2, a changeover switch 6f, an interpolation memory control section 6g that performs write / read control for the interpolation memory 5c, an output switching section 6h, and a spatial filter 6i.

Next, in the case of performing interlace display in which line data is read from the two memories 5a and 5b of the odd number memory 5a and the even number memory 5b shown in FIG. The operation of the read display unit 6 will be described.

When performing interlace display, the changeover switch 6f is connected to the frequency divider 6e side. Therefore, the display clock signal d1 obtained by dividing the display frequency f _D into 1/2 is input to the synchronizing signal generator 6b. In this case, the frequency of the horizontal synchronizing signal Ha is also divided into 1/2.

The read controller 6c sequentially reads line data from the odd number memory 5a and the even number memory 5b for each display screen. For example, for the odd-numbered memory 5a, FIG.
As shown in, each time the horizontal synchronizing signal Ha is input, the 1, 3, 5, ... Line data are sequentially read in the writing order. Then, when the eighth odd line data, that is, the fifteenth line data counted from the entire line data is read, a control signal is sent to the interpolation memory control unit 6g and read to the interpolation memory 5c. The th line data is written as interpolation line data.

Then, at the time when the next horizontal synchronizing signal Ha is input, the interpolation memory 5
The same interpolated line data as the fifteenth line data written in the previous horizontal synchronization period to c is read. This switching control is performed by the output switching unit 6h. Therefore, FIG.
As shown in (a), in the frame displayed on the display unit 7, the same interpolation line data is inserted after the 15th line data.

The interpolation line data insertion processing is performed once every eight scanning lines, that is, at nine scanning cycles. Therefore, 270 line data is generated by performing 30 times on one screen.

Similarly, when the next one display screen is created, the 2.4.6 ... th line data are sequentially read from the even-numbered memory 5b. Then, as in the case of the odd-numbered memory 5a, as shown in FIG. 4B, the interpolation line data insertion processing is performed in 9 scanning cycles.

The reason for providing the interpolation memory 5c is as follows. That is, as described above, the odd memory 5a
The image data is written in the even-numbered memory 5b in order without specifying an address, and is similarly read in the written order. That is, since the read start address cannot be specified in the memories 5a and 5b, the same line data cannot be repeatedly read. Therefore, the once read line data is stored and held for one horizontal cycle period in the interpolation memory 5c for reading again.

Each line data read by the format shown in FIGS. 4 (a) and 4 (b) is subjected to a smoothing process between the interpolation line data and the next line data in the spatial filter 6i. After that, in the D / A converter 6, it is converted into an analog line signal e, and the display unit 7
Sent to. Since the images of the odd frames of FIG. 4A and the even frames of FIG. 4B are alternately displayed on the display unit 7, the number of scanning lines is 540.

Next, when performing a non-interlace display for displaying a still image or the like, the changeover switch 6f is connected to the display clock generating section 6a side. Therefore, the display clock signal d having the display frequency f _D is input to the synchronization signal generator 6b. In this case, the read controller 6c uses the horizontal sync signal H from the odd-numbered memory 5a and the even-numbered memory 5b at a display frequency f _D that is twice as high as that in the case of interlaced display.
Every time a is input, the odd line data and the even line data are alternately read to create the frame shown in FIG.

In this case, similarly to the case of the interlace display, the interpolation line data insertion processing is carried out at 9 scanning cycles. Therefore, 60 interpolation line data are inserted in one frame, and the number of 480 scanning lines of the input TV signal a is pseudo-converted into the number of 540 scanning lines.

According to the image display device having such a configuration, the number of 480 scanning lines of the input TV signal a is pseudo 5
Since the number of scanning lines is converted to 40, the horizontal resolution is NT.
When the limit horizontal resolution of the SC system is set to 720 pixels, the ratio of the number of pixels in the vertical direction and the number of pixels in the horizontal direction of one screen is 540: 720 = 3: 4. Therefore, the aspect ratio of one pixel is 1: 1.

Therefore, for example, even if the image data input from an external computer or the like is displayed on the display unit 7, it is displayed in a correct shape. Further, even when the image data input from the computer or the like is displayed on the image by the TV signal, the image data is displayed correctly.

Further, in the apparatus of the embodiment, a 1: 1 image can be displayed while performing interlaced display on a moving image and no interlaced display on a still image and maintaining a high horizontal resolution.

FIG. 6 is a block diagram showing a schematic structure of an image display device according to another embodiment of the present invention. The same parts as those in the embodiment shown in FIG. 2 are designated by the same reference numerals. Therefore, detailed description of the overlapping portions is omitted.

In this embodiment, for example, red (R) digital image data output from the coder 1e is converted into parallel data by the serial / parallel conversion circuit 1f.
The parallel data is sent to the write terminal DI of the multiport memory 5d. The multi-port memory 5d has two data terminals as shown in the figure. In this embodiment, one terminal is set as the write terminal DI and the other terminal is set as the read terminal DO. The data writing process and the data reading process can be executed independently of each other. Since this multi-port memory 5d is composed of DRAM, it is provided with a memory refresh controller 5e for holding the stored contents.

In the process of writing the image data to the multiport memory 5d, the image data is sequentially written while the write control unit 2 specifies the write address AI. Similarly,
When the written image data is read line by line, the read control unit 6c reads the read address AO.

In this case, the image data can be read by designating an arbitrary address. Therefore, FIG.
In order to obtain the no-interlace display format shown in, the same line data is easily read as interpolation line data by re-designating the address in the multiport memory 5d every 9 scanning line periods. The interpolated line data that can be output is inserted into the normal line data mutual intervals, and as shown in FIG. 5, each line data of 540 scanning lines forms one screen.

It should be noted that the writing speed of the address-specified image data for the multi-port memory 5d constituted by this RAM is slower than the writing speed for each of the memories 5a, 5b not specifying the address shown in FIG. So
The digital image data is converted into parallel data in advance by the serial / parallel conversion circuit 1f to reduce the speed.

In the image display device thus constructed, the number of effective scanning lines of the input TV signal a can be pseudo-converted from 480 to 540 as in the embodiment shown in FIG. Therefore, it is possible to obtain substantially the same effect as that of the embodiment shown in FIG.

Further, in this embodiment, since the image data is written in the multiport memory 5d by designating the address, the interpolation memory 5c, the interpolation memory control section 6g, and the output switching section 6h shown in FIG. Since it can be removed, the configuration of the entire device can be simplified. FIG. 7 is a block diagram showing a schematic configuration of an image display device according to still another embodiment of the present invention. The same parts as those in the embodiment shown in FIG. 6 are designated by the same reference numerals. Therefore, detailed description of the overlapping portions is omitted.

In this embodiment, a function of superimposing a graphic created by the personal computer 8 on the display device 7 is incorporated. The image data showing a figure created by the personal computer 8 is the interface circuit 8
With a, it is converted into image data in the format of 720 × 540. The image data for one screen output from the interface circuit 8a is once written in the image memory 8b in the signal processing unit 4a.

As the data transmission system from the personal computer 8 to the interface circuit 8a, the SCSI system is adopted in the embodiment, but it is not particularly limited to the SCSI system.

The image data written in the graphic memory 8b is read from the graphic memory 8b in synchronization with the read timing for the multiport memory 5d and sent to the switching terminal of the output switching circuit 8c. Output switching circuit 8c
The image data read from the malport memory 5d and the brightness level data set in the register 8d are input to the.

The output switching circuit 8c reads 720.times.540 binarized pixel data which are sequentially input from the graphic memory 8b to the switching terminals, and in the case of [0], the image from the malport memory 5d. Data is output, and in the case of [1], the signal value of the brightness level data set in the register 8d is output.

Therefore, on one display screen, the graphic portion created by the personal computer 8 is displayed with the brightness set in the register 8, and the area other than the graphic portion is the image data output from the multiport memory 5d. Is displayed. In other words, on the display screen of the display unit 7, the graphic created by the personal computer 8 is displayed overlaid on the image of the TV signal.

Here, since each pixel of the figure created by the personal computer 8 is displayed on the screen set so that the aspect ratio is 1: 1 on the display screen, it is created by the personal computer 8. The figure is displayed correctly without any deformation. In this way, a computer-generated figure can be displayed accurately while maintaining the maximum horizontal resolution 720 of the NTSC system.

[0054]

As described above, according to the image display apparatus of the present invention, each line data for each scanning line is sequentially read from the image storage unit at a frequency higher than the writing frequency, and the interpolation line data is also read. Is inserted between the line data at regular intervals to increase the number of scanning lines of the input signal in a pseudo manner. Therefore, the aspect ratio of each pixel to be displayed can be set to 1: 1 while maintaining a high horizontal resolution, and image data supplied from the outside such as a computer can be accurately displayed.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing a basic structure of an image display device according to an embodiment of the present invention,

FIG. 2 is a detailed block diagram of the apparatus of the embodiment,

FIG. 3 is a diagram showing a display frame in the apparatus of the embodiment,

FIG. 4 is a diagram showing a procedure of inserting interpolated interpolation line data in the apparatus of the embodiment;

FIG. 5 is a diagram showing a procedure of inserting interpolation line data of a no-interlace method in the apparatus of the embodiment.

FIG. 6 is a block diagram showing an image display device according to another embodiment of the present invention,

FIG. 7 is a block diagram showing an image display device according to still another embodiment of the present invention,

FIG. 8 is a display frame diagram for explaining problems of the conventional image display device.

[Explanation of symbols]

1 ... Image signal processing unit, 1a ... Y / C separation circuit, 1b ... Synchronous separation circuit, 1e ... Decoder, 1d ... A / D converter, 2
... Writing controller, 4a, 4b. 4c ... Signal processing unit, 5 ... Image storage unit, 5a ... Odd memory, 5b ... Even memory, 5c
... interpolation memory, 5d ... multi-port memory, 6 ... read display section, 6a ... display clock generation section, 6b ... synchronization signal generation section, 6c ... read control section, 6d ... D / A converter, 6i ... spatial filter, 7 ... Display unit, 8 ... Personal computer, 8b ... Graphic memory.

Claims (1)

[Claims] 1. An image display device for storing an image signal input from the outside in an image storage unit, and then reading the image signal from the image storage unit and displaying the image signal on a display unit, wherein the input image signal is a reference clock signal. An image signal processing means for sampling the digital image data into digital image data, a writing control means for writing the digital image data to the image storage section in synchronization with the reference clock signal, and a display clock faster than the reference clock signal. In synchronization with the signal, a pixel data reading means for reading line data consisting of pixel data for each scanning line from the image storage section, and the same line data for every fixed number of line data reading as interpolated line data. The interpolation line data is fixed between the interpolation data reading unit and each line data sequentially read by the pixel data reading unit. The image display apparatus and a display control means for displaying on the display unit insert with the period.