JPH1013710A - Display method and its device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make image distortion based on a time difference due to interlace scanning inconspicuous by generating a new intermediate frame image and inserting the image between original frames. SOLUTION: Sampling data (A) in odd number and even number fields form one frame, a new intermediate frame image is generated from sampling data of adjacent odd number fields and sampling data of adjacent even number fields and the image is inserted between original frame images. An odd number field O1 and an even number field E1 of a 1st frame are synthesized to generate display data O1/E1 of the 1st frame. Then an odd number field O2 and an even number field E1 of a 2nd frame are synthesized to generate display data O2/E1 of a new intermediate frame. Thus, new intermediate frame images O2/E1., O3/E2,... are inserted by outputting the display data obtained one after another at an interval of 16.6ms and image distortion is principally halved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display method and an apparatus for displaying an image composed of interlaced video signals such as NTSC television signals on a screen, and more particularly to an object and a pattern displayed on the screen. The present invention relates to a display method and a display device in which distortion of an image is not noticeable even when the movement is fast.

[0002]

2. Description of the Related Art For example, taking an NTSC television signal as an example, as shown in FIG. 7, 525 scanning lines are scanned twice every other line, and one screen is displayed on two screens of an odd field and an even field. A so-called interlaced scanning which forms a frame is performed. In the case of the NTSC system, the frame frequency is 30 Hz (30 frames / second), the field frequency is 60 Hz.
(60 sheets / second). Therefore, the interval between frame images is 33.3 ms, and the interval between field images is 16.6 m.
s.

FIG. 8 shows a conventional display device for such interlaced video signals. In the figure, reference numeral 51 denotes a first frame memory, and 52 denotes a second frame memory. The operation of the display device of FIG. 8 will be described with reference to the operation explanatory diagram of FIG. The symbol O in FIG. 9 indicates an odd field (ODD), and E indicates an even field (EVEN). The numbers 1, 2,... Added to the field symbols O, E indicate frame numbers. For example, O1 indicates an odd field of the first frame, E1
1 means an even field of the first frame.

When the sampling data (video signal) as shown in FIG. 9A is input to the display device, the first frame memory 51 is stored in the first frame memory 51 as shown in FIG. 9B. Odd frame sampling data (O1 / E
1), (O3 / E3), (O5 / E5),... Are sequentially stored every other frame.
Shows the sampling data (O2 / E) of the even frame.
2), (O4 / E4), (O6 / E6),... Are sequentially stored every other frame.

When the sampling data of the odd frame is written in the first frame memory 51, the sampling data of the even frame is read from the second frame memory 52, and the second frame memory 52 is read. When the sampling data of the even frame is written in the first frame memory 51, the sampling data of the odd frame is read from the first frame memory 51. As a result, the display data as shown in FIG.
Output one after another at intervals.

[0006]

However, there is a time difference of 16.6 ms between the odd field and the even field. For this reason, when an object or design existing on the screen moves, image distortion due to the time difference of the interlaced scanning occurs in the frame image obtained by combining the odd field and the even field as shown in FIG. This image distortion increases as the movement of the object or the design moves faster. Since the display screen is updated one after another every 33.3 ms (one frame), if the object or the symbol continues to move as it is,
The image distortion due to the time difference between the odd field and the even field is also maintained as it is, and there is a problem that the portion where the image distortion occurs looks jagged as shown in FIG.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem. It is an object of the present invention to provide a method for detecting a time difference caused by interlaced scanning even when an object or a pattern displayed on a screen is moving quickly. It is an object of the present invention to provide a display method and an image display apparatus in which image distortion based on the image is made inconspicuous.

[0008]

In order to solve the above problems, the present invention employs the following means. That is,
The invention according to claim 1 is a display method for displaying an image composed of a video signal of an interlaced scanning method on a screen, wherein an odd-numbered field image in one frame image of adjacent frame images and an odd field image in the other frame image are displayed. A new intermediate frame image is created using the even-numbered field image, and the created intermediate frame image is inserted between the adjacent original frame images.

In such a configuration, a newly created intermediate image is inserted between the original frame images.
The motion is smoother than that of the display image consisting of only the original frame image, and even if the object or the design moves at high speed during the display screen, large image distortion unlike the related art does not occur.

According to a second aspect of the present invention, there is provided a display device for displaying an image composed of video signals of the interlaced scanning method on a screen, comprising two memories for storing video signals of odd fields, and two memories for storing video signals of even fields. It comprises two memories for storing video signals, and a memory control circuit for controlling writing and reading of video signals to and from each of the memories, wherein the memory control circuit is used when writing a video signal to any of the memories. By reading the video signal stored in the other memory, a new intermediate frame image is obtained from the video signal of the odd field in one frame image and the video signal of the even field in the other frame image in the adjacent frame images. Display data is created, and the display data of the created intermediate frame image is compared with the display data of the adjacent original frame image. It is characterized in that the controls to insert and output.

With this configuration, it is possible to obtain a display device whose motion is smoother than that of a display image consisting of only the original frame image.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram illustrating the principle of the method of the present invention. FIG. 1A shows input sampling data (video signal), and FIG. 1B shows display data created by the method of the present invention. The sampling data constitutes one frame of the odd field and the even field. According to the method of the present invention, a new intermediate frame image is created from the sampling data of the adjacent odd field and the sampling data of the even field. Is inserted between the original frame images.

That is, the odd fields O1, O2, O
, And sampling data composed of even fields E1, E2, E3,..., As shown in FIG.
If they are sent alternately at 16.6 ms intervals,
First, the odd field O1 and the even field E1 of the first frame are synthesized, and as shown in FIG.
The display data (O1 / E1) of the frame is created. Next, the odd field O2 of the second frame and the even field E1 of the first frame are combined, and as shown in FIG. 1B, display data (O2 / E1) of a new intermediate frame.
Create

Similarly, the odd field O2 of the second frame and the even field E2 of the second frame are combined to create the original display data (O2 / E2) of the second frame. Further, the odd field O3 of the third frame and the even field E2 of the second frame are combined to create new intermediate frame display data (O3 / E2). Further, the odd field O3 of the third frame and the even field E3 of the third frame are combined to create the original display data (O3 / E3) of the third frame. Further, the odd field O4 (not shown) of the fourth frame and the even field E3 of the third frame are combined to create new intermediate frame display data (O4 / E3).

If the display data thus obtained are output one after another at intervals of 16.6 ms, the display data shown in FIG.
As shown in (B), (O1 / E1), (O2 / E1)
1), (O2 / E2), (O3 / E2), (O3 / E
3), (O4 / E3),..., A series of display data sequentially output is obtained. As is apparent from the display data shown in FIG. 1B, the original frame images (O1 / E1), (O2 / E2), (O3 / E3),.
, A newly created intermediate frame image (O2 / E
1), (O3 / E2), (O4 / E3),... Are inserted. For this reason, the image distortion is halved in principle compared to the display image consisting of only the original frame image, and the portion where the image distortion has occurred does not look jagged as in the related art. .

FIG. 2 is a block diagram showing the basic configuration of the apparatus of the present invention configured by applying the method of the present invention. In the figure, 1 is a first memory for odd fields (ODD1 memory), 2 is a second memory for odd fields (ODD2 memory), 3 is a first memory for even fields (EVEN1 memory), and 4 is a second memory for even fields. (EVEN2
Memory) and 5 are memory control units. Each memory 1
4 have a memory capacity capable of storing image data for at least one field.

The operation of the circuit of FIG. 2 will be described with reference to the operation explanatory diagram of FIG. Now, for memories 1 to 4,
When the sampling data (video signal) shown in FIG. 3A is sequentially input, the memory control unit 5 writes the sampling data in each memory in the state shown in FIG. The sampled data is read out to create display data as shown in FIG.

That is, when the sampling data O1 of the odd field of the first frame in FIG. 3A is input, the sampling data O1 is stored in the first memory 1 for the odd field as shown in FIG. 3B. Is stored.
Next, when the sampling data E1 of the even field of the first frame is input, the sampling data E1 is stored in the first memory 3 for the even field. And
The memory control unit 5 writes the sampling data E1 and, at the same time, reads and outputs the sampling data O1 stored in the first memory 1 for odd fields.

Next, when sampling data O2 of the odd field of the second frame is input, the sampling data O2 is stored in the second memory 2 for the odd field. The memory control unit 5 writes the sampling data O2, simultaneously reads and outputs the sampling data O1 stored in the odd-field first memory 1, and stores the sampling data O1 in the even-field first memory 3. The sampling data E1 is read and output.

Next, when the sampling data E2 of the even field of the second frame is input, the sampling data E2 is stored in the second memory 4 for the even field. The memory control unit 5 writes the sampling data E2, reads out and outputs the sampling data 02 stored in the second memory 2 for odd fields, and outputs the sampling data E2. The data E1 is subsequently read and output.

Thus, the sampling data O1, E1, O2, E2, O3, E3,... Shown in FIG.
Are sequentially input to each of the memories 1 to 4 as shown in FIG.
Writing and reading of sampling data are performed at the timings shown in FIG. 3C, and as shown in FIG. 3C, the display data (O1 / E1), (O2 / E1), (O2 / E1).
2), (O3 / E2), (O3 / E3), (O4 / E
3), (O4 / E4), (O5 / E4),.
Output sequentially at ms intervals. This frame image is sent to a display, which is not shown, and is displayed on a screen.

FIG. 4 shows a specific circuit example of the device of the present invention. In the figure, 1 is a first memory for odd fields (ODD1 memory), 2 is a second memory for odd fields (ODD2 memory), 3 is a first memory for even fields (EVEN1 memory), and 4 is a second memory for even fields. (EVEN2 memory), 5 is a memory control unit. 6
Memory write data buffer is _{1-6 4} permits the passage of data to be stored in each memory (W (D)), 7 1
_7-4 memory read data buffer to allow the passage of data read from the memory (R (D)), 8 1 ~
8 ₄ memory write address buffer to allow the passage of light (write) address (W (A)), 9 1 ~9
₄ is a memory read address buffer (R (A)) for permitting passage of a read (read) address, 10 to 17
Is a negative logic AND gate, and 18 to 20 are inversion circuits.
The same parts as those in FIG. 2 are denoted by the same reference numerals.

The operation of the circuit of FIG. 4 will be described with reference to the timing chart of FIG. 5 and the operation explanatory diagram of FIG. For the sake of simplicity, FIG. 5 (A) and FIG.
The operation of the timing position portion in (A) will be described. The operation at other timing positions is the same as the operation at this timing position.

First, the operation at the timing position will be described. In the case of the timing position, the write memory select signal in FIG. 5B is “0”, and the ODD in FIG.
(Even field) Memory toggle signal is "1", FIG.
The (E) EVEN (even field) memory toggle signal is "1". Therefore, eight negative logics AN
Of the D gates 10 to 17, the negative logic AND gates 10,
The outputs 13, 14, 16 and 17 are "1", and the output of the negative logic AND gate 12 is "0". In addition, negative logic A
The ND gates 11 and 15 have their gates opened by a "0" signal applied to one input terminal.

The output of the negative logic AND gate 10 becomes "1".
Then, the memory write address buffer 8₁And memorabilia
Unit data buffer 6₁Becomes inactive. Also,
When the output of the negative logic AND gate 13 becomes "1", the memory
Read address buffer 9 _TwoAnd memory read data
Buffer 7_TwoBecomes inactive. In addition, negative logic AND
When the gate 14 becomes "1", the memory write
Less buffer 8_ThreeAnd memory write data buffer 6_Three
Becomes inactive. Also, the negative logic AND gate 16 is
When the output becomes "1", the memory write address buffer
8_FourAnd memory write data buffer 6_FourIs inoperative
Becomes Also, the negative logic AND gate 17 outputs “1”.
Then, the memory read address buffer 9_FourAnd memory
Read data buffer 7_FourBecomes inactive.

When the output of the negative logic AND gate 12 becomes "0", the memory write address buffer 8 ₂
Memory write data buffer 6 ₂ is in an operating state. When the memory write address buffer ₈₂ and the memory write data buffer 6 ₂ is in an operating state, the second memory (ODD2 memory) 2 for odd field becomes write (write) mode, FIG. 5 (C) and 3
As shown in (B), the sampling data O2 of the odd field of the second frame is successively written and stored at an address position designated by a write (write) address.

On the other hand, the negative logic AND gates 11 and 15
As described above, the gate is opened by the "0" signal applied to one input terminal. For this reason, the read memory select signal shown in FIG. 5D applied to the other input terminal passes through the negative logic AND gates 11 and 15 as they are, and the subsequent memory read / address buffer 9 ₁ and memory read data buffer _71, a memory read address buffer 9 _3, is sent to a memory read data buffer 7 _3.

The memory read address buffer 9 _1, a read memory select signal to the memory read data buffer ₇₁ is inputted, the first memory for the odd field (ODD1 memory) 1 becomes read (read) mode, FIG. 5 As shown in FIG. 3C and FIG. 3B, the sampling data O1 of the odd field of the first frame stored in the first memory for odd field (ODD1 memory) 1 is designated by a read (read) address. It reads and outputs one after another from the address position where it is.

The memory read / address buffer 9
_3, the read memory select signal to the memory read data buffer 7 ₃ is input, a first memory (EVEN1 memory) 3 for the even field is a read (read) mode, FIG. 5 (E) and FIG. 3 (B) As shown in
The sampling data E1 of the even field of the first frame stored in the first memory for even field (EVEN1 memory) 3 is sequentially read from an address position designated by a read (read) address and output.

The read memory select signal is
As shown in the enlarged view of FIG. 5D, the pulse frequency is composed of the pulse frequencies corresponding to the total number of pixels in one field, and is "0".
The pixels of the odd field (ODD) memory are alternately read at the level position, and the pixels of the even field (EVEN) memory are alternately read at the "1" level position.

As a result of the above processing operation, at the timing position, as shown in FIG. 3B, at the same time as the sampling data O2 is written in the odd field second memory (ODD2 memory) 2, the odd field 1
Sampling data O from the memory (ODD1 memory) 1
1 is a first memory for an even field (EVEN1).
Sampling data E1 is read from the memory 3)
It is output as display data (O1 / E1) as shown in FIG.

Next, the operation at the timing position will be described. In the case of the timing position, the write memory select signal in FIG. 5B is “1”, and the ODD in FIG.
(Even field) Memory toggle signal is "0", FIG.
The (E) EVEN (even field) memory toggle signal is "1". Therefore, eight negative logics AN
Of the D gates 10 to 17, the negative logic AND gates 10,
11, 12, 14 and 17 output "1", and the negative logic AND gate 16 outputs "0". In addition, negative logic A
The ND gates 13 and 15 have their gates opened by a "0" signal applied to one input terminal.

The output of the negative logic AND gate 10 becomes "1".
Then, the memory write address buffer 8₁And memorabilia
Unit data buffer 6₁Becomes inactive. Also,
When the output of the negative logic AND gate 11 becomes "1", the memory
Read address buffer 9 ₁And memory read data
Buffer 7₁Becomes inactive. In addition, negative logic AND
When the output of the gate 12 becomes "1", the memory write
Less buffer 8_TwoAnd memory write data buffer 6_Two
Becomes inactive. Also, the negative logic AND gate 14
When the output becomes "1", the memory write address buffer
8_ThreeAnd memory write data buffer 6_ThreeIs inoperative
Becomes Also, the negative logic AND gate 17 outputs “1”.
Then, the memory read address buffer 9_FourAnd memory
Read data buffer 7_FourBecomes inactive.

When the output of the negative logic AND gate 16 becomes "0", the memory write address buffer 8 ₄
Memory write data buffer 6 ₄ is in an operating state. When the memory write address buffer 8 ₄ and the memory write data buffer 6 ₄ is in an operating state, the second memory (EVEN2 memory) 4 for the even field is a write (write) mode, FIG. 5 (E) and 3
As shown in (B), the sampling data E2 of the even field of the second frame is successively written and stored at an address position designated by a write (write) address.

On the other hand, the negative logic AND gates 13 and 15
As described above, the gate is opened by the "0" signal applied to one input terminal. For this reason, the read memory select signal shown in FIG. 5D applied to the other input terminal passes through the negative logic AND gates 13 and 15 as they are, and the subsequent memory read / address buffer 9 ₂ and memory read data buffer 7 _2, memory read address buffer 9 _3, is sent to a memory read data buffer 7 _3.

The memory read address buffer 9 _2, a read memory select signal on the memory read data buffer 7 ₂ is input, the second memory for the odd field (ODD2 memory) 1 becomes read (read) mode, FIG. 5 As shown in FIG. 3 (C) and FIG. 3 (B), the sampling data O2 of the odd field of the second frame stored in the second memory for odd field (ODD2 memory) 1 is designated by a read (read) address. It reads and outputs one after another from the address position where it is.

The memory read / address buffer 9
_3, the read memory select signal to the memory read data buffer 7 ₃ is input, a first memory (EVEN1 memory) 3 for the even field is a read (read) mode, FIG. 5 (E) and FIG. 3 (B) As shown in
The sampling data E1 of the even field of the first frame stored in the first memory for even field (EVEN1 memory) 3 is sequentially read from an address position designated by a read (read) address and output.

As a result of the above processing operation, at the timing position, as shown in FIG. 3B, at the same time as the sampling data E2 is written in the second memory for even fields (EVEN2 memory) 4, the second data for odd fields is simultaneously read. Sampling data O2 from the second memory (ODD2 memory) 1 and the first memory (EVEN) for even-numbered fields.
1), the sampling data E1 is read out, and the display data (O2 / E1) is displayed as shown in FIG.
Is output as

The same processing operation as described above is performed in the manner shown in FIG.
By executing the sampling data at all timing positions, the display data (O1 / E1), (O2 / E1), (O2 / E2),
(O3 / E2), (O3 / E3), (O4 / E3),
(O4 / E4), (O5 / E4),... Are sequentially output at intervals of 16.6 ms.

In the above example, the case where the display screen is a full size (1/1 screen) without reduction is described. However, the method of the present invention uses a reduced screen converted by the averaging method (for example, 1/4 reduction). Screen, 1/16 reduced screen, etc.). FIG. 6 shows 1 /
4 shows a method of creating a reduced screen. In order to reduce the screen size to 1/4, 2 × 2 pixels of the 1/1 screen are regarded as one block, the average value is obtained, and the obtained average value is compared with the signal level value of the corresponding pixel in the 1/4 screen. Is what you do. Similarly, in the case of a 1/16 reduced screen, the average value of 4 × 4 pixels is determined as one block, and the obtained average value is 1/1.
What is necessary is just to set the signal level value of the pixel at the corresponding position in the six screens.

In the above example, the field frequency 60
Although the description has been given taking the case of an NTSC television signal having a frequency of 30 Hz and a frame frequency of 30 Hz as an example, the present invention is not limited to this signal, and can be applied to any interlaced video signal.

[0042]

As described above, according to the display method of the first aspect, an odd field image in one frame image of adjacent frame images and an even field image in the other frame image are used. Since a new intermediate frame image is created and the created intermediate frame image is inserted between the adjacent original frame images,
The motion is smoother than a display image consisting only of the original frame image, and even if an object or a symbol on the display screen moves at a high speed, a large image distortion as in the related art does not occur. For this reason, it is possible to display a clear image with small distortion, in which the image distortion based on the time difference due to the interlaced scanning is not conspicuous.

According to the display device of the present invention, two memories for storing the video signal of the odd field, two memories for storing the video signal of the odd field, and writing of the video signal to each of these memories. Since the display data of the intermediate frame image is created using the memory control circuit for controlling the reading and the display data of the created intermediate frame image is inserted between the display data of the adjacent original frame images. , The movement of the displayed image is smooth,
It is possible to provide an image display device in which image distortion based on a time difference due to interlaced scanning is small.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the method of the present invention.

FIG. 2 is a block diagram showing a basic configuration of a device of the present invention configured by applying the method of the present invention.

FIG. 3 is an operation explanatory view of the device of the present invention.

FIG. 4 is a diagram showing a specific circuit example of the device of the present invention.

FIG. 5 is a timing chart of the circuit example of FIG. 4;

FIG. 6 is a diagram illustrating a method of creating a １ ／ reduced screen using an averaging method.

FIG. 7 is an explanatory diagram of a video signal of the interlaced scanning method.

FIG. 8 is a diagram illustrating a configuration of a conventional display device.

FIG. 9 is a diagram illustrating the operation of a conventional device.

FIG. 10 is a diagram illustrating an example of occurrence of image distortion in a video signal of the interlaced scanning method.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 First memory for odd field 2 Second memory for odd field 3 First memory for even field 4 Second memory for even field 5 Memory control unit 6 _{1 to} 6 ₄ Memory write / data buffer 7 _{1 to} 7 ₄ Memory read Data buffer 8 ₁ to 8 ₄ Memory write / address buffer 9 _{1 to} 9 ₄ Memory read / address buffer 10 to 17 Negative logic AND gate 18 to 20 Inverting circuit

Claims (2)

[Claims] 1. A display method for displaying, on a screen, an image composed of interlaced video signals, comprising: an odd field image in one frame image of adjacent frame images; and an even field field in another frame image. A new intermediate frame image is created using the image, and the created intermediate frame image is inserted between the adjacent original frame images. 2. A display device for displaying, on a screen, an image composed of a video signal of an interlaced scanning method, comprising two memories for storing a video signal of an odd field;
Two memories for storing video signals of even fields;
A memory control circuit that controls writing and reading of a video signal to and from each of the memories, wherein the memory control circuit writes a video signal to any one of the memories while storing a video signal stored in another memory. By reading, the display data of the new intermediate frame image is created from the video signal of the odd field in one frame image of the adjacent frame image and the video signal of the even field in the other frame image, and the created intermediate frame image is created. A display device which controls so as to insert and output display data of a frame image between display data of the adjacent original frame images.