JPH1098692A - Image display - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid influence of a noise even if the noise to be superimposed on a video signal exists by extending an interval to judge 'presence/absence of motion' longer than a conventional one. SOLUTION: A switch 10 selects a video signal B read out of field memory 1 of an initial stage when an output signal M from a switching signal generating circuit 11 shows a high level and selects a video signal K read out of line memory 9 when the output signal M shows a low level. In this case, if the video signal K read out of the line memory 9 is based on the video signal B read out of the field memory 1 of the initial stage, the video signal K is line period, when the video signal K is based on a video signal C read from field memory 2 of a middle stage, the video signal K is field period. Consequently, since the interval to judge 'presence/absence of motion' is extended longer than the conventional one, frequent change of the judging result of 'presence/absence of motion' by the noise is avoided even if noise to be superimposed on the video signal exists.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device for converting an interlaced video signal into a non-interlaced video signal and displaying an image.

[0002]

2. Description of the Related Art In an image display device such as a liquid crystal display device or a plasma display device, it is sometimes necessary to convert an interlaced video signal into a non-interlaced video signal.

For such conversion, it is necessary to double the number of scanning lines included in one field. As a method of converting the number of scanning lines, there are a field interpolation method and a line interpolation method.

[0004] The former field interpolation method is a method of outputting data of a pixel at the same position one field before the current field on a line to be interpolated in the current field. Is a method of outputting, on a line to be interpolated, data of pixels included in any one of upper and lower lines adjacent thereto.

[0005] Field interpolation has the advantage of increasing the resolution in the vertical direction when displaying an image. However, since the video signals of two fields having an input time difference are displayed at the same time, the image is distorted when displaying a moving image.

On the other hand, the line interpolation has the advantage that the displayed image is completely replaced for each field, so that the image is less distorted and suitable for displaying a moving image. On the other hand, the same data is displayed over two lines. The vertical resolution is inferior to field interpolation.

As described above, since the field correlation is larger than the line correlation in the display of the stationary surface, the field interpolation is performed.
Line display is suitable for displaying moving images because line correlation is larger than field correlation.

Therefore, in the prior art, the difference between the characteristics of the field interpolation and the line interpolation is utilized,
"Presence or absence of motion" of the video signal for each pixel when displaying images
A technique has been disclosed in which the display quality is improved by switching between the above two interpolation methods based on the determination result (for example, Japanese Patent Application Laid-Open No. 63-15 / 1988).
6487).

FIG. 4 is a block diagram showing the configuration of an image display apparatus common to that of the above-mentioned Japanese Patent Application Laid-Open No. 63-156487, which is an example of the prior art, and FIG. Is a time chart of signals of various parts for the following.

Referring to FIG. 4, field memories 14, 1
Numeral 5 is capable of storing a digitized video signal for one field.
Reference numerals 20, 23, and 24 are capable of storing digitized video signals for one line.

The above-mentioned field memories 14 and 15 include:
When one is in the write mode, the other is alternately switched for each field so as to be in the read mode, and when the video signal for one field is sequentially written, one field already stored in parallel with the video signal is written. Minute data is sequentially read.

[0012] In each of the field memories 14 and 15, a video signal in the NTSC system transmitted from a conventional broadcasting station is written at the same speed.
From the field memory 14 (or 15) selected by the switch 13 described later, the video signal
From the other field memory 15 (or 14), which was read out at the same speed V and not selected by the switch 13, the video signal is twice as fast as the writing speed V (= 2V).
To be read.

Further, each of the line memories 19 and 2
0, 23, and 24 are alternately switched every horizontal synchronization period H (one line) so that when one is in the write mode, the other is in the read mode, and when video signals for one line are sequentially written. , The one-line video signal already stored is sequentially read out in parallel.

Then, each of the line memories 19, 20,.
23 and 24 include NT transmitted from a conventional broadcasting station.
While the video signal by the SC system is written at the same speed, the speed is twice as fast as the writing speed V (= 2).
V) and read twice consecutively.

The switches 13 and 17 are switched so that, for each field of the input video signal, one selects the field 14 (or 15) and the other selects the field memory 15 (or 14). is there.

The switch 16 selects the same field memory as that selected by the switch 13 and outputs the video signal to the switch 22.

One of the switches 18 and 21 selects a line memory 19 (or 20) and the other selects a line memory 20 (or 19) for each line of an input video signal.
Is selected, and similarly, the switches 22 and
Reference numeral 25 designates switching for selecting one line memory 23 (or 24) and selecting the other line memory 24 (or 23) for each line of the input video signal.

The level comparator 26 includes switches 21 and
5 are input together, the difference between the quantization levels for each pixel of both data R and S is obtained, and the level difference is set in advance for the determination of “the presence or absence of motion”. When the level difference is smaller than the threshold value, there is "no motion" between the previous and next fields, and when the level difference is larger than the threshold value, there is "motion" between the previous and next fields. The determination is performed, and a switching signal based on the determination result is output to the switch 27.

The switch 27 is connected to the switch 2 during the first half H / 2 (= h) of the horizontal synchronization period H of the input video signal.
The video signal from the first side is forcibly selected, and in the remaining second period H / 2 (= h), the switching signal from the level comparator 26 selects the video signal output from both switches 17 and 21. Is selected.

Next, the operation of the image display device having the configuration shown in FIG. 4 will be described with reference to a time chart shown in FIG.

Incidentally, here, in order to simplify the explanation,
It is assumed that the input video signal is an odd-numbered field, and that the numbers assigned to the respective signals in FIG. 5 have the following meanings.

For example, in the case of "2O3", the leftmost digit indicates the order of input of the field, the central alphabet indicates whether the field is odd or even, O is odd, E is even, and 1 The rightmost number indicates the line number in the field. Therefore, the meaning of “2O3” is a signal on the third line of the second odd field.

Now, it is assumed that the input video signal O is an odd-numbered field, and that one of the field memories 14 is selected by the switch 13. At this time, the video signal of the odd field is written to the field memory 14. At the same time, this field memory 1
4, the already stored video signal P one frame before (= two fields before) becomes the same speed V as the writing speed V.
Is read. After selecting this video signal P, the switch 16 sends it to the switch 22.

In parallel with this operation, the video signal Q written one field before the video signal O is read from the other field memory 15 at a speed 2V twice as fast as the writing speed. However, in this case, the readout timing of the video signal Q is performed in the second half h of the horizontal synchronization period H of the video signal O of the input odd field so that the field interpolation is appropriately performed.

When the switch 13 selects one field memory 14, the switch 17 selects the other field memory 15, so that the output Q of the field memory 15 is sent to the switch 27 as it is.

The video signal 0 of the odd field is also sent to the switch 18 in parallel with being sent to the field memory 14.

If one line memory 19 is selected by the switch 18 and a video signal for one line is written, the switch 21
, The other line memory 20 is selected. From this line memory 20, the video signal R of one line before is continuously output twice at a speed twice as fast as the writing speed and twice during one horizontal synchronization period H. It is read out and sent to the switch 27 and the level comparator 26.

Further, one of the line memories 23 is selected by the switch 22 and one frame before (two fields before).
When the video signal of one line is written, the other line memory 24 is selected by the switch 25 in parallel with this, and the video signal S of the previous line is output from the line memory 24. The data is read out twice at a speed twice as fast as the writing speed and continuously during one horizontal synchronizing period H and sent to the level comparator 26.

Therefore, in the above example, the level comparator 26 has the video signal R of the current odd-numbered field and the video signal of the same line one frame before (the odd-numbered field two fields before). S will be input together.

In the level comparator 26, both video signals R, S
Is obtained in units of one pixel, and the level difference is compared with a threshold value set for determination of “presence or absence of motion”.

If the level difference is smaller than the threshold value, it is determined that there is no motion between the preceding and following fields, and a high-level switching signal is supplied to the switch 27 during the latter half of the horizontal synchronization period H. If the level difference is larger than the threshold value, it is determined that there is “motion” between the preceding and following fields, and a low-level switching signal is output to the switch 27 during the latter half of the horizontal synchronization period H, for example h.

The switch 27 selects the output of the switch 17 when a high-level switching signal is supplied, and selects the output of the switch 21 to which a low-level switching signal is supplied.

Therefore, for example, the level comparator 26
When the state determined as “no motion” between the previous and next fields continues as it is over a plurality of lines, the video signal U () output from the switch 27 is in the first half of the horizontal synchronization period H, H / 2. (= H), the video signal for one line of the current field (here, odd field) is a video signal for one line of one field before (here, even field) in the latter half period H / 2 (= h). Is output to the display.

When the level comparator 26 determines that "moving" between the preceding and succeeding fields continues over a plurality of lines, the video signal U () output from the switch 27 is In the first half of the period H, the video signal for one line of the current field (here, the odd field) in the second half of the period H / 2 (= h)
(= H), the video signal of the same line of the same current field (here, an odd field) is output to the display. That is, if it is determined that there is no motion, field interpolation is performed, and if it is determined that there is motion, line interpolation is performed.

FIG. 5 shows the case where only "no motion" or "only motion" continues over a plurality of lines, but the determination of the presence or absence of motion is made on a pixel-by-pixel basis. Therefore, the video signal output U is frequently switched in the same field and line.

[0036]

SUMMARY OF THE INVENTION As described above,
In the related art, the presence or absence of motion is determined for each pixel, and switching between field interpolation and line interpolation is performed based on the determination result, thereby enabling display of a high-resolution still image and a moving image without distortion. .

However, the switching of the interpolation method based on the above-mentioned "presence / absence of motion" is performed by comparing the video signal of the pixel at the same position of the current field and the field two fields (one frame) before the current field, and determining the level of both. Since the difference is compared with a predetermined threshold value, especially when the level difference of the video signal is near this threshold value, if noise or the like is superimposed on the video signal, it is influenced by the noise to determine whether or not there is motion. May change frequently and may not be stable.

That is, when the level difference is obtained by comparing the video signal of the pixel at the same position two fields before (one frame before) with respect to the current field as in the prior art, the level difference is expressed by " When it is near the threshold value for the determination of the presence / absence of motion, the result of the determination of the presence / absence of movement is frequently switched because it is easily affected by noise or the like. When the field interpolation and the line interpolation are frequently switched at the same position and displayed, the luminance level also changes due to the difference in the interpolation method, so that the displayed image flickers and the image quality deteriorates.

[0039]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention converts an interlaced video signal to a non-interlaced video signal and displays an image.
Field interpolation for outputting the data of the pixel at the same position one field before on the line to be interpolated, and line interpolation for outputting the data of the pixel contained in any one of the upper and lower lines adjacent to the line to be interpolated The following configuration is adopted in an image display device configured to perform switching control based on a motion detection result of a motion detection unit that performs level comparison for each pixel at the same position between different frames.

That is, in the present invention, the motion detecting means
It is configured to detect the presence or absence of motion by performing level comparison at least for pixels at the same position before and after a plurality of frames.

In this configuration, the interval of motion detection is longer than before, so that the phenomenon that field interpolation and line interpolation are frequently switched is suppressed, and flickering of display pixels is reduced.

In particular, in the structure according to the first aspect, the motion detecting means includes a level comparing means for performing a level comparison for each pixel at the same position before and after one frame, and delaying a comparison result of the level comparing means by at least one frame. A signal for selecting field interpolation only when the output result of the level comparing means and the output result of the delay means are both "no motion" determination results, and otherwise selecting line interpolation. And a logic means for outputting In particular, the delay means can be constituted by a field memory, and the logic means can be constituted by an AND gate.

[0043]

FIG. 1 is a block diagram showing an image display device according to an embodiment of the present invention.

The image display device of this embodiment includes three field memories 1, 2, 3 in the first stage, the middle stage, and the last stage.

Each of the field memories 1, 2, 3 can store a digitized video signal for one field. When the video signals for one field are sequentially written, they are stored in parallel. 1 already memorized
The video signals for the fields are sequentially read. Moreover, the reading speed of the video signal by the first-stage field memory 1 is twice (= 2) the writing speed V.
V), and each of the middle and final field memories 2,
3 is performed at twice the writing speed (= 2 V) of the writing speed of the first-stage field memory 1 in both the writing speed and the reading speed. Therefore, for each of the field memories 1, 2, and 3, reading of a video signal for one line is performed in the first half of the horizontal synchronization period H, H / 2 (= h).

The level difference detector 4 has a video signal B read from the first-stage field memory 1 and a video signal D read from the last-stage field memory 3 (which is
The difference between the quantization levels (which is the signal before the frame) is obtained for each pixel.

The level comparator 5 compares the level difference detection signal E detected by the level difference detector 4 with a threshold value set in advance for the determination of “presence or absence of motion”. If it is smaller than the threshold value, it is determined that there is no movement, and if the level difference is larger than the threshold value, it is determined that there is movement and a low-level determination signal F is output.

The field memory 6 is capable of storing video signals for one field, and here the level comparator 5
Is provided for delaying the output signal of 2 fields by 2 fields (= 1 frame).

That is, when the decision signal F output from the level comparator 5 in units of one pixel is sequentially written into the field memory 6, the judgment signal G already written in parallel with the judgment signal F is stored in units of one pixel. Read sequentially,
Further, when the read determination signal G is sequentially written into the field memory 6 again, the already written determination signal H is sequentially read in parallel with this.

In this case, the writing speed and the reading speed of each of the signals F, G, H of the field memory 6 are set so as to be the same 2 V as those of the field memories 2 and 3 in the middle stage and the subsequent stage.

The AND gate 7 outputs two fields from the judgment result output F of the level comparator 5 and the field memory 6.
(= 1 frame) The logical sum of the judgment result regarding the pixel at the same position, which is output after being delayed, is calculated.

In this embodiment, the level difference detector 4, the level comparator 5, the field memory 6, and the AND gate 7 constitute a motion detecting means 12.

When a high-level signal is output from the AND gate 7, the switch 8 outputs a low-level signal to the video signal C read from the middle-stage field memory 2 for field interpolation. If
The video signal B read from the first-stage field memory 1 for line interpolation is selected and output to the next-stage line memory 9.

The line memory 9 is capable of storing one line of video signal. During the first half H / 2 (= h) of the horizontal synchronization period H, one line of video signal J is sequentially written, and In the latter half of the period H / 2 (= h), one line of the video signal K written in the first half of the period is sequentially read. The writing speed and the reading speed are both the first stage field memory 1 Twice the writing speed of
V).

The switching signal generation circuit 11 performs the first half of the horizontal synchronization period H based on the horizontal synchronization signal L included in the NTSC video signal transmitted from the broadcasting station.
A switching signal M which is at a high level at H / 2 (= h) and at a low level in the second half H / 2 (= h) is generated, and this switching signal M is output to the switch 10.

The switch 10 selects the video signal B read from the first-stage field memory 1 when the output signal M from the switching signal generating circuit 11 is at a high level, and reads the video signal B from the line memory 9 when the output signal M is at a low level. The selected video signal K is selected and output to a display.

Next, the operation of the image display device having the configuration shown in FIG. 1 will be described with reference to a time chart shown in FIG.

Here, in order to simplify the explanation,
It is assumed that the digitized video signal input at the present time is an even-numbered field, and that the numbers given to the respective signals in FIG. 2 have the following meanings.

For example, in the case of "2E4", the leftmost digit indicates the order of input of the field, the central alphabet indicates whether the field is odd or even, O is odd, E is even, and 1 The rightmost number indicates the line number in the field. Therefore, the meaning of “2E4” is a signal on the fourth line of the second even field.

When the input video signal A is an even field, the video signal for one field is written into the first-stage field memory 1. In parallel with this, the video signal B of the odd field, which is one field before and is already stored, is read from the first-stage field memory 1 at a speed 2V which is twice the writing speed V. Therefore, the reading of the video signal for one line is performed within the first half period H / 2 (= h) of the horizontal synchronization period H.

Middle and final field memories 2, 3
Is performed in synchronization with the read timing of the field memory 1 (that is, performed at twice the writing speed of the first-stage field memory 1), so that the video signal C read from the middle-stage field memory 2 is read and written. Is a video signal one field before the video signal B read from the first-stage field memory 1, and
Similarly, the video signal D read from the last-stage field memory 3 is a video signal one field before the video signal C read from the middle-stage field memory 2. That is, the video signal D is a video signal two fields before (= 1 framed before) the video signal B.

The video signal B read from the field memory 1 at the first stage is sent to the switches 8 and 10 and sent to the level difference detector 4 to detect the level difference between the video signal and the previous frame. Is also entered.

The level difference detector 4 comprises a video signal B read from the first-stage field memory 1 and a video signal D read from the last-stage field memory 3 (this is a signal one frame before). Is obtained for each pixel, and the level difference is output to the next-stage level comparator 5.

The level comparator 5 compares the level difference detection signal E detected by the level difference detector 4 with a threshold value set in advance for determining whether or not there is motion. If it is smaller than the threshold, it is determined that there is no movement, and if the level difference is larger than the threshold, it is determined that there is movement and a low-level determination signal F is output.

The field memory 6 writes the output signal F and reads the output signal G of the level comparator 5 at the same timing as the middle and final stage field memories 2 and 3, and writes and outputs the output signal G. Signal H
As a result, when viewed from the output signal F of the level comparator 5, the output signal H of the field memory 6 is the same as the output signal of the level comparator 5 one frame before (= two fields before). I can say.

The AND gate 7 outputs the output signal F of the level comparator 5 and the output signal H read from the field memory 6 (this corresponds to the output F of the comparator 5 at the same pixel at one frame before one frame). ) And OR.

Therefore, the output of the AND gate 7 becomes high level when the output F of the level comparator 5 becomes high level for two or more frames (when it is determined that there is no motion for two or more frames). ). Further, when the output F of the level comparator 5 becomes low level in two frames (when it is determined that there is "motion" in two frames)
, The output of the AND gate 7 becomes low level.

When the output of the AND gate 7 is at a low level meaning "moving", the switch 8 changes the video signal B read from the first-stage field memory 1 for line interpolation to "no motion". When the signal is at the high level, the video signal C read from the middle field memory 2 for field interpolation is selected, and this is output to the next line memory 9 as the video signal J.

In the first half of the horizontal synchronizing period H, the line memory 9 receives 1 from the switch 8 during the period H / 2 (= h).
The video signals J for the lines are sequentially written, and the video signal K for one line written in the first half of the remaining second period H / 2 (= h) is sequentially read. Then, the read video signal K is given to the switch 10.

The switch 10 selects the video signal B read from the first-stage field memory 1 when the output signal M from the switching signal generation circuit 11 is at a high level, and reads the video signal B from the line memory 9 when the output signal M is at a low level. The output video signal K is selected.

At this time, if the video signal K read from the line memory 9 is based on the video signal B read from the first-stage field memory 1, the line interpolation is performed, and the video signal read from the middle-stage field memory 2 is read. If it is based on the signal C, it is a field interpolation.

As described above, in this embodiment, since the interval for determining “the presence or absence of motion” is longer than in the past (the determination is made over two or more frames), it is superimposed on the video signal. Even if there is noise or the like, the determination result of “presence / absence of motion” is not frequently switched due to the influence. For this reason, unlike the related art, it is possible to prevent the luminance level from being changed due to the difference in the interpolation method between the field interpolation and the line interpolation, thereby preventing the displayed image from flickering and deteriorating the image quality.

In the embodiment shown in FIG. 1, a dedicated field memory 6 is provided to delay the output signal of the level comparator 5 by two fields (= 1 frame). If the storage capacity of the field memories 2 and 3 has room and the output F of the level comparator 5 can be stored in an area different from the area where the video signals B and C are stored, the output F can be used. As shown in FIG. 3, the field memory 6 can be omitted.

That is, in the configuration shown in FIG. 3, while the video signals B and C are stored in the middle and final stage field memories 2 'and 3', respectively, the output F of the level comparator 5 is first ANDed. The output G of the level comparator 5 which is added to the gate 7 and is stored in the middle-stage field memory 2 ′ and read out from the middle-stage field memory 2 ′ one field before is read out from the middle-stage field memory 2 ′. In response to this, the output H of the level comparator 5 one field before, which is read from the last-stage field memory 3 ′, is supplied to the AND gate 7. Therefore, what is compared by the AND gate 7 is the current output F of the level comparator 5 and one frame earlier (=
This is the output H of the level comparator 5 (two fields before), which means that the output of the level comparator 5 has been delayed by one frame by the field memories 2 'and 3'.

In each of the above embodiments, the field interpolation is performed only when it is determined that “no motion” has occurred for two or more frames. However, the present invention is not limited to this. It is also possible to perform field interpolation only when it is determined that there is "no motion" for four or more frames.

[0076]

According to the present invention, the interval for judging "the presence / absence of motion" is made longer than before.
Even if there is noise or the like superimposed on the video signal, the determination result of “presence / absence of motion” is not frequently switched due to the influence.

For this reason, it is possible to eliminate the problem that the luminance level changes due to the difference in the interpolation method between the field interpolation and the line interpolation and the displayed image flickers and the image quality is deteriorated. Is done.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an image display device according to an embodiment of the present invention.

FIG. 2 is a time chart for explaining the operation of the image display device having the configuration of FIG. 1;

FIG. 3 is a block diagram showing a configuration of an image display device according to another embodiment of the present invention.

FIG. 4 is a block diagram illustrating a configuration of a conventional image display device.

FIG. 5 is a time chart for explaining the operation of the conventional apparatus of FIG. 4;

[Explanation of symbols]

1, 2, 3, ... field memory, 4 ... level difference detector,
5 level comparator (level comparing means), 6 field memory (delay means), 7 AND gate (logic means), 8 switch, 9 line memory, 10 switch, 11 switching signal generation circuit, 12 ... Motion detecting means, 2 ', 3' ... Field memory.

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[Procedure amendment]

[Submission date] December 5, 1996

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0026

[Correction method] Change

[Correction contents]

The video signal O of the odd field is also sent to the switch 18 in parallel with being sent to the field memory 14.

[Procedure amendment 2]

[Document name to be amended] Drawing

[Correction target item name] Figure 2

[Correction method] Change

[Correction contents]

FIG. 2

Claims (3)

[Claims] 1. A method of converting an interlaced video signal into a non-interlaced video signal and displaying the converted image signal, wherein a field interpolation for outputting data of a pixel at the same position one field before on a line to be interpolated. A line interpolation for outputting data of a pixel included in one of upper and lower lines adjacent to a line to be interpolated, and a motion of a motion detecting means for performing a level comparison for each pixel at the same position between different frames. In the image display device configured to perform switching control based on a detection result, the motion detection unit is configured to perform level comparison at least for pixels at the same position before and after a plurality of frames to detect presence / absence of motion. An image display device characterized in that: 2. The image display device according to claim 1, wherein said motion detection means performs level comparison for each pixel at the same position before and after one frame, and at least one comparison result of said level comparison means. Delay means for delaying by a frame, and field interpolation is selected only when the output result of the level comparison means and the output result of the delay means are both "no motion", and in other cases, line interpolation is selected. Logic means for outputting a selection signal. 3. The image display device according to claim 2, wherein said delay means is a field memory, and said logic means is AND.
An image display device comprising a gate.