JPS59176773A - Image memory control system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] <Technical Field of the Invention> The present invention relates to a high-speed, large-capacity image memory used in bitmap type raster scan graphic/character display devices, etc., and in particular uses two sets of memory blocks operating in nibble mode. The present invention relates to an image memory control method that continuously outputs data at equal intervals.

<Technical Background> In raster scan graphic/character display devices, the scanning lines of the cathode ray tube scan the fluorescent surface at a constant speed, so the image memory must always be read out at regular intervals. By the way, recently, 256K dynamic RA operating in nibble mode has been developed as a 1LsI memory.
M has been put into practical use. The nibble mode is a mode in which four consecutive bits are accessed and read out in succession. but,
In nibble mode, the second to fourth bits of the four consecutive address bits can be read at equal intervals at high speed, but the first bit requires access for setting the address and for precharging. Since it takes time, it cannot be read out at high speed. Therefore, in the past, in order to be able to read data continuously and at regular intervals during that time, it was necessary to use a buffering method using registers.

FIG. 1 shows an example of the configuration of the conventional image memory described above.

In the figure, 1.2 is dynamic R for each of the four 256
Memory blocks A and B are composed of AM, and are all accessed using the same address. Therefore, 8 bits corresponding to 256 of the 81 and the same address in the dynamic RAM constitute 1 byte of data.

3 is a buffer consisting of four 8-bit registers R, , R, , R2°R8, each 256 of which has a dynamic RAM.
4 consecutive parallel 8 read in nibble mode from
Bit (byte) data is stored in register R8 of the buffer.
It is distributed to each of Rl, Rt, and Rs. Register set signals Load,
Ho, Load, R+, LoaaR2, L2i
adRs is generated and each register 'RO, R1°R, .
The write timing of R is controlled.

4 is a 32-manpower multiplexer MPX, which inputs 8-bit X4 input data from each register R6, R1, R1, Rs to the corresponding channel N O,N.

The selection of N,,N, and the bit interpretation are combined and converted into a continuous serial data video signal.

In this way, each 256KR of memory blocks 1 and 2
Even if the AM operates in nibble mode and a long interval is inserted every 4 bits, the multiplexer 4 can output continuous data with equal bit intervals.

However, this method has the disadvantage that it requires a large number of registers as buffers and multiplexers for switching their outputs.

<Objective and Configuration of the Invention> An object of the present invention is to realize an image memory control method that uses a memory that operates in nibble mode and is capable of reading data at high speed and at regular intervals.

As a means to prevent this, the present invention combines two nibble mode operation type memory blocks and controls the timing so that the access and precharge period of one exactly overlaps with the read period of the other, and its configuration is as follows: It is equipped with two independent memory blocks that operate in nibble mode and a multiplexer that selects one of the outputs of the two memory blocks, and selects the output of one memory block with the multiplexer to operate in nibble mode. While data is being continuously read out, access to the other memory block is started, and the timing is set so that data output from the other memory starts immediately after data output from one memory ends. The method is characterized in that the data read from the two memory blocks are made consecutive at equal intervals by controlling and repeating the above operations alternately.

<Embodiments of the invention> The details of the present invention will be explained below based on examples.

FIG. 2 is a block diagram of an embodiment of the image memory control system according to the present invention, and FIG. 3 is a timing diagram thereof.

In FIG. 2, numerals 5 and 6 each indicate memory blocks A each consisting of four 256 dynamic RAMs.

B and corresponds to memory blocks 1 and 2 in FIG. Further, 7 is an 8-person multiplexer.

There are four nibble mode output lines from each of the 256 dynamic RAMs for each memory block A and B, and these are coupled to each of the eight input terminals of the multiplexer 7. The multiplexer 7 selects 8 in accordance with the A/B selection and bit selection signals given from the memory control circuit 8.
Scans human input signals and converts them into 1-channel video signals.

The memory control circuit 8 also includes a memory block A.

RAS of the nibble mode operation control signal for B.

Generates CAS and address signals, a 3-bit A/B select signal and a bit select signal for multiplexer 7.

Next, the circuit operation will be explained with reference to the timing diagram of FIG.

Memory block A has a nibble mode control signal A-RA.
S, A-CAS and A address are given, and memory block B is similarly given B-RAS.

B-CAS, B address is given. These A-system signals and B-system signals are out of phase with each other by 1/2 as shown by ■ and ■, and each 256-bit signal C is read out serially from the dynamic RAM. As shown by ■ and ■, the pulse width of each control signal is set so that they are connected at just the right timing.

As a result, from memory block A, dynamic RA is applied to four 256 bits in continuous 4-bit operation in nibble mode.
From M, 4 bits each in parallel, (1 to 4), (5 to 8)
, (9-12), (13-16) are read out, immediately following from memory block B, (17-2
0), (21-24), (25-28), (29-32
) are read out.

Regarding these 4-bit parallel readout output bits,
In the multiplexer 7, the memory block output is selected by the A/B select signal, and the parallel 4-pit signal is sampled by the bit select signal and converted into a 1-bit serial video signal at a constant speed and interval.

<Effects of the Invention> As described above, according to the present invention, the access and precharge times that occur when using nibble mode memory are parallelized with the read time of other nibble mode memories, so that the apparent Thus, an image memory control system capable of constant speed reading with fewer parts and low cost can be realized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an image memory according to a conventional method, FIG. 2 is a block diagram of an embodiment of an image memory according to an uninvented method, and FIG. 3 is a timing diagram of the embodiment of FIG. In the figure, 5 is memory block A, 6 is memo 1 block B
, 7 is an eight-person multiplexer, and 8 is a control circuit for memo 1. Patent applicant Fujitsu Limited

Claims (1)

[Claims] Equipped with two independent memory blocks that operate in nibble mode and a multiplexer that selects one of the outputs of the two memory blocks, and selects the output of one memory block with the multiplexer and operates continuously in nibble mode. While the data is being read from the memory block, access to the other memory block is started, and timing control is performed so that data output from the other memory starts immediately after data output from one memory ends. An image memory control method characterized by repeating the above operations alternately to make data read from two memory blocks consecutive at equal intervals.