JPH08147458A - Memory control unit - Google Patents

Abstract

PURPOSE: To decrease the buffer memory capacity of an information processing system which generates plural data differing in bit with. CONSTITUTION: A data generating means 101 generates data with 24-bit and 12-bit widths. Memories 103-104 have 24-bit width. The data with the 12-bit width are stored in the memories so that two data in adjacent addresses are successive. Data expanding means 105-106 expand the 24-bit data stored in the memories 103-104 into 32-bit data. Those data are read out by a memory read means 108. The memories are stored with only the data generated by the data generating means 101, so the buffer memory capacity is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing system for generating image data having a plurality of gradation bit widths.
The present invention relates to a memory control device that temporarily stores image data having a plurality of gradation bit widths in a common buffer memory.

[0002]

2. Description of the Related Art With the recent increase in CPU speed and memory capacity, the processing performance of information processing systems has improved, and the amount of data that can be handled by information processing systems has also increased. This means that, with regard to image data, it has become possible to handle image data having high resolution and high gradation and higher image quality.

The gradation bit width per pixel of image data differs depending on the type of image data. For example,
Full-color images such as natural images are generally 24 bits wide, and grayscale images such as X-ray photographs are generally 1
It is 2 bits wide.

For example, an image processing system such as taking in image data input from a video camera as digital data, decompressing compressed image data, and generating image data by performing three-dimensional graphics processing. Generate image data. The generated image data is finally stored in the main memory, but in order to generate image data at high speed, the image data is temporarily stored in a dedicated buffer memory that can be accessed faster than accessing the main memory. I often do it.

FIG. 3 shows an example of a memory control device of a buffer memory when one information processing system generates a plurality of image data having different gradation bit widths.

In FIG. 3, reference numeral 301 denotes a data generating means for generating two types of image data having different gradation bit widths, and 3
Reference numeral 02 is a data expansion means for adding a bit to the first data, 303 is a data expansion means for adding a bit to the second data, 304 is a data input selection for selecting the output data of the data expansion means 302 and the data expansion means 303. Means, 305 is a memory for temporarily storing image data, 3
Reference numeral 06 is a data reading means for reading image data from the memory 305, 307 is a memory access right arbitration means, 30
8 is a selector for selecting an address to the memory 305, 3
A selector 09 selects a memory control signal for the memory 305.

The data generating means 301 generates image data for each pixel and outputs the address and data of the pixel. The data generating means 301 generates two types of image data, that is, 24-bit width image data and 12-bit width image data. First, consider the case where image data having a width of 24 bits is generated.

The data expansion means 303 adds arbitrary 8 bits to the 24-bit width data output from the data generation means 301 and outputs the data in accordance with the bit width of 32 bits of the memory. FIG. 4 shows an example of data expansion. Here, the image data 401 generated by the data generation means 301 is set to bit 2
Assigned to 3 to 0 and extended data from bits 31 to 24
The data 402 having a width of 32 bits is created by allocating to the.

The data input selection means 304 selects and outputs the 24-bit width data, that is, the output of the data expansion means 303 expanded to the 32-bit width, according to the data selection signal output from the data generation means 301.

The data generation means 301 requests the memory access right arbitration means 307 for an access right to the memory 305. The memory access right arbitration unit 307 arbitrates the memory access right between the data generating unit 301 and the data reading unit 306, and permits the data generating unit 301 to access the memory 305.

The selector 308 selects and outputs the address generated by the data generating means 301 according to the access right selecting signal output from the memory access right arbitration means 307. The selector 309 is a memory access right arbitration unit 30.
The memory control signal generated by the data generating means 301 is selected and output by the access right selection signal output from the data generator 7. The data output by the data input selection means 304 is stored in the memory 305 according to these addresses and the memory control signal.
Is written to the specified position of.

The data reading means 306 requests the memory access right arbitration means 307 for an access right to the memory 305. The memory access right arbitration unit 307 arbitrates the memory access right between the data generating unit 301 and the data reading unit 306, and permits the data reading unit 306 to access the memory 305.

The selector 308 selects and outputs the address generated by the data read means 306 according to the access right selection signal output from the memory access right arbitration means 307. The selector 309 selects and outputs the memory control signal generated by the data reading unit 306 according to the access right selection signal output by the memory access right arbitration unit 307. The data at the specified position in the memory 305 is read to the data reading means 306 by these addresses and the memory control signal.

Similarly, consider the case where the data generating means 301 generates 12-bit width data. Data expansion means 3
02 adds arbitrary 20 bits to the 12-bit width data output from the data generating means 301, and outputs it in accordance with the bit width of 32 bits of the memory. FIG. 4 shows an example of data expansion. Here, the image data 403 generated by the data generating means 301 is assigned to bits 11 to 0, and the extension data is assigned to bits 31 to 12, thereby creating data 404 having a 32-bit width.

The data input selection means 304 selects and outputs the 12-bit width data, that is, the output of the data expansion means 302 expanded to the 32-bit width, by the data selection signal output from the data generation means 301.

The data generating means 301 requests the memory access right arbitration means 307 for an access right to the memory 305. The memory access right arbitration unit 307 arbitrates the memory access right between the data generating unit 301 and the data reading unit 306, and permits the data generating unit 301 to access the memory 305.

The selector 308 selects and outputs the address generated by the data generating means 301 according to the access right selecting signal output from the memory access right arbitration means 307. The selector 309 is a memory access right arbitration unit 30.
The memory control signal generated by the data generating means 301 is selected and output by the access right selection signal output from the data generator 7. The data output by the data input selection means 304 is stored in the memory 305 according to these addresses and the memory control signal.
Is written to the specified position of.

The data reading means 306 requests the memory access right arbitration means 307 for an access right to the memory 305. The memory access right arbitration unit 307 arbitrates the memory access right between the data generating unit 301 and the data reading unit 306, and permits the data reading unit 306 to access the memory 305.

The selector 308 selects and outputs the address generated by the data reading unit 306 according to the access right selection signal output from the memory access right arbitration unit 307. The selector 309 selects and outputs the memory control signal generated by the data reading unit 306 according to the access right selection signal output by the memory access right arbitration unit 307. The data at the specified position in the memory 305 is read to the data reading means 306 by these addresses and the memory control signal.

[0020]

The minimum access unit to the main memory of the information processing system is generally 1 byte (= 8 bits). (2 M power: M is an integer of 0 or more, the upper limit is It can be accessed in byte units (depending on the information processing system). Therefore, the memory configuration also needs to be (2 to the Mth power) byte width.

In order to store 24-bit width data in the (2 M power) byte width memory, at least 4 (= 2 2 power) byte width memory is required since 24 bits = 3 bytes. The memory 305 has a width of 32 bits (= 4 bytes). Therefore, 24-bit width data is stored in the memory 305.
When storing in, it must be expanded to 32 bits wide,
Unnecessary 8-bit data having no information amount must be added to each pixel. This is because the data width is (2 to the Mth power)
This is because it is not the exact bite.

Similarly, in the case of 12-bit width data, a memory with a width of at least 16 bits (= 2 bytes) is required, and unnecessary data of 4 bits with no information amount is not added to each pixel. must not.

However, since the data generating means 301 outputs an address corresponding to each pixel, the memory 3
The address of 05 corresponds to one pixel on a one-to-one basis. Therefore, it is necessary to store 12-bit width data in 32-bit width. Therefore, even when 12-bit width data is stored in the memory 305, it is necessary to expand to a 32-bit width, and unnecessary data 20 having no information amount for each pixel
Bits must be added.

That is, in the case of 24-bit width data,
An extra buffer memory for 8 bits per pixel is required, and an extra buffer memory for 20 bits per pixel is required for 12-bit width data.

In view of the above-mentioned problems of conventional memory control, the present invention has different bit widths such as a 24 bit width and a 12 bit width (3 × (2 to the nth power: n is an integer of 0 or more)). In an information processing system that generates multiple data,
An object of the present invention is to provide a memory control device capable of effectively using a buffer memory having only a required bit width and reducing the memory amount.

[0026]

In order to solve the above problems, the present invention generates and generates a plurality of data having a bit width of (3 × (2 to the nth power: n is an integer of 0 or more)). A plurality of data generating means having different bit widths and a plurality of data output from the data generating means are concatenated and stored for each individual data (2 to the N-th power: N is an integer of n or more). A memory having a width of (3 × (2 to the Nth power)), and data input selection means for selecting data output from the data generation means based on a data selection signal output from the data generation means and inputting the selected data to the memory. Data reading means for reading the data stored in the memory, and arbitrary data is added to the data stored in the memory at a bit position determined by the bit width of the data output by the data generating means (4 × ( N powers), and a plurality of data expanding means for setting the bit width, and data output selecting means for selecting the data output by the data expanding means based on the data selection signal output by the data generating means and inputting the data to the data reading means. It is characterized by having and.

[0027]

The present invention has a memory (3 ×
Data having a bit width of (2 to the Nth power) and smaller than the bit width of the memory (3 × (2 to the nth power)) are concatenated and stored in the memory, Since the data expansion unit adds data at the time of reading the memory to (4 × (2 N power)) (= 2 (N + 2) power) bit width,
You only need as much buffer memory as you need.

[0028]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a memory controller according to an embodiment of the present invention. In FIG. 1, 101 is a data generating means for generating two types of image data having different gradation bit widths, 102 is a data input selecting means for selecting two types of data output from the data generating means 101, 103.
Reference numeral 104 is a memory upper half-bit portion for temporarily storing image data, 104 is a memory half-lower-order bit portion for temporarily storing image data, and 105 is data expansion means for adding bits to the first data. Reference numeral 106 is a data expansion unit for adding a bit to the second data, 107 is a data output selection unit for selecting output data of the data expansion unit 105 and the data expansion unit 106, and 108 is data for reading image data from the memory 103 and the memory 104. Read means, 109 is memory access right arbitration means, 110
Is a control signal generating means for outputting a memory control signal to the memory 103 and the memory 104 from the address and the memory control signal output from the data generating means 101, and 111 is an address for outputting to the memory 103 and the memory 104 from the address outputted by the data generating means 101. , 112 is a selector for selecting addresses to the memories 103 and 104, 113 is a selector for selecting a memory control signal to the memory 103, and 114 is a selector for selecting a memory control signal to the memory 104. is there.

The data generation means 101 generates image data for each pixel and outputs the address and data of the pixel. The data generating means 101 generates two types of image data, that is, image data having a width of 24 bits and image data having a width of 12 bits. First, consider the case where image data having a width of 24 bits is generated.

The data input selection means 102 selects and outputs 24-bit width data according to the data selection signal output from the data generation means 101.

The data generation means 101 requests the memory access right arbitration means 109 for the access right to the memories 103 and 104. Memory access right arbitration means 109
Is a data generating means 101 and a data reading means 108.
Arbitrates the memory access right with the data generating means 1
01 is permitted to access the memory 103 and the memory 104.

The control signal generation means 110 outputs the memory control signal output from the data generation means 101 to the selector 113 and the selector 114 as it is based on the data selection signal output from the data generation means 101.

The shifter 111 is responsive to the data selection signal output from the data generating means 101 to generate the data generating means 10.
The address output by 1 is output as it is to the selector 112.

The selector 112 selects the address output by the shifter 111 according to the access right selection signal output by the memory access right arbitration means 109 and outputs it to the memory 103 and the memory 104. The selector 113 selects the memory control signal output from the control signal generation unit 110 according to the access right selection signal output from the memory access right arbitration unit 109, and outputs it to the memory 103.
The selector 114 selects the memory control signal output from the control signal generation unit 110 according to the access right selection signal output from the memory access right arbitration unit 109 and selects the memory 10.
Output to 4. According to these addresses and memory control signals, the data input selection means 102 outputs 24
Bit-width data is written to specified locations in the memories 103 and 104.

The data reading means 108 requests the memory access right arbitration means 109 for the access right to the memories 103 and 104. Memory access right arbitration means 1
Reference numeral 09 is a data generating means 101 and a data reading means 1
08 arbitrates the memory access right and permits the data reading means 108 to access the memories 103 and 104.

The selector 112 selects the address output by the data reading unit 108 according to the access right selection signal output by the memory access right arbitration unit 109, and outputs it to the memory 103 and the memory 104. The selector 113 is responsive to the access right selection signal output from the memory access right arbitration means 109 to read the data reading means 10.
The memory control signal output from the memory 8 is selected and output to the memory 103. The selector 114 receives the access right selection signal output from the memory access right arbitration unit 109,
The memory control signal output by the data reading means 108 is selected and output to the memory 104. The memory 103 and the memory 1 are controlled by these addresses and memory control signals.
The data at the designated position 04 is read.

The data expansion means 106 adds arbitrary 8 bits to the 24-bit width data read from the memory 103 and the memory 104, and outputs it in accordance with the 32-bit width. FIG. 2 shows an example of data expansion. Here, memory 1
03 and the image data 201 read from the memory 104
Is assigned to bits 23 to 0, and extension data is assigned to bit 3
32 bits wide data 2 by allocating from 1 to 24
Make 02.

The data output selection means 107 selects and outputs 24-bit width data, that is, the output of the data expansion means 106 expanded to 32 bits by the data selection signal output from the data generation means 101, and this data is the data. It is read by the reading means 108.

Therefore, in the case of 24-bit width data,
Two 12-bit width memories (= 24-bit width) may be prepared as buffer memories. A 12-bit wide memory is a 4-bit wide RAM that is widely distributed in the market.
It can be easily configured by arranging them in parallel. Since the buffer memory can be used up only with image data, there is no need for a buffer memory for storing extra data other than image data.

Similarly, consider the case where the data generating means 101 generates 12-bit width data.

The data input selection means 102 selects 12-bit width data in response to the data selection signal output from the data generation means 101, and concatenates two pieces of this 12-bit width data and outputs them in a 24-bit width.

The data generation means 101 requests the memory access right arbitration means 109 for the access right to the memories 103 and 104. Memory access right arbitration means 109
Is a data generating means 101 and a data reading means 108.
Arbitrates the memory access right with the data generating means 1
01 is permitted to access the memory 103 and the memory 104.

Based on the data selection signal output from the data generating means 101, the control signal generating means 110 outputs the data generating means 101 when the least significant bit (bit 0) of the address output from the data generating means 101 is "0". The memory control signal output by the data generator 1 to the selector 113.
When the least significant bit of the address output by 01 is "1", the memory control signal output by the data generating means 101 is output to the selector 114.

The shifter 111 is responsive to the data selection signal output from the data generating means 101 to generate data.
The address output from 1 is shifted to the right by 1 bit (to the lower bit direction) and output to the selector 112.

The selector 112 selects the address output by the shifter 111 according to the access right selection signal output by the memory access right arbitration means 109, and outputs it to the memory 103 and the memory 104. The selector 113 selects the memory control signal output from the control signal generation unit 110 according to the access right selection signal output from the memory access right arbitration unit 109, and outputs it to the memory 103.
The selector 114 selects the memory control signal output from the control signal generation unit 110 according to the access right selection signal output from the memory access right arbitration unit 109 and selects the memory 10.
Output to 4. By these addresses and the memory control signal, when the least significant bit of the address output from the data generating means 101 is "0", the data input selecting means 1
The upper 12 bits of the 24-bit width data output by 02 are placed in the designated position of the memory 103, and the data generating means 101
When the least significant bit of the address output by is 1, the lower 12 bits of the 24-bit width data output by the data input selection means 102 are written to the designated position in the memory 104.

In this way, the image data of the even address (the least significant bit is "0") is stored in the memory 103, and the image data of the odd address (the least significant bit is "1") is stored in the memory 104, and is stored in 24 bits. The width of the buffer memory can be used up only with image data.

The data reading means 108 requests the memory access right arbitration means 109 for the access right to the memories 103 and 104. Memory access right arbitration means 1
Reference numeral 09 is a data generating means 101 and a data reading means 1
08 arbitrates the memory access right and permits the data reading means 108 to access the memories 103 and 104.

The selector 112 selects the address output by the data read means 108 according to the access right selection signal output by the memory access right arbitration means 109, and outputs it to the memory 103 and the memory 104. The selector 113 is responsive to the access right selection signal output from the memory access right arbitration means 109 to read the data reading means 10.
The memory control signal output from the memory 8 is selected and output to the memory 103. The selector 114 selects the memory control signal output from the data reading unit 108 according to the access right selection signal output from the memory access right arbitration unit 109, and outputs it to the memory 104. The memory 103 and the memory 10 are controlled by these addresses and memory control signals.
The data at the designated position 4 is read.

The data expansion means 105 adds arbitrary 8 bits to the 24-bit width data read from the memories 103 and 104, and outputs the data in accordance with the 32-bit width. FIG. 2 shows an example of data expansion. Here, memory 1
The image data 203 read from 03 is assigned to bits 27 to 16, the image data 204 read from the memory 104 is assigned to bits 11 to 0, and the extension data is assigned to bits 31 to 28 and bits 15 to 12. The 32-bit width data 205 is created with.

The data output selection means 107 selects and outputs the output of the data expansion means 105 expanded to 12-bit width data, that is, 32 bits according to the data selection signal output from the data generation means 101, and this data is the data. It is read by the reading means 108.

Therefore, even in the case of 12-bit width data,
Two 12-bit width memories (= 24-bit width) may be prepared as buffer memories. Since the buffer memory can be used up only with image data, there is no need for a buffer memory for storing extra data other than image data.

In the above-mentioned embodiment, an example in which all data is read out by 32 bits is shown, but in the example of the above memory structure, since it is composed of a 4-bit width RAM, 8
It is also possible to read in units of bits or 16 bits.

[0054]

As described above, according to the present invention,
(3 × (2 to the nth power: n is an integer of 0 or more)) When a plurality of data having different bit widths are generated, the data output by the data generating means is (2 to the N-nth power: N). Is an integer equal to or greater than n) and is stored contiguously (3 × (2 to the Nth power)), and a bit determined by the bit width of the data output from the data generating means to the data stored in the memory. Arbitrary data is added to the position (4 × (2 of N
By providing multiple data expansion means to make the bit width, it is sufficient to have only enough buffer memory to store the generated data, and reduce the amount of memory by eliminating the extra buffer memory. Can be done, and its practical effect is great.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a memory control device according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram illustrating an operation of the memory control device according to the embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a conventional memory control device.

FIG. 4 is an explanatory diagram illustrating an operation of a conventional memory control device.

[Description of sign]

 101 data generating means 102 data input selecting means 103 to 104 memory 105 to 106 data expanding means 107 data output selecting means 108 data reading means 109 memory access right arbitration means 110 control signal generating means 111 shifter 112 to 114 selector

Claims (1)

[Claims] 1. Data generating means for generating a plurality of data having a bit width (3 × (2 to the nth power: n is an integer of 0 or more)), and the data generating means having different bit widths from the generated data. A plurality of pieces of data output by the means are stored concatenated for each piece of data (2 N−n power: N is an integer of n or more) (3 × (2 N power)) bit width memory; Data input selection means for selecting data output by the data generation means based on a data selection signal output by the data generation means and inputting the data to the memory; data read-out means for reading the data stored in the memory; and the memory A plurality of data expansion means for adding arbitrary data to the data stored in the data generator at the bit position determined by the bit width of the data output by the data generating means (4 × (2 N power)) And before And a data output selecting means for selecting data output from the data expanding means based on a data selection signal output from the data generating means and inputting the data to the data reading means.