JP3001763B2 - Image processing system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION This invention is related to <br/> to the image processing system to be displayed on the display device while updating the image data stored in the image memory address multiplex method, especially, high while realizing fast processing relates to an image processing system that realizes a compact structure at a low price.

An image processing system such as a computer graphic has an image memory of an address multiplex system which is accessed according to an address specified by a row address (ROW address) and a column address (COLUMN address). And a process of displaying the stored image data on a display device.

In order to make such an image processing system practical, high-speed processing must be realized,
It is necessary to realize a low-cost and compact configuration.

[0004]

2. Description of the Related Art In a conventional image processing system, a video RAM is used as an image memory of an address multiplex system.
(VRAM), the image data X
By mapping the Y address and the row / column address of the video RAM on a one-to-one basis, storing the image data in the video RAM and displaying the stored image data on a display device,
Is updated and displayed on the display device while updating the image data.

That is, as shown in FIG. 15, a configuration is employed in which a two-port video RAM capable of simultaneously executing both a random access process to a memory and a sequential access process for outputting to a display device is provided. In addition, as shown in FIG. 16, the drawing CP adopts a configuration in which the XY addresses of the image data and the row / column addresses of the video RAM are mapped one-to-one.
U rewrites some or all of the image data stored in the video RAM using the random access port of the video RAM, and the VRAM controller uses the sequential port of the video RAM to The image data stored in the video RAM is sequentially read, and a DA converter (DAC) converts the read image data from a digital signal to an analog signal to display the image data on a display device. That is the configuration.

[0006]

However, according to such a conventional technique, there is a problem that high-speed processing cannot be realized.

That is, the video RAM is a normal DRA
Similar to M, there is a characteristic that access when changing a row address is delayed. More specifically, when a clock frequency of 60 MHz is used, when writing to a video RAM, 150 ns is required from when a row address is newly set to when the first pixel is written.
After that, every time one pixel is written, 5 times
It takes 0 ns (3 clocks). Therefore, the time required for accessing n pixels on the same row address is “(100 + 50 × n) ns”. FIG.
A time chart of the video RAM memory access is shown in FIG. Here, RAS in the figure is a row address decision signal, CAS is a column address decision signal, and WE is a write enable signal.

If a triangle as shown in FIG. 18A is written in accordance with the pixel order shown in FIG. 18B, it takes 150 ns to write one pixel in the first stage.
Since it takes 250 ns to write the three pixels in the second stage, it takes 350 ns to write the five pixels in the third stage, it takes 450 ns to write the seven pixels in the fourth stage, and it takes 550 ns to write the nine pixels in the fifth stage. A long processing time such as 1750 ns in total is required.

Further, according to such a conventional technique, there is a problem that the price of the image processing system becomes high because a video RAM, which is more expensive than a normal DRAM such as a two-port memory, must be used. (2) Since a video RAM having the same memory capacity as that of a normal DRAM called a two-port memory (the same size and having only about 1/4 of the memory capacity) must be used, the image processing system cannot be made compact. There was a point.

The present invention was made in view of such circumstances, in the case that a configuration of displaying the updated while the display device image data stored in the image memory address multiplex system, high speed with implementing the process, for the purpose of provision of a new image processing system that realizes a compact structure at a low price.

[0011]

FIG. 1 to FIG. 3 show the principle configuration of an image processing system 1 equipped with the present invention.

An image processing system 1 of the present invention whose principle configuration is shown in FIG. 1 is a first image memory 10 of an address multiplex system having a plurality of banks having a capacity capable of storing one screen, and storing one screen. A second image memory 11 of an address multiplex type having a plurality of banks having a possible capacity, a first memory control unit 12 for executing access control processing of the first image memory 10, and a second image memory 11 Memory control unit 13 for executing the access control processing of the first and second image memories 1
Selection means 1 for outputting display image data by selecting one of the data outputs 1 and 12 as an input;
4, a display device 15 for displaying the display image data output by the selection means 14, and a drawing calculation mechanism 16 for calculating and outputting the XY address / data value of the drawing image data
And the synchronization signal as input, calculates the XY address of the display image data (calculates by incrementing X one by one and incrementing Y one by one according to the raster scan) and outputting An address calculation mechanism 17 is provided.

The first memory control unit 1
Reference numeral 2 denotes an address conversion means 18 for converting the XY address of the input image data into a row / column address of the first image memory 10, and a screen end signal generated from a synchronization signal. And a memory mode determining unit 19 for determining whether to write the drawing image data into the image memory 10 or read the display image data from the first image memory 10.

The second memory control unit 13
Sets the XY address of the input image data to the second
The address conversion means 20 for converting the image data into the row / column address of the image memory 11 and the drawing image data written in the second image memory 11 in response to the screen end signal generated from the synchronization signal. Memory mode determining means 21 for determining whether to read out display image data from the memory 11.

An image processing system 1 according to the present invention, whose principle configuration is shown in FIG. 2, comprises an address multiplex type image memory 30 composed of two banks, each of which has a capacity capable of storing one screen. A memory control unit 31 for executing access control processing of the image memory 30; a data adjusting unit 32 for generating display image data by adjusting image data output from the image memory 30; A display device 33 for displaying image data; and a drawing calculation mechanism 34 for calculating and outputting XY addresses / data values of drawn image data.
And an output address calculation mechanism 35 that receives a synchronization signal as input, calculates and outputs X and Y addresses of display image data.

The memory control unit 31
Address conversion means 36 for converting the X and Y addresses of the input image data into the row and column addresses of the image memory 30, and receiving the screen end signal generated from the synchronization signal, the drawing image data is stored in either bank. A bank mode determining means 37 for determining which bank is to be used for reading out the display image data; and when a continuous access to a different rectangular area on the same bank occurs, the rectangular mode of another bank is set prior to the access. Time slice control means 38 for controlling access to the area.

An image processing system 1 of the present invention whose principle configuration is shown in FIG. 3 is provided for storing image information other than display image data, and has an address of a plurality of banks having a capacity capable of storing one screen. A multiplex type non-display information image memory 40, a video RAM 41 for storing display image data, and a first memory control unit 42 for executing access control processing of the non-display information image memory 40
A second memory control unit 43 for executing an access control process for the video RAM 41; and a display device 44 for displaying display image data output from the video RAM 41.
And a drawing calculation mechanism 45 that calculates and outputs XY addresses / data values of the drawn image data.

Then, the first memory control unit 4
2 is provided with an address conversion means 46 for converting the XY address of the input image data into the row / column address of the non-display information image memory 40.

[0019]

In the image processing system 1 of the present invention whose principle configuration is shown in FIG. 1, when the memory mode determining means 19 receives the screen end signal, it writes the drawing image data in the first image memory 10 until then. Is determined, this time, it is determined to read the display image data from the first image memory 10, and until then, if it is determined to read the display image data from the first image memory 10, This time, it is determined to write the drawing image data in the first image memory 10.

On the other hand, when the memory mode determining means 19 determines writing,
It is determined that the display image data is to be read from the second image memory 11, and when the read is determined, it is determined that the drawing image data is to be written to the second image memory 11.

In response to the determination by the memory mode determining means 19 and 21, the address converting means 18 and 20 output the drawing calculating mechanism 16 when it is determined to write the drawing image data in the image memories 10 and 11. When the XY address is received and it is determined to read the display image data from the image memories 10 and 11, the XY address output from the output address calculating mechanism 17 is received.

Upon receiving the X and Y addresses of the image data, the address converting means 18 and 20 apply the image memory 10 and the image memory 10 to the rectangular area of the image data as shown in FIG.
By allocating 11 identical row addresses, allocating column addresses of the image memories 10 and 11 to each rectangular area in the order of raster scan, and allocating different banks to adjacent rectangular areas,
The received X and Y addresses are converted into row and column addresses of the image memories 10 and 11.

Since the image memories 10 and 11 are accessed according to the calculated row / column address, the selecting means 14 selects the image memories 10 and 11 for outputting the display image data, thereby displaying the display. The image data is displayed on the display device 15.

According to this configuration, when the image memories 10 and 11 are accessed, if the accesses are within the same rectangular area, they can be executed without changing the row address, and high-speed access can be realized. Become. Note that this effect alone can be realized by adopting a single bank configuration and allocating the same row address of the image memories 10 and 11 to the rectangular area of the image data as shown in FIG. is there.

When accessing the image memories 10 and 11 and the access extends over different rectangular areas, a different bank is allocated to adjacent rectangular areas of the same image data. Therefore, by using an image memory such as a synchronous DRAM, which can set a row address of another bank during access, it is possible to set a row address of another bank during access. High-speed access can be realized.

Thus, the image processing system 1 whose principle configuration is shown in FIG. 1 can access the image memories 10 and 11 at high speed. The image processing system 1 updates the drawing image data without using an expensive and large video RAM, and
5 can be displayed.

In the image processing system 1 of the present invention whose principle configuration is shown in FIG. 2, the bank mode determining means 37 receives the screen end signal, and when there are two banks, bank A and bank B, When it was decided to write the drawing image data to the bank A, it was decided to read the display image data from the bank A, and to decide to read the display image data from the bank B until then. At this time, it is determined that the drawing image data is to be written to the bank B.

On the other hand, the time slice control means 38 determines whether to receive the XY address output from the drawing calculation mechanism 34 or the XY address output from the output address calculation mechanism 35 according to an algorithm described later. When it is determined that the XY address output from the drawing calculation mechanism 34 is to be received, the output address calculation mechanism 35 is instructed to temporarily stop the transmission of the XY address and output from the output address calculation mechanism 35. When determining to receive the XY address, the drawing calculation mechanism 3
4 is instructed to temporarily stop sending the X and Y addresses.

Upon receiving the XY address of either the drawing image data or the display image data according to the control processing of the time slice control means 38, the address conversion means 36, as shown in FIG. The same row address of the image memory 30 is assigned to the rectangular area of the data, and the column address of the image memory 30 is assigned to each rectangular area in accordance with the raster scan order. By allocating the same bank, the received XY address is converted to the row / column address of the image memory 30.

When performing such address conversion processing, the time slice control means 38, when continuous access to different rectangular areas on the same bank occurs, prior to the access, to the other bank. By controlling to access the rectangular area, it is determined whether to receive the XY address output from the drawing calculation mechanism 34 or the XY address output from the output address calculation mechanism 35.

That is, X output from the drawing calculation mechanism 34
When receiving the Y address, if the XY address moves to a different rectangular area, the reception of the XY address is temporarily stopped, and the XY output from the output address calculating mechanism 35 is returned. X / Y output from the output address calculation mechanism 35
If the XY address moves to a different rectangular area while receiving the address, the reception of the XY address is temporarily stopped, and this time, the drawing calculation mechanism 34
Is determined to receive the X and Y addresses output by the.

In accordance with the row / column address calculated in this way, writing of the drawing image data and reading of the display image data are alternately performed at the boundary of the rectangular area. That is, the display image data output from the image memory 30 is not continuously output, but is output while being sandwiched between the rendered image data. The output display image data is extracted, converted into continuous data, and displayed on the display device 33.

According to this configuration, when accessing the image memory 30, if the access is within the same rectangular area, the access can be performed without changing the row address, and high-speed access can be realized.

When the image memory 30 is accessed, if the access straddles a different rectangular area, two banks are switched in a time-division manner at the boundary of the rectangular area. By using an image memory such as a synchronous DRAM that allows a row address of another bank to be set during access, it is possible to set a row address of another bank during access, thereby achieving high-speed access. It can be realized.

As described above, the image processing system 1 whose principle configuration is shown in FIG. 2 can access the image memory 30 at high speed. The image processing system 1 does not use an expensive and large video RAM,
The drawing image data can be displayed on the display device 33 while being updated.

In the image processing system 1 of the present invention whose principle configuration is shown in FIG.
1, the image data is updated and displayed on the display device 44 while the image data is updated. However, the non-display information such as the depth information of the drawn image data output from the drawing calculation One memory control unit 42 is processed to receive it.

When the XY address of the non-display information is received, the address conversion means 46, as shown in FIG. 4, assigns the same row address of the non-display information image memory 40 to the rectangular area of the image data. In addition to the allocation, the column addresses of the non-display information image memory 40 are allocated to each rectangular area according to the raster scan order, and different banks are allocated to adjacent rectangular areas. Is converted to the row / column address of the non-display information image memory 40.

The non-display information image memory 40 is accessed in accordance with the calculated row / column address. For the same reason as described with reference to FIG. 1, this access is realized at high speed.

As described above, the image processing system 1 whose principle configuration is shown in FIG. 3 can write the non-display information of the drawn image data into the non-display information image memory 40 at high speed.
It can be read.

[0040]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to embodiments. FIG. 7 shows an embodiment of the image processing system 1 of the present invention whose principle configuration is shown in FIG. In the figure, the same components as those described in FIG. 1 are denoted by the same reference numerals.

Reference numeral 100 denotes a digital signal processor, which expands a first memory control unit 12, a second memory control unit 13, a drawing calculation mechanism 16, and an output address calculation mechanism 17. 10a is the first
Synchronous DRA corresponding to the image memory 10 of FIG.
M and 11a are second synchronous DRAMs corresponding to the second image memory 11, and 14a is a selector corresponding to the selection means 14. Reference numeral 22 denotes a DA converter that converts display image data output from the selector 14a from a digital signal to an analog signal, and reference numeral 23 denotes a synchronization signal generation mechanism that generates a synchronization signal.

Prior to the description of this embodiment, a synchronous DRAM will be described. Synchronous DRAM
Is composed of two banks, the access for changing the row address and the access for changing the read and the write are slow, but the read access and the write access for several words or more of the same row address are very fast. The feature is that the row address of another bank can be changed while accessing a bank, so that the access speed of a different row address can be improved. Then, it has a feature of automatically accessing a column address that counts up one by one from the designated column address.

For example, as shown in FIG. 8, when the row address a / column address a1 of the A bank is set, 1
Write access is performed for the four column addresses that count up by one. During this time, the row address b of the bank B can be set, and then, when the column address a2 of the bank A is set, one by one Write access is performed for the four column addresses that count up, and subsequently, when the column address b1 of bank B is set, write access is performed for the column address that counts up by one. In other words, while accessing a certain bank, the row address of another bank can be changed, and a column address that counts up one by one from the specified column address is automatically accessed. It is doing.

Next, a description will be given of the embodiment of FIG. In the embodiment of FIG. 7, one of the synchronous DRAMs 10a and 11a is used as described with reference to the principle configuration diagram of FIG.
Is used for access from the drawing calculation mechanism 16, and the other synchronous DRAMs 10a and 11a are used for access from the output address calculation mechanism 17, and the roles of the two synchronous DRAMs 10a and 11a are written by the drawing calculation mechanism 16 to complete one screen. The synchronous DRAM 10 prepared as a double buffer is changed by
a, 11a, the display image data is read out, and the display device 15 is read out.
Is displayed.

Each synchronous DRAM 10a, 11a
Has the capacity to store one screen, so for example,
When one screen has 2048 × 1024 pixels, two banks are configured to have a capacity of 2048 × 1024 pixels.

The synchronous DRAMs 10a and 11a
In response, the first and second memory control units 12, 1
As described with reference to FIG. 1, the address conversion units 18 and 19 of the third unit 3 assign the same row address of the synchronous DRAMs 10a and 11a to the rectangular area of the image data and perform raster scan on each rectangular area. , The column addresses of the synchronous DRAMs 10a and 11a are allocated in accordance with the order of X, and different banks are allocated to adjacent rectangular areas.
A process for converting the Y address to the row / column address of the synchronous DRAMs 10a and 11a is executed.

FIG. 9 shows an embodiment of this memory mapping. In this embodiment, one rectangular area is 32 ×
The configuration of 32 pixels is adopted. Such memory mapping is, specifically,

[0048]

(Equation 1)

Will be realized in accordance with here,
In the equation 1, "RA" is a row address, and "BA".
Represents a bank address, “CA” represents a column address, “BA = 0” represents bank A, and “BA = 1” represents bank B.

FIG. 10 shows a hardware configuration of the address conversion means 18 and 19 for realizing the equation (1). Here, X (0) is the least significant bit of the X address, X (1
0) is the most significant bit of the X address, Y (0) is the least significant bit of the Y address, the most significant bit of the Y address of Y (9), R
OW (0) represents the least significant bit of the row address, ROW (9) represents the most significant bit of the row address, COLUMN (0) represents the least significant bit of the column address, and COLUMN (9) represents the most significant bit of the column address. I have.

With this hardware configuration, for example,
When the XY address of the image data “X = 64, Y = 32” is received, “X = 00001000000, Y = 00001000”
According to “00”, the address conversion units 18 and 19 determine “row address = 0000100001, column address = 0000000000,
Bank address = 1 ", that is," row address = 3
An address conversion process for realizing the memory mapping shown in FIG. 9 is executed, for example, "3, column address = 0, bank address = B".

According to the row / column address calculated by the address conversion processing, the synchronous DRAM 1
Although 0a and 11a are accessed, image data drawn by computer graphics or the like usually has the property of being localized, and therefore often falls within the same rectangular area. Since the same row address is allocated in the rectangular area, the synchronous DRAM 10 can be used without changing the row address.
The write accesses a and 11a are realized.

When the display image data is output, the same rectangular area is scanned in the horizontal direction. Since the same row address is allocated in the rectangular area, The read access to the synchronous DRAMs 10a and 11a is realized without changing the row address. In addition, since the configuration is such that the column addresses of the synchronous DRAMs 10a and 11a are assigned to each rectangular area in the order of raster scan, the synchronous DRAM 10a is used.
According to the column address continuous access function of the a and 11a, an extremely high-speed access is realized.

Since a different bank is allocated to adjacent rectangular areas of the same image data, write access shifts to the adjacent rectangular area by drawing image data straddling the adjacent rectangular area. Also, when read access shifts to an adjacent rectangular area according to a raster scan, the row address of another bank can be set during access according to the above-described row address setting function of the synchronous DRAMs 10a and 11a. , A substantially continuous access is realized.

On the other hand, the selector 14a switches one of the synchronous DRAMs 10a,
Since the display image data is output from 1a, the synchronous DRAMs 10a and 11a which output the display image data are selected in accordance with the screen end signal generated from the synchronization signal, and the output display image data is converted to the DA converter 22. And receives this output, and receives it from the DA converter 2
2 converts the display image data output from the selector 14a from a digital signal to an analog signal and displays the data on the display device 15.

As described above, the image processing system 1 shown in FIG. 7 has two synchronous DRAMs having a one-port configuration.
10a and 11a, the synchronous DR of the writing destination of the drawing image data is set in units of one screen.
By adopting a configuration in which the AMs 10a and 11a and the synchronous DRAMs 10a and 11a from which the display image data is read out are changed, a configuration in which the drawing image data is updated and displayed on the display device 15 is adopted, which is expensive. The image data can be displayed on the display device 15 while updating the drawing image data without using a large video RAM.

FIG. 11 shows an embodiment of the image processing system 1 of the present invention, whose principle configuration is shown in FIG. In the figure,
The same components as those described in FIG. 2 are denoted by the same symbols.

Reference numeral 100 denotes a digital signal processor, which is a memory control unit 31, a drawing calculation mechanism 3
4 and the output address calculation mechanism 35. 30a is a synchronous D corresponding to the image memory 30
The RAM 32 a is a speed conversion buffer corresponding to the data adjusting unit 32. Reference numeral 39 denotes a DA converter, which converts display image data generated by the speed conversion buffer 32a from a digital signal to an analog signal, and reference numeral 40 denotes a synchronization signal generation mechanism, which generates a synchronization signal.

In the embodiment of FIG. 11, if the two banks of the synchronous DRAM 30a are represented by banks A and B as described with reference to the principle configuration diagram of FIG. 2, one of the banks A and B is drawn and calculated. For access from the mechanism 34,
The other banks A and B are used for access from the output address calculation mechanism 35, and the roles of the two banks A and B are changed at the stage when the drawing calculation mechanism 34 has finished writing one screen, thereby forming a double buffer. The drawing image data is written into the two banks A and B of the prepared synchronous DRAM 30a, and the display image data is read out and displayed on the display device 33.

Each of the banks A and B of the synchronous DRAM 30a has a capacity capable of storing one screen. For example, when one screen has 2048 × 1024 pixels, each bank A and B has a capacity of 2048 × 1024. It is configured to have a capacity for a pixel.

In response to the synchronous DRAM 30a, the address conversion means 36 included in the memory control unit 31 allocates the same row address of the synchronous DRAM 30 to the rectangular area of the image data as described with reference to FIG. A column address of the synchronous DRAM 30a is allocated to each rectangular area in the order of raster scan, and further, the same bank is allocated to each rectangular area of the same image data, so that the received XY address is synchronous. A process for converting to a row / column address of the DRAM 30a is executed.

FIG. 12 shows an embodiment of this memory mapping. In this embodiment, one rectangular area is defined as 32
It has a configuration of × 32 pixels. Such memory mapping is, specifically,

[0063]

(Equation 2)

This is realized according to here,
[Equation 2] In the equation, "RA" is a row address, and "CA"
Represents a column address. When accessing bank A, the most significant bit of the Y address is set to "0", and when accessing bank B, "1" is set to the most significant bit of the Y address.

FIG. 13 shows a hardware configuration of the address conversion means 36 for realizing the equation (2). Here, X (0) is the least significant bit of the X address, X (10) is the most significant bit of the X address, Y (0) is the least significant bit of the Y address, and the most significant bit of the Y address of Y (9). , ROW (0)
Is the least significant bit of the row address, ROW (10) is the most significant bit of the row address, COLUMN (0) is the least significant bit of the column address, and COLUMN (9) is the most significant bit of the column address.

With this hardware configuration, for example,
When the XY address of the image data “X = 32, Y = 32” is received, when accessing bank A,
In accordance with “X = 00000100000, Y = 000000100000”, the address conversion means 36 determines “row address = 00001000001,
Column address = 0000000000, bank address = 0 ”,
That is, “row address = 65, column address =
An address conversion process for realizing the memory mapping shown in FIG. 12 is executed, for example, "0, bank address = A".

According to the row / column address calculated by the address conversion process, the synchronous DRAM 3
0a is accessed, but usually, image data drawn by computer graphics or the like often has the property of being localized, so that it often fits in the same rectangular area. Since the same row address is allocated in the area, the write access to the synchronous DRAM 30a is realized without changing the row address.

When the display image data is output, the same rectangular area is scanned in the horizontal direction. Since the same row address is assigned to the rectangular area, each rectangular area has: The read access of the synchronous DRAM 30a is realized without changing the row address. Moreover, for each rectangular area, synchronous DRA is performed in accordance with the raster scan order.
Since the configuration of allocating the column address of the M30a is adopted, an extremely high-speed access is realized according to the above-described column address continuous access function of the synchronous DRAM 30a.

When the synchronous DRAM 30a is accessed, if the access extends over a different rectangular area, the two banks are switched in a time-division manner with the rectangular area as a boundary. The drawing image data does not fit in the same rectangular area, and the drawing image data straddles the adjacent rectangular area, so that write access shifts to the adjacent rectangular area, or read access shifts to the adjacent rectangular area according to raster scanning. In some cases, according to the above-described row address setting function of the synchronous DRAM 30a, a row address of another bank can be set during access, and substantially continuous access is realized.

According to the embodiment of FIG. 11, the writing of the drawing image data and the reading of the display image data are alternately performed in a time-division manner, so that the display image data output from the synchronous DRAM 30a is Are not continuously output, but are output sandwiched between drawing image data.

From this, the speed conversion buffer 32a extracts the display image data output from the synchronous DRAM 30a, converts it into continuous data,
Will be displayed. For example, with a capacity of 2 lines,
During one-line scanning of the display device 33, display image data output from the synchronous DRAM 30a is converted into continuous data and stored in another buffer for one line. It outputs according to the frequency. According to such a processing configuration, in the embodiment of FIG. 7, if the memory access speed is lower than the display frequency, correct image data cannot be output, and if the memory access speed is higher than the display frequency, However, according to the embodiment of FIG. 11, the ratio of the display output access to the total memory access can be freely set, so that the maximum drawing performance can be obtained. There are advantages.

As described above, the image processing system 1 shown in FIG. 11 employs a configuration including the synchronous DRAM 30a having a two-bank configuration employing a one-port configuration, and using a unit of one screen as a unit for writing drawing image data. Banks and
Since the display image data is updated and displayed on the display device 33 by changing the read-out bank of the display image data, the drawing image data is updated without using a large and expensive video RAM. The image data can be displayed on the display device 33 while being updated.

FIG. 14 shows an embodiment of the image processing system 1 of the present invention, whose principle configuration is shown in FIG. In the figure,
The same components as those described in FIG. 3 are denoted by the same symbols.

Reference numeral 100 denotes a digital signal processor, which expands the first memory control unit 42, the second memory control unit 43, and the drawing calculation mechanism 45. Reference numeral 40a denotes a synchronous DRAM corresponding to the non-display information image memory 40; 47, a DA converter for converting display image data output from the video RAM 41 from a digital signal to an analog signal;
Is a synchronization signal generating mechanism for generating a synchronization signal.

The image processing system 1 of this embodiment has a configuration in which the video RAM 41 is provided and the image data is updated and displayed on the display device 44 as in the prior art. The depth information and the control information that are not output to the CPU are stored in the synchronous DRAM 40a.

That is, in the case of the embodiment shown in FIG. 7, the synchronous DR output to the display device 15 is used.
Since the AMs 10a and 11a cannot be accessed from the drawing calculation mechanism 16, in order to solve this, in this embodiment, a two-port video RAM 4 is used for an image plane requiring display output access.
1 and the planes that do not require display output access are stored in the synchronous DRAM 40a. In addition, in many cases, only the light is sufficient for the image plane.
In many cases, data is read once and then written.

When the XY address of such non-display information is received from the drawing calculation mechanism 45, the address conversion means 46 executes the same address conversion processing as the address conversion means 18 and 19 in the embodiment of FIG. Then, according to the row / column address obtained as a result, the synchronous DRAM 40a
Will be accessed at high speed.

In this way, the image processing system 1 shown in FIG. 14 can write non-display information of the drawn image data into the synchronous DRAM 40a at a high speed, and can read out the non-display information from the synchronous DRAM 40a at a high speed.

The present invention has been described with reference to the illustrated embodiments.
The present invention is not limited to this. For example, in the embodiments, the present invention is disclosed by using a synchronous DRAM, but the present invention is not limited to this.

For example, if a triangle as shown in FIG. 13 (a) is written in accordance with the pixel order shown in FIG. 13 (b), as described above, if the prior art is 1750 ns,
If what is needed is described in the case where the triangles fit in the same rectangular area, the present invention does not require changing the row address, so that the access speed can be reduced to 1350 ns even at the same access speed as the video RAM. . In addition,
In this case, if a synchronous DRAM is used, continuous access is possible even when this triangle does not fit in the same rectangular area, and one access can be made for one clock (16.7 ns). The time required for access is “16.7 × number of pixels = 16.7 × 25 = 418n”
s ".

[0081]

As described above, according to the present invention,
The address multiplex type image memory can be accessed at high speed. Then, while realizing high-speed processing, image data stored in the address multiplex type image memory can be updated and displayed on the display device without using an expensive and large video RAM.

[Brief description of the drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a principle configuration diagram of the present invention.

FIG. 3 is a diagram illustrating the principle of the present invention;

FIG. 4 is an explanatory diagram of memory mapping according to the present invention.

FIG. 5 is an explanatory diagram of memory mapping according to the present invention.

FIG. 6 is an explanatory diagram of memory mapping according to the present invention.

FIG. 7 is an embodiment of the present invention.

FIG. 8 is an explanatory diagram of a synchronous DRAM.

FIG. 9 is an example of a memory mapping.

FIG. 10 shows an embodiment of an address conversion means.

FIG. 11 is an embodiment of the present invention.

FIG. 12 is an example of a memory mapping.

FIG. 13 shows an embodiment of an address conversion means.

FIG. 14 is an embodiment of the present invention.

FIG. 15 is an explanatory diagram of a conventional technique.

FIG. 16 is an explanatory diagram of a conventional technique.

FIG. 17 is a time chart of memory access of a video RAM.

FIG. 18 is an example of an access order of image data.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Image processing system 10 1st image memory 11 2nd image memory 12 1st memory control unit 13 2nd memory control unit 14 Selection means 15 Display device 16 Drawing calculation mechanism 17 Output address calculation mechanism 18 Address conversion means 19 Memory mode determination means 20 Address conversion means 21 Memory mode determination means

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-2-289095 (JP, A) JP-A-3-144778 (JP, A) JP-A-63-2855591 (JP, A) Nikkei Electronics, Nikkei BP Issued May 11, 1992, No. 533, p. 143 −147 (58) Field surveyed (Int.Cl. ⁷ , DB name) G06T 1/60 G06F 12/02 570

Claims (3)

(57) [Claims] 1. An image processing system for updating image data stored in an address multiplex type image memory and displaying the updated image data on a display device, wherein the image memory has a plurality of banks having a capacity capable of storing one screen. Two image memories are provided. The image memory is provided in correspondence with the image memory. The same row address is assigned to a rectangular area of image data, and different banks are assigned to adjacent rectangular areas. A memory control unit that calculates the storage address of the image data, and the memory control unit writes drawing image data to one of the image memories and reads display image data from the other image memory in units of one screen. It adopts a configuration that repeats while changing the above image memory An image processing system, further comprising: a selection unit that selects the image memory for outputting display image data and sends the display image data to a display device. 2. An image processing system for displaying image data stored in an address multiplex type image memory on a display device while updating the image data, the image memory comprising two banks as the image memory,
One image memory in which each bank has a capacity capable of storing one screen is prepared, and the same row address is allocated to a rectangular area of image data, and the same bank is allocated to each rectangular area of the same image data. According to the address conversion, the storage address of the image memory is calculated, and when continuous access to different rectangular areas on the same bank occurs,
A memory control unit for switching an access destination bank in accordance with a time slice control for accessing a rectangular area of another bank prior to the access; and the memory control unit writes drawing image data to one bank, and Reading of the display image data from the bank is repeated while changing the bank in units of one screen, and further, the display image data to be read at time intervals is extracted by the time slice control and converted into continuous data. An image processing system comprising: a data adjusting unit that sends the data to a display device. 3. The method of claim 1 or 2, wherein the image processing system, an image memory, the two banks synchronous DRA
An image processing system characterized in that the image processing system is configured to use M.