JPH07220059A - Picture memory access system and picture processing system - Google Patents

Abstract

PURPOSE:To provide the picture processing system where picture data stored in a picture memory in the address multiplex system is displayed on a display device while being updated at a high speed without using a video RAM. CONSTITUTION:Two picture memories 10 and 11 of plural banks each of which has the one-picture capacity are prepared, and two control units 12 and 13 are provided which have address conversion means which convert X and Y addresses of picture data to addresses of picture memories 10 and 11 while assigning the same row address to a square area of picture data, and picture data write to one picture memory by one control unit and picture data read from the other picture memory by the other control unit are repeated while exchanging the picture memories with one picture as a unit, and a selecting means is provided which selects display picture data outputted from picture memories to send them to a display device 15.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image memory access method for performing access control of an address multiplex type image memory and a display device while updating image data stored in the address multiplex type image memory. More particularly, the present invention relates to an image memory access method that realizes high-speed processing and an image processing system that realizes high-speed processing and a low-cost and compact configuration.

An image processing system such as a computer graphic is provided with an image memory of an address multiplex system which is accessed according to an address defined by a row address (ROW address) and a column address (COLUMN address). The image data is stored in and the stored image data is displayed on the display device.

In order to make such an image processing system practical, in addition to realizing high-speed processing,
It is necessary to realize a low-cost and compact configuration.

[0004]

2. Description of the Related Art In a conventional image processing system, a video RAM is used as an address multiplex type image memory.
(VRAM) is adopted, and X of image data
The Y-address and the row / column address of the video RAM are mapped one-to-one, while the image data is stored in this video RAM, and the stored image data is displayed on the display device.
The configuration is such that the image data stored in is displayed on the display device while being updated.

That is, as shown in FIG. 15, a structure having a 2-port video RAM capable of simultaneously executing both random access processing to a memory and sequential access processing for outputting to a display device is adopted. At the same time, as shown in FIG. 16, the drawing CP has a configuration in which the X and Y addresses of the image data and the row and column addresses of the video RAM are mapped one to one.
U uses the random access port of this video RAM to rewrite part or all of the image data stored in this video RAM, and the VRAM controller uses the sequential port of this video RAM. The image data stored in the video RAM is read out sequentially, and the DA converter (DAC) converts the read image data from a digital signal into an analog signal to be displayed on the display device. That is the structure adopted.

[0006]

However, according to such a conventional technique, there is a problem that high-speed processing cannot be realized.

That is, the video RAM is a normal DRA.
Similar to M, it has a characteristic that access when changing the row address is delayed. More specifically, when a clock frequency of 60 MHz is used, when writing to the video RAM, it takes 150 ns from newly setting the row address to writing the first pixel.
It takes 5 seconds for each pixel to be written.
It takes 0 ns (3 clocks). Therefore, the time required to access n pixels on the same row address is “(100 + 50 × n) ns”. FIG. 17
A time chart of memory access of this video RAM is shown in FIG. In the figure, RAS is a row address confirmation signal, CAS is a column address confirmation signal, and WE is a write enable signal.

If a triangle as shown in FIG. 18A is written according to the pixel order shown in FIG. 18B, it takes 150 ns to write one pixel in the first stage.
It takes 250 ns to write the 3rd pixel in the 2nd row, 350ns to write the 5th pixel in the 3rd row, 450ns to write the 7th pixel in the 4th row, and 550ns to write the 9th pixel in the 5th row. A long processing time of 1750 ns in total is required.

Further, according to such a conventional technique, since a video RAM, which is more expensive than a normal DRAM called a 2-port memory, must be used, there is a problem that the price of the image processing system becomes high. The problem that the image processing system cannot be made compact because a 2-port memory, which has a smaller memory capacity than a normal DRAM, such as a video RAM (which has the same size and only has a memory capacity of about 1/4), must be used. There was a point.

The present invention has been made in view of the above circumstances, and provides a new image memory access system for realizing high-speed processing when executing access control of an image memory of the address multiplex system. In addition, while processing the image data stored in the address multiplex type image memory while displaying the image data on the display device while updating the image data, high-speed processing is realized, and a low-cost and compact configuration is realized. The purpose is to provide a new image processing system.

[0011]

1 to 3 show the principle configuration of an image processing system 1 including the present invention.

An image processing system 1 of the present invention, the principle configuration of which is shown in FIG. 1, includes a first image memory 10 of an address multiplex system of a plurality of banks having a capacity capable of storing one screen, and one screen storage. A second image memory 11 of an address multiplex system having a plurality of banks having a possible capacity, a first memory control unit 12 that executes access control processing of the first image memory 10, and a second image memory 11 Second memory control unit 13 for executing the access control processing of the first and second image memories 1
Selection means 1 for outputting display image data by selecting one of the data outputs 1 and 12 as an input
4, a display device 15 for displaying the display image data output by the selection means 14, and a drawing calculation mechanism 16 for calculating and outputting the X / Y address / data value of the drawing image data.
And an output that calculates the X / Y address of the display image data (calculates by incrementing X one by one and incrementing Y one by one according to the raster scan) using the synchronization signal as an input. An address calculation mechanism 17 is provided.

Then, the first memory control unit 1
2 receives the address conversion means 18 for converting the X / Y address of the input image data into the row / column address of the first image memory 10, and the screen end signal generated from the synchronization signal. Memory mode determining means 19 for determining whether to write drawing image data in the image memory 10 or to read display image data from the first image memory 10.

Further, the second memory control unit 13
Specifies the X / Y address of the input image data as the second
Address conversion means 20 for converting into a row / column address of the image memory 11 and a screen end signal generated from the synchronization signal to write drawing image data in the second image memory 11 or the second image memory The memory mode determining unit 21 determines whether to read the display image data from the display unit 11.

The image processing system 1 of the present invention, the principle configuration of which is shown in FIG. 2, is composed of two banks, and an image memory 30 of an address multiplex system having a capacity capable of storing one screen in each bank, A memory control unit 31 that executes access control processing of the image memory 30, a data adjusting unit 32 that generates display image data by adjusting the image data output from the image memory 30, and a display that the data adjusting unit 32 generates. A display device 33 for displaying image data and a drawing calculation mechanism 34 for calculating and outputting X / Y addresses / data values of drawn image data.
And an output address calculation mechanism 35 which receives the synchronization signal as input and calculates and outputs the X and Y addresses of the display image data.

The memory control unit 31 is
The address conversion means 36 for converting the X / Y address of the input image data into the row / column address of the image memory 30, and the screen end signal generated from the synchronization signal, receive the drawing image data in which bank. The bank mode determining means 37 for determining which bank the display image data is to be written from and to read the display image data, and when continuous access to different rectangular areas on the same bank occurs, the rectangle of another bank is preceded by the access. And a time slice control means 38 for controlling to access the area.

The image processing system 1 of the present invention whose principle configuration is shown in FIG. 3 is provided for storing image information other than display image data and has an address of a plurality of banks having a capacity capable of storing one screen. Multiplex type non-display information image memory 40, video RAM 41 for storing display image data, and first memory control unit 42 for executing access control processing of non-display information image memory 40.
A second memory control unit 43 for executing access control processing of the video RAM 41, and a display device 44 for displaying display image data output from the video RAM 41.
And a drawing calculation mechanism 45 for calculating and outputting X / Y addresses / data values of drawn image data.

Then, the first memory control unit 4
2 includes an address conversion unit 46 that converts the X / Y address of the input image data into a row / column address of the non-display information image memory 40.

[0019]

In the image processing system 1 of the present invention whose principle configuration is shown in FIG. 1, when the memory mode determination means 19 receives the screen end signal, it writes the drawn image data in the first image memory 10 until then. When it was decided to read the display image data from the first image memory 10, and when it was decided to read the display image data from the first image memory 10 until then, This time, it is decided to write the drawn image data in the first image memory 10.

On the other hand, the memory mode determining means 21 determines when the memory mode determining means 19 determines writing.
It is decided to read the display image data from the second image memory 11, and when the reading is decided, it is decided to write the drawing image data in the second image memory 11.

In response to the decision made by the memory mode decision means 19 and 21, the address conversion means 18 and 20 output the drawing calculation mechanism 16 when it is decided to write the drawn image data in the image memories 10 and 11. When it is decided to receive the X / Y address and read the display image data from the image memories 10 and 11, the X / Y address output from the output address calculation mechanism 17 is received.

When the X / Y addresses of the image data are received, the address converting means 18, 20 send the image memory 10, 20, to the rectangular area of the image data as shown in FIG.
By assigning 11 identical row addresses, assigning column addresses of the image memories 10 and 11 to each rectangular area in the order of raster scanning, and assigning different banks to adjacent rectangular areas,
The received XY addresses are converted into row / column addresses of the image memories 10 and 11.

Since the image memories 10 and 11 are accessed according to the calculated row and column addresses, the selecting means 14 selects the image memories 10 and 11 to which the display image data is output, thereby displaying the display. The image data is displayed on the display device 15.

According to this configuration, when the image memories 10 and 11 are accessed, if the access is within the same rectangular area, it can be executed without changing the row address, and high speed access can be realized. Become. Note that this effect alone can be realized by adopting a single bank configuration and allocating the same row address of the image memories 10 and 11 to the rectangular area of the image data as shown in FIG. is there.

When the image memories 10 and 11 are accessed over different rectangular areas, different banks are assigned to adjacent rectangular areas of the same image data. Therefore, it is possible to set the row address of another bank during access by using an image memory such as a synchronous DRAM that can set the row address of another bank during access. High-speed access can be realized.

In this way, the image processing system 1 whose principle configuration is shown in FIG. 1 can access the image memories 10 and 11 at high speed. Then, the image processing system 1 does not use an expensive and large video RAM and updates the drawn image data while displaying the display device 1.
5 can be displayed.

In the image processing system 1 of the present invention whose principle configuration is shown in FIG. 2, when the bank mode determining means 37 receives the screen end signal, when there are two banks, bank A and bank B, until then. , It was decided to write the drawing image data to the bank A, this time, it was decided to read the display image data from the bank A, and until then, it was decided to read the display image data from the bank B. At this time, it is decided to write the drawn image data in the bank B this time.

On the other hand, the time slice control means 38 determines whether to receive the X / Y address output from the drawing calculation mechanism 34 or the X / Y address output from the output address calculation mechanism 35 according to an algorithm described later. When deciding to receive the X / Y address output from the drawing calculation mechanism 34, the output address calculation mechanism 35 is instructed to suspend the sending of the X / Y address, and the output address calculation mechanism 35 outputs. When it is decided to receive the X / Y address, the drawing calculation mechanism 3
4 is instructed to temporarily stop transmission of the X and Y addresses.

According to the control process of the time slice control means 38, when the X / Y address of the image data of either the drawn image data or the display image data is received, the address conversion means 36, as shown in FIG. The same row address of the image memory 30 is allocated to the rectangular area of the data, the column address of the image memory 30 is allocated to each rectangular area in the order of the raster scan, and the rectangular area of the same image data is allocated to each rectangular area. By allocating the same bank to the same, the received XY addresses are converted into row / column addresses of the image memory 30.

When performing such address conversion processing, the time slice control means 38, when continuous accesses to different rectangular areas on the same bank occur, prior to the access, the time slice control means 38 of other banks. By controlling to access the rectangular area, it is determined whether the X / Y address output by the drawing calculation mechanism 34 or the X / Y address output by the output address calculation mechanism 35 is received.

That is, X output from the drawing calculation mechanism 34
When receiving the Y address, when the X / Y address moves to a different rectangular area, the reception of the X / Y address is temporarily stopped, and this time, the X / Y output by the output address calculation mechanism 35 is output. XY output by the output address calculation mechanism 35 after determining to receive the address
When the X / Y address moves to a different rectangular area while receiving the address, the reception of the X / Y address is temporarily stopped, and this time, the drawing calculation mechanism 34
It is decided to receive the X and Y addresses output by.

According to the row / column address thus calculated, writing of the drawing image data and reading of the display image data are alternately executed with the rectangular area as a boundary. That is, the display image data output from the image memory 30 is not output continuously, but is sandwiched between the drawn image data and output. The output display image data is extracted, converted into continuous data, and displayed on the display device 33.

According to this configuration, when the image memory 30 is accessed, if the access is within the same rectangular area, it can be executed without changing the row address, and high speed access can be realized.

Then, when the image memory 30 is accessed, if the access extends over different rectangular areas, the two banks are time-divisionally switched with the rectangular area as a boundary. By using an image memory such as a synchronous DRAM that can set the row address of another bank during access, it becomes possible to set the row address of another bank during access, thus achieving high-speed access. It will be possible.

In this way, the image processing system 1 whose principle configuration is shown in FIG. 2 can access the image memory 30 at high speed. The image processing system 1 does not use an expensive and large video RAM,
The drawn image data can be displayed on the display device 33 while being updated.

In the image processing system 1 of the present invention whose principle configuration is shown in FIG. 3, the video RAM 4 is used as in the prior art.
1 is provided, the image data is updated and displayed on the display device 44. However, regarding non-display information such as depth information that the drawing image data output by the drawing calculation mechanism 45 has, The memory control unit 42 of No. 1 receives the data.

When the X / Y address of the non-display information is received, the address converting means 46 sets the same row address of the non-display information image memory 40 to the rectangular area of the image data as shown in FIG. Along with the allocation, the column addresses of the non-display information image memory 40 are allocated to each rectangular area in the order of the raster scan, and further, different banks are allocated to the adjacent rectangular areas. Is converted into a row / column address of the non-display information image memory 40.

The non-display information image memory 40 is accessed according to the calculated row / column address, but this access is realized at high speed for the same reason as described with reference to FIG.

In this way, the image processing system 1 whose principle configuration is shown in FIG. 3 can write the non-display information of the drawn image data into the non-display information image memory 40 at high speed.
You can read it.

[0040]

EXAMPLES The present invention will be described in detail below with reference to examples. FIG. 7 shows an embodiment of the image processing system 1 of the present invention whose principle configuration is shown in FIG. In the figure, the same components as those described in FIG. 1 are indicated by the same symbols.

Reference numeral 100 denotes a digital signal processor which expands the first memory control unit 12, the second memory control unit 13, the drawing calculation mechanism 16 and the output address calculation mechanism 17. 10a is the first
First synchronous DRA corresponding to the image memory 10 of
M and 11a are second synchronous DRAMs corresponding to the second image memory 11, and 14a is a selector corresponding to the selecting means 14. Reference numeral 22 is a DA converter, which converts the display image data output from the selector 14a from a digital signal to an analog signal, and 23 is a synchronization signal generation mechanism, which generates a synchronization signal.

Before the description of this embodiment, a synchronous DRAM will be described. Synchronous DRAM
Is composed of two banks, the access to change the row address and the access to change the read and write are slow, but the read access and the write access for several words or more of the same row address are very fast. Since the row address of another bank can be changed while the bank is being accessed, the access speed of a different row address can be improved. Then, it has a feature that a column address which is incremented by one from the designated column address is automatically accessed.

For example, as shown in FIG. 8, when the row address a / column address a1 of bank A is set, 1
When a write access is executed to four column addresses that are incremented by one, during which the row address b of bank B can be set, and subsequently the column address a2 of bank A is set, one by one Write access is performed to the four column addresses that are counting up, and subsequently, when the column address b1 of bank B is set, write access is performed to the column address that is incrementing by one. In this way, the row address of another bank can be changed while accessing one bank, and the column address that increments by 1 from the designated column address is automatically accessed. I am doing it.

Next, a description will be given of the embodiment shown in FIG. In the embodiment of FIG. 7, one of the synchronous DRAMs 10a and 11a, as described in the principle configuration diagram of FIG.
Is used for access from the drawing calculation mechanism 16 and the other synchronous DRAM 10a, 11a is used for access from the output address calculation mechanism 17, the drawing calculation mechanism 16 finishes writing one screen for the role of these two synchronous DRAMs 10a, 11a. Synchronous DRAM 10 prepared as a double buffer by changing over at different stages
a and 11a, while writing the drawing image data, the display image data is read out to display device 15
It is processed so that it is displayed in.

Each synchronous DRAM 10a, 11a
Has the capacity to store one screen,
When one screen has 2048 × 1024 pixels, two banks are configured to have a capacity of 2048 × 1024 pixels.

This synchronous DRAM 10a, 11a
In response, the first and second memory control units 12, 1
As described with reference to FIG. 1, the address converting means 18 and 19 provided in the third circuit assign the same row address of the synchronous DRAMs 10a and 11a to the rectangular area of the image data, and raster scan each rectangular area. The column addresses of the synchronous DRAMs 10a and 11a are allocated in the order of, and further, different banks are allocated to the adjacent rectangular areas, so that the received X.
A process of converting the Y address into the row / column address of the synchronous DRAMs 10a and 11a is executed.

FIG. 9 shows an example of this memory manpping. In this embodiment, one rectangular area is 32 ×
The structure is formed by 32 pixels. Such memory mapping is

[0048]

[Equation 1]

Will be realized according to the following. here,
[Equation 1] "RA" in the formula is a low address, and "BA" is
Represents a bank address, “CA” represents a column address, “BA = 0” represents bank A, and “BA = 1” represents bank B.

FIG. 10 shows the hardware structure of the address conversion means 18 and 19 for realizing the equation (1). Where X (0) is the least significant bit of the X address, X (1
0) is the most significant bit of the X address, Y (0) is the least significant bit of the Y address, Y (9) is the most significant bit of the Y address, R
OW (0) represents the least significant bit of the row address, ROW (9) represents the most significant bit of the row address, COLUMN (0) represents the least significant bit of the column address, and COLUMN (9) represents the most significant bit of the column address. There is.

With this hardware configuration, for example,
When the X / Y address of the image data "X = 64, Y = 32" is received, "X = 00001000000, Y = 00001000"
According to "00", the address conversion means 18 and 19 determine that "row address = 0000100001, column address = 0000000000,
Bank address = 1 ", that is," row address = 3 "
3, column address = 0, bank address = B ”, the address conversion processing for realizing the memory mapping shown in FIG. 9 is executed.

According to the row / column address calculated by this address conversion processing, the synchronous DRAM 1
Although 0a and 11a are accessed, the image data drawn by computer graphics or the like usually has a localized property, and therefore often falls within the same rectangular area. In such a case, Since the same row address is allocated in the rectangular area, the synchronous DRAM 10 can be used without changing the row address.
The write access of a and 11a is realized.

When the display image data is output, the same rectangular area is scanned in the horizontal direction, so that the same row address is allocated within the rectangular area. The read access to the synchronous DRAMs 10a and 11a is realized without changing the row address. Moreover, since the column addresses of the synchronous DRAMs 10a and 11a are assigned to each rectangular area in the order of raster scan, the synchronous DRAM 10
According to the above-mentioned column address continuous access function of a and 11a, extremely high speed access is realized.

Since different banks are assigned to adjacent rectangular areas of the same image data, the write access is transferred to the adjacent rectangular area by the drawing image data straddling the adjacent rectangular area. Alternatively, even when the read access is moved to the adjacent rectangular area according to the raster scan, the row address of another bank can be set during the access according to the row address setting function of the synchronous DRAMs 10a and 11a. , Substantially continuous access will be realized.

On the other hand, the selector 14a alternates for each screen, and one of the synchronous DRAMs 10a, 1
Since the display image data is output from 1a, the synchronous DRAM 10a or 11a which outputs the display image data is selected according to the screen end signal generated from the synchronization signal, and the output display image data is output to the DA converter 22. To the DA converter 2
2 converts the display image data output from the selector 14a from a digital signal into an analog signal and displays it on the display device 15.

In this way, the image processing system 1 shown in FIG. 7 has two synchronous DRAMs each having a one-port structure.
By adopting the configuration including 10a and 11a, the synchronous DR of the writing destination of the drawn image data in units of one screen
Since the AMs 10a and 11a and the synchronous DRAMs 10a and 11a from which the display image data is read are replaced, the drawing image data is updated and displayed on the display device 15, which is expensive. The drawing image data can be updated and displayed on the display device 15 without using a large video RAM.

FIG. 11 shows an embodiment of the image processing system 1 of the present invention whose principle configuration is shown in FIG. In the figure,
The same components as those described in FIG. 2 are indicated by the same symbols.

A digital signal processor 100 includes a memory control unit 31 and a drawing calculation mechanism 3.
4 and the output address calculation mechanism 35 are expanded. 30a is a synchronous D corresponding to the image memory 30.
The RAMs 32a are speed conversion buffers corresponding to the data adjusting means 32. Reference numeral 39 is a DA converter for converting the display image data generated by the speed conversion buffer 32a from a digital signal into an analog signal, and 40 is a synchronizing signal generating mechanism for generating a synchronizing signal.

In the embodiment of FIG. 11, if the two banks of the synchronous DRAM 30a are represented by banks A and B, as described in the principle configuration diagram of FIG. 2, one of the banks A and B is drawn and calculated. For access from the mechanism 34,
The other banks A and B are used for access from the output address calculation mechanism 35, and the roles of these two banks A and B are changed at the stage when the drawing calculation mechanism 34 finishes writing one screen, thereby forming a double buffer. The drawing image data is written into the two banks A and B of the prepared synchronous DRAM 30a, and the display image data is read out and displayed on the display device 33.

Since each bank A, B of the synchronous DRAM 30a has a storage capacity for one screen, for example, when one screen has 2048 × 1024 pixels, each bank A, B has 2048 × 1024 pixels. It is configured to have a capacity for pixels.

In response to the synchronous DRAM 30a, the address conversion means 36 included in the memory control unit 31 allocates the same row address of the synchronous DRAM 30 to the rectangular area of the image data as described with reference to FIG. , The column address of the synchronous DRAM 30a is allocated to each rectangular area in the order of raster scan, and the same bank is allocated to each rectangular area of the same image data, so that the received XY addresses are synchronous. The process of converting to the row / column address of the DRAM 30a is executed.

FIG. 12 shows an example of this memory manpping. In this embodiment, one rectangular area is 32
The configuration is formed by 32 pixels. Such memory mapping is

[0063]

[Equation 2]

It will be realized according to. here,
[Equation 2] "RA" in the equation is a low address, and "CA"
Represents a column address. When accessing the bank A, the most significant bit of the Y address is set to "0", and when accessing the bank B, the most significant bit of the Y address is set to "1".

FIG. 13 shows the hardware structure of the address conversion means 36 for realizing the equation (2). Where X (0) is the least significant bit of the X address, X (10) is the most significant bit of the X address, Y (0) is the least significant bit of the Y address, and most significant bit of the Y address of Y (9). , ROW (0)
Is the least significant bit of the row address, ROW (10) is the most significant bit of the row address, COLUMN (0) is the least significant bit of the column address, and COLUMN (9) is the most significant bit of the column address.

With this hardware configuration, for example,
When the X / Y address of the image data “X = 32, Y = 32” is received, when accessing the bank A,
In accordance with "X = 00000100000, Y = 0000100000", the address conversion means 36 causes the "row address = 00001000001,
Column address = 0000000000, bank address = 0 ",
That is, “row address = 65, column address =
0, bank address = A ", the address conversion processing for realizing the memory mapping shown in FIG. 12 is executed.

In accordance with the row / column address calculated by this address conversion processing, the synchronous DRAM 3
Although 0a is accessed, the image data drawn by computer graphics or the like usually has a localized property, so that it often fits within the same rectangular area. Since the same row address is allocated in the area, write access to the synchronous DRAM 30a can be realized without changing the row address.

When the display image data is output, the same rectangular area is scanned in the horizontal direction, so that the same row address is assigned to each rectangular area. The read access to the synchronous DRAM 30a is realized without changing the row address. Moreover, for each rectangular area, the synchronous DRA is performed according to the raster scan order.
Since the column address of the M30a is assigned, extremely high speed access can be realized according to the above-described column address continuous access function of the synchronous DRAM 30a.

When accessing the synchronous DRAM 30a, if the access is across different rectangular areas, the two banks are switched in a time division manner with the rectangular area as a boundary. If the drawn image data does not fit in the same rectangular area and the drawn image data straddles the adjacent rectangular area, write access moves to the adjacent rectangular area, or read access moves to the adjacent rectangular area according to raster scan. Even at this time, according to the above-mentioned row address setting function of the synchronous DRAM 30a, it becomes possible to set the row address of another bank during the access, so that substantially continuous access is realized.

According to the embodiment of FIG. 11, the writing of the drawing image data and the reading of the display image data are alternately executed in a time division manner. Therefore, the display image data output from the synchronous DRAM 30a is Instead of being continuously output, the output is sandwiched between the drawn image data.

From this, the speed conversion buffer 32a extracts the display image data output from the synchronous DRAM 30a, converts it into continuous data, and displays it in the display device 33.
Will be displayed. For example, with a capacity of 2 lines,
During the one-line scanning of the display device 33, the display image data output from the synchronous DRAM 30a is converted into continuous data and stored in another buffer for one line, and when the next one line is scanned, the display is displayed. It outputs according to the frequency. According to such a processing configuration, in the embodiment of FIG. 7, correct image data cannot be output when the memory access speed is lower than the display frequency, and when the memory access speed is higher than the display frequency. According to the embodiment of FIG. 11, the ratio of the display output access to the total memory access can be set freely, so that the maximum drawing performance can be obtained. There are advantages.

In this way, the image processing system 1 shown in FIG. 11 has a structure including the two-bank synchronous DRAM 30a having the one-port structure, and the drawing image data is written in one screen unit. A bank,
Since the drawing image data is updated and displayed on the display device 33 by adopting a configuration in which the bank to which the display image data is read is changed, the drawing is performed without using an expensive and large video RAM. The image data can be displayed on the display device 33 while being updated.

FIG. 14 shows an embodiment of the image processing system 1 of the present invention whose principle configuration is shown in FIG. In the figure,
The same components as those described in FIG. 3 are indicated by the same symbols.

Reference numeral 100 denotes a digital signal processor which expands the first memory control unit 42, the second memory control unit 43 and the drawing calculation mechanism 45. Reference numeral 40a is a synchronous DRAM corresponding to the non-display information image memory 40, 47 is a DA converter for converting the display image data output from the video RAM 41 from a digital signal to an analog signal, 48
Is a synchronization signal generation mechanism for generating a synchronization signal.

In the image processing system 1 of this embodiment, as in the prior art, the video RAM 41 is provided so that the image data is updated and displayed on the display device 44. The depth information and the control information that are not output to the above are stored in the synchronous DRAM 40a.

That is, according to the embodiment of FIG. 7, the synchronous DR output to the display device 15 is the one.
Since the AMs 10a and 11a cannot be accessed from the drawing calculation mechanism 16, in order to solve this, in this embodiment, the video RAM 4 having a two-port configuration is used for the image plane that requires display output access.
1 and the planes that do not need display output access are stored in the synchronous DRAM 40a. For the image plane, it is often the case that only the light is needed, and the depth information etc.
Often read once and then write.

When the X / Y address of such non-display information is received from the drawing calculation mechanism 45, the address conversion means 46 executes the same address conversion processing as the address conversion means 18 and 19 of the embodiment of FIG. Then, according to the row / column address obtained as a result, the synchronous DRAM 40a
Will be accessed at high speed.

In this way, the image processing system 1 shown in FIG. 14 can write the non-display information of the drawn image data into the synchronous DRAM 40a at high speed and read it from the synchronous DRAM 40a at high speed.

Although the present invention has been described with reference to the illustrated embodiment,
The present invention is not limited to this. For example, in the embodiment, the present invention is disclosed by using the synchronous DRAM, but the present invention is not limited to this.

For example, if a triangle as shown in FIG. 13A is written according to the pixel order shown in FIG. 13B, as described above, in the case of the conventional technique, 1750 ns.
If what is needed is a case in which this triangle fits within the same rectangular area, the row address does not need to be changed in the present invention, so that the access speed can be shortened to 1350 ns even at the same access speed as the video RAM. . In addition,
In this case, if a synchronous DRAM is used, continuous access is possible even when the triangles do not fit in the same rectangular area, and one access can be performed in one clock (16.7 ns). The time required for access is "16.7 x number of pixels = 16.7 x 25 = 418n.
It will be significantly shortened to "s".

[0081]

As described above, according to the present invention,
The address multiplex type image memory can be accessed at high speed. Then, it becomes possible to display on the display device while updating the image data stored in the image memory of the address multiplex system while realizing high-speed processing and without using an expensive and large video RAM.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a principle configuration diagram of the present invention.

FIG. 3 is a principle configuration diagram of the present invention.

FIG. 4 is an explanatory diagram of memory mapping of the present invention.

FIG. 5 is an explanatory diagram of memory mapping of the present invention.

FIG. 6 is an explanatory diagram of memory mapping of the present invention.

FIG. 7 is an example of the present invention.

FIG. 8 is an explanatory diagram of a synchronous DRAM.

FIG. 9 is an example of memory mapping.

FIG. 10 shows an embodiment of address conversion means.

FIG. 11 is an example of the present invention.

FIG. 12 is an example of memory mapping.

FIG. 13 is an example of an address conversion unit.

FIG. 14 is an example of the present invention.

FIG. 15 is an explanatory diagram of a conventional technique.

FIG. 16 is an explanatory diagram of a conventional technique.

FIG. 17 is a time chart of memory access of the video RAM.

FIG. 18 is an example of an access order of image data.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Image processing system 10 1st image memory 11 2nd image memory 12 1st memory control unit 13 2nd memory control unit 14 Selection means 15 Display device 16 Drawing calculation mechanism 17 Output address calculation mechanism 18 Address conversion means 19 Memory mode determining means 20 Address converting means 21 Memory mode determining means

Claims (9)

[Claims] 1. An image memory access method for executing access control of an image memory of an address multiplex method, wherein the same row address of the image memory is allocated to a rectangular area of the image data, and the XY addresses of the image data are allocated. An image memory access method characterized by comprising address conversion means for converting into a storage address of an image memory, and processing to access the image memory according to the storage address converted by the address conversion means. 2. The image memory access method according to claim 1, wherein the address conversion means performs processing so as to allocate a column address of the image memory to each rectangular area of the image data according to a raster scan order. And image memory access method. 3. The image memory access method according to claim 1 or 2, wherein when the image memory is composed of two or more banks, the address converting means sets adjacent rectangular areas of the same image data to Image memory access method characterized by processing to allocate different banks. 4. The image memory access method according to claim 1, wherein when the image memory is composed of two or more banks, the address conversion means is the same for each rectangular area of the same image data. A time slice control means for performing processing so as to allocate different banks in the same bank and controlling the rectangular areas of other banks to be accessed prior to the access when different rectangular areas on the same bank are continuously accessed. An image memory access method characterized by being provided. 5. An image processing system for performing processing for displaying on a display device while updating image data stored in an image memory of an address multiplex system, wherein the image memory of the address multiplex system is 1
Two image memories (10, 11) having a plurality of banks having a capacity for storing screens are prepared, and the address converting means (18, 20) according to claim 3 is provided. 20) According to the above image memory (10,
11) is provided with two memory control units (12, 13) for calculating the storage address, and one of the memory control units (12, 13) draws image data in one of the image memories (10, 11). The memory control unit (12,1
3) adopts a configuration in which reading of display image data from the other image memory (10, 11) is repeated while changing the image memory (10, 11) in units of one screen. The image memory of the one that outputs the display image data by inputting the data output of the above-mentioned image memory (10, 11)
An image processing system comprising: a selecting means (14) for selecting (10, 11) and sending the display image data to a display device (15). 6. An image processing system for processing image data stored in an address multiplex type image memory while displaying the image data on a display device while updating the image data.
5. An image memory (30) comprising one bank and having a capacity capable of storing one screen in each bank is provided, and the address conversion means (36) and the time slice control means (38) according to claim 4. A memory control unit (3) for calculating the storage address of the image memory (30) according to the address conversion means (36) and switching the access destination bank according to the time slice control means (38).
1), and that the memory control unit (31) writes drawing image data to one bank and reads display image data from the other bank. By adopting a configuration which repeats alternatingly, further, display image data which is read out at time intervals by the time slice control means (38) is extracted, and the display image data is converted into continuous data to display device (33). An image processing system characterized by comprising a data adjusting means (32) for sending to the. 7. The image processing system according to claim 5, wherein the image memory (10, 11, 30) is configured to use a two-bank synchronous DRAM. . 8. An image processing system for updating image data stored in an address multiplex type image memory while displaying the image data on a display device, wherein the display image data is used as the address multiplex type image memory. In addition to the video RAM (41) for storing the image data, a non-display information image memory (40) of a plurality of banks having a capacity capable of storing one screen for storing image information other than display image data is prepared, and An address converting means (46) according to claim 3, comprising:
A memory control unit (42) for executing an access process to the non-display information image memory (40) while calculating the storage address of the non-display information image memory (40) according to the address conversion means (46) An image processing system characterized by this. 9. The image processing system according to claim 8, wherein the expanded image memory for non-display information (40) is configured to use a two-bank synchronous DRAM.