JPH11296145A - Liquid crystal display controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simultaneously display the same or different video data within a low resolution display range by providing a display control means for controlling the display of held still pictures or display data successively inputted from a personal computer on any divided arbitrary picture of low resolution. SOLUTION: A frame memory write control part 0103 generates a write command WCMD to frame memories 1(0101) and 2(0102). A frame memory write address generating part 0104 generates a write address WADR. A picture division control part 0107 displays plural low resolution video signals on a liquid crystal panel 0117 while dividing them into pictures. With an input vertical synchronizing signal VSYNC as a trigger, a write/read switching control part 0108 switches write/read control to the frame memories 1(0101) and 2(0102). Then, held images are displayed in the first to third divided areas on the liquid crystal panel 0117 and video data to be successively changed form the personal computer are displayed in the fourth area.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display for displaying video data. Further, the present invention relates to a liquid crystal display control device and a control method for controlling display of the liquid crystal display device.

[0002]

2. Description of the Related Art Conventionally, as a liquid crystal display control device for displaying video data from a personal computer or the like, a frame for storing a video signal for liquid crystal display as disclosed in, for example, JP-A-7-261703. A memory, a write row address setting unit that sets a write row address of a video signal to the frame memory based on a first timing signal from a video signal supply source, and a request to write the video signal to the frame memory based on the first timing signal The liquid crystal display control device includes a write control circuit for generating a signal.

The liquid crystal display control device includes a synchronizing signal generating circuit for transmitting a second timing signal set at a desired timing, and a row address for reading a video signal from a frame memory based on the second timing signal. A read row address setting unit, a read control circuit for generating a read request signal of a video signal to the frame memory based on the second timing signal, a write request signal, and writing of a video signal in the frame memory from the read request signal And a conflict avoiding unit for generating a control signal for avoiding a conflict between reading and transmitting the control signal to the frame memory.

FIG. 27 shows a configuration example of a liquid crystal display control device disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 7-261703. 2001 is a frame memory, 2002 is a synchronization circuit, 2003 is a write row address counter, 2004 is a write control circuit, 2005 is a synchronization signal generation circuit, 2006 is a read row address counter, 2007 is a read control circuit, 20
08 is an address switching circuit, 2009 is RAS / and CA
Each of the S / generation circuits is shown.

In FIG. 27, a write clock signal WCLK synchronized with a horizontal synchronizing signal HSYNC and a vertical synchronizing signal VSYNC, and a horizontal display signal H are used to write a video signal DT1 to a frame memory 2701.
DISP, vertical display signal VDISP and video signal DT
A synchronizing circuit 2702 for transmitting a write enable signal WE indicating an effective part of the control signals WCLK and HD
A write row address counter 2703 which is a write row address for setting a write row address WAD of the video data DT1 to the frame memory 2701 based on the ISP and VDISP, and a write control for generating a write request signal WREQ based on the control signals HDISP and VDISP. And a circuit 2704 for controlling the writing of the video data DT1 to the frame memory 2701.

[0006] Further, there is provided a synchronization signal generation circuit 2705 composed of a clock oscillation circuit and a counter, and the synchronization signal generation circuit 2705 reads out the data written in the frame memory 2701 at a timing suitable for the liquid crystal display unit. To generate a second timing signal set for this purpose.

[0007] The second timing signal in this embodiment is a horizontal synchronizing signal LHSYNC and a vertical synchronizing signal LVSY.
NC, a read clock signal RCLK, a vertical display signal LVDISP, a horizontal display signal LHDISP, and a read enable signal RE indicating an effective display portion.

Each signal generated by the synchronizing signal generation circuit 2705 is supplied to the apparatus shown in FIG. 20 by a read row address counter 2706 which is a read row address setting unit for setting a read row address RAD of a video signal to the frame memory 2701. And a read control circuit 2707 that generates a read request signal RREQ. Each signal generated by the synchronization signal generation circuit 2705 is supplied to the read row address counter 2706 and the read control circuit 2707. .

Further, the present liquid crystal display control device includes an address switching circuit 2708 for selecting a write row address WAD or a read row address RAD and sending the selected row address to the frame memory 2701, and responding to two request signals WREQ and RREQ by a frame. Control signals RAS / and CAS / for avoiding contention between write and read operations in memory 2701
And a RAS / and CAS / generation circuit 2709 of a conflict avoidance unit that generates

The write control circuit 2704 outputs the signal W
REQ as well as the signal WREQ and the signal RAS /
Switching signal WA based on the signal CAS /
Is transmitted to the address switching circuit 2708. The read control circuit 2707 generates a signal RREQ and transmits an address switching signal RA / based on the signal RREQ, the signal RAS /, and the signal CAS / to the address switching circuit 2708. The address switching circuit 2708 generates a frame memory 2701 based on these signals WA /, RA /.
Are selectively switched.

[0011]

However, in the above prior art, the use of a frame memory allows
Since the timing of writing video signals to the frame memory and the timing of reading them for display on the liquid crystal panel can be controlled asynchronously, the basic part of being able to read video signals corresponding to the operable frequency of the liquid crystal panel is possible. However, there is no mention of an application such as a configuration capable of simultaneously displaying a plurality of video screens.

Further, in the above-mentioned prior art, a CRT display device which performs analog control requires digital control in units of pixels, and an adjustment realizing means of a liquid crystal display device which requires adjustment which is not provided in the CRT display device. Was not mentioned.

An object of the present invention is to divide this high-resolution liquid crystal display screen into a plurality of low-resolution display ranges as a display form of a high-resolution liquid crystal display device, and to provide the same or different video images for each of the low-resolution display ranges. An object of the present invention is to provide a liquid crystal display control device capable of simultaneously displaying data.

Another object of the present invention is to provide a reference for making various adjustments in a liquid crystal display device which requires digital control in units of pixels, unlike a CRT display device which performs analog control. Generate display data internally,
A liquid crystal display control device capable of simultaneously displaying video display data to be adjusted and display data as a reference for adjustment for each of a display screen of a high resolution liquid crystal display device divided into a plurality of low resolution display ranges. Is to provide.

Still another object of the present invention is to provide a liquid crystal display device in which a plurality of video data are displayed in a superimposed manner depending on the input video data. An object of the present invention is to provide a liquid crystal display control device which can always display both video signals by superimposing them without losing display.

[0016]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, according to the present invention, the liquid crystal display device is compatible with high resolution, has a frame memory capable of storing several frames of the high resolution video signal, and divides the inside of the memory into a plurality of regions corresponding to low resolution. Then, control for writing and reading is performed for each of the divided areas. Thus, in the display of the high-resolution display device, the same or different low-resolution video signals can be simultaneously displayed in each of the divided display areas. Also, arbitrary digital data by a microcomputer is stored in one area of the divided plurality of low resolution areas of the frame memory, this data is used as reference data for liquid crystal display device adjustment, and the video data to be adjusted is stored in other divided areas. By storing in
The adjustment reference data and the video data to be adjusted can be simultaneously displayed on the high resolution liquid crystal display device.

Further, as a display mode of the liquid crystal display device, when a plurality of video data are superimposed and displayed, the weight of the main video data in each digitized display data is set to 1/2. By assigning the weight of the secondary video data only to the top and synthesizing both video data, any video data information can be superimposed and displayed without losing any video data information when displayed on a liquid crystal display device. Things.

[0019]

An embodiment of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of a liquid crystal display system using the technology of the present invention. A main part of the technology of the present invention is a screen division control unit 0107 and the control by the control unit. And a frame memory / write address generation unit 0104. Also,
In this embodiment, a synchronous DRAM is assumed as the frame memory 10101 and the frame memory 2 0102 used so as to be able to cope with high-resolution input video data.

In FIG. 1, 0101 denotes first high-resolution video data (here, 1280 dots × 1024 lines of S)
An XGA mode is assumed.) A frame memory 1 for storing one frame and a frame memory 0102 for storing one frame of the second high-resolution video data are connected to the frame memory 2 and 0103 in synchronization with a write system control clock WCLK. 101
01, write command W for frame memory 2 0102
Frame memory write control unit for generating CMD, 0104
Is the frame memory that generates the write address WADR.
Write address generation unit, 0105 is also the read command R
Frame memory read control unit for generating CMD,
Is the frame memory that generates the read address RADR
A read address generation unit, 0107 is a screen division control unit for dividing a plurality of low resolution video signals on a high resolution liquid crystal panel for display, and 0108 is triggered by an input vertical synchronization signal VSYNC, and the frame memory 10101 and A write / read switching control unit for switching write / read control to the frame memory 2 0102; 0109, an oscillator for generating a read system control clock RCLK; 0110, selection of a write command WCMD or read command RCMD for the frame memory 1. The selector circuit 1 or 0111 that performs the write address WADR or the read address RA
The selector circuits 2, 0112 and 0113 for selecting the DR are the same as the selector circuit 3 for the frame memory 2 0102, and the selector circuits 4 and 0114 are the same for the frame memory 1010.
A buffer circuit 1 for controlling switching of write data WDATA and read data RDATA for 1
Is a buffer circuit 2 for the frame memory 2 0102, and 0116 is a selector circuit 5 for selecting the read data from the frame memory 1 0101 or the frame memory 2 0102. 0117 is a liquid crystal for displaying the read data RDATA from the selector circuit 0116. Panel, 0118 is an inverter circuit, 0119 is input video data (WDATA)
Write data conversion control unit for performing conversion according to the data bus width of the memory when writing
Denotes read data conversion control units for converting display data read from the frame memory in accordance with the data bus width of the liquid crystal panel.

Hereinafter, a first embodiment of the present invention will be described with reference to FIG.

First, the digitized write data WD
ATA includes a buffer circuit 1 0114 and a buffer circuit 2 01
The data is output to the frame memory 10101 and the frame memory 20102 via 15. In which frame memory the write data WDATA is written, the write / read switching control unit 0108 is determined based on the input vertical synchronization signal VSYNC.
Is selected by the write enable signal WENP generated in step (1).

When the frame memory 10101 is a write,
WENP = "H", and the frame memory write control unit 0103 is synchronized with the write clock WCLK.
The write command WCMD and the write address WADR generated by the frame memory / write address generation unit 0104 are transferred to the selector circuit 1011 and the selector circuit 2
0111 is selected.

While the frame memory 1 0101 is in a write state, the frame memory 2 0102 is in a read state by a signal obtained by inverting the write enable signal WENP = "H" by an inverter circuit 0118. In this case, the oscillator
The read command RCMD and the read address RADR generated by the frame memory read control unit 0105 and the frame memory read address generation unit 0106 at the timing synchronized with the read clock RCLK output from the selector circuit 3 0112 and the selector circuit 4 0113 is selected.

Accordingly, the memory data read from the buffer circuit 0115 is selected as read data RDATA by the selector circuit 5016 and displayed on the liquid crystal panel 0117. Here, in the write operation to the frame memory 10101, in order to realize the screen division display which is a feature of the present invention, the frame memory write control is performed by the division control signal DIVCNT [3: 0] from the screen division control unit 0107. It controls the unit 0103 and the frame memory / write address generation unit 0104, and controls the write position for the frame memory 10101.

FIG. 2 shows a display state of the liquid crystal panel when the screen division control is performed according to FIG. Here, the entire display area is the liquid crystal panel 0117 and the resolution is SXGA (1
The resolution is VGA (640 dots × 480 lines), and the resolution is VGA (640 dots × 480 lines).

In FIG. 2, reference numeral 0117 denotes S shown in FIG.
XGA size liquid crystal panel, 0201 is the first split screen when the screen is split into the VGA size, 0202 is the second split screen, 0203 is the third split screen, and 0204 is the fourth split screen
Are respectively shown.

First, the VGA size video write data WDATA of FIG. 1 is written to a memory area corresponding to the first divided screen 0201. Next, different VGA size video write data WDATA is written to the memory area corresponding to the second divided screen 0202 while the write operation to the memory area corresponding to the first divided screen 0201 is prohibited. Similarly,
In a state where the write operation to the memory area corresponding to the first divided screen 0201 and the second divided screen 0202 is prohibited, further different VGA size video write data WDATA
Is written to the memory area corresponding to the divided screen 0203.

Next, the first to third divided screens 02
In a state where the write operation to the memory area corresponding to 01 to 0203 is prohibited, the VGA size video write data WDAT input to the memory area corresponding to the fourth divided screen 0204 is input.
A is sequentially written. For display on the liquid crystal panel 0117, memory data in all areas is sequentially read regardless of the divided screen. Therefore, the video data displayed on the liquid crystal panel 0117 displays the held video in the first to third divided areas, and the fourth divided area displays the video data that is sequentially changed by a system operation such as a personal computer. It can be displayed.

FIG. 3 is an operation flowchart for realizing the split screen display shown in FIGS. 1 and 2. Here, the operation will be described for the frame memory 10101.

First, the state of the write enable signal WENP output from the write / read switching control unit 0108 is confirmed. In the invalid state (WENP = “L”), the frame memory 1 0101 performs a read access operation (at this time, the frame memory 2 0102 performs a write access).
In the valid state (WENP = “H”), the frame memory 0101 is in write access, and the validity / invalidity of the screen division mode is confirmed. When the screen division mode is invalid, the write operation is performed on the entire area of the liquid crystal panel 0117.

When the screen division mode is valid, the light area setting signal DIVCN output from the screen division control unit
The write operation is performed on the divided area corresponding to the state of T [3: 0]. By setting DIVCNT [3: 0] = 1h, a write operation for the first divided screen area 0201 is executed. Subsequently, the write enable signal is valid (WENP =
“H”) and when the screen division mode is enabled, the write area setting state is checked again.

By setting DIVCNT [3: 0] = 2h during this time, the write operation to the first divided screen area 0201 is prohibited, and the write operation to the second divided screen area 0202 is executed. Hereinafter, similarly, DIVCNT
By setting [3: 0] = 4h, 8h, a write operation is performed on the third divided screen area 0203 and the fourth divided screen area 0204. After the execution of the write operation for the fourth divided screen area 0204, the write enable signal is invalidated (WENP = “L”) so that the frame memory 10 0
Access to 101 switches from write to read,
The frame memory 20102 performs write access according to this sequence.

Next, the write enable signal is valid (WEN
P- "H"), and when the screen division mode is valid and the write area setting is DIVCNT [3: 0] = 8h, a write operation is performed on the memory area corresponding to the fourth divided screen area 0204. Then, the video data is updated. By repeating the above control between the frame memory 1 0101 and the frame memory 2 0102, the liquid crystal panel 01 shown in FIG.
In the display 17, the display in the first to third divided screen areas 0201 to 0203 is in a hold state, and only the display in the fourth divided area 0204 can display video data that is sequentially changed by a system operation.

An example of the operation timing for the flowchart shown in FIG.
5216165. The configuration of this frame memory is “1048576 word × 16 bits”.
0101 and a frame memory 2 0102.

FIG. 4 shows a write data conversion control unit 0119 for realizing this configuration, and FIG. 5 shows a read data conversion control unit.
The timing operation of FIG. In FIG. 4, the video data (IREDATA-IBODATA) has two parallel R, G, and B, each of which has a total of 48 bits of 8 bits. This data needs to be written to the frame memory 10101 or the frame memory 2 0102. The data bus width of two chips of memory is 32 bits (FM
1WD-FM2WD), so 48 bits to 32 bits
Data conversion to bits needs to be performed. FIG. 4 shows the timing for this data conversion.

FIG. 5 shows the conversion timing of the data read from the memory. In the case of reading from the memory, the operation is the reverse of the operation of writing to the memory shown in FIG. 4, and the video data (FM1RD-FM2RD) read from the memory in 32-bit width units is converted into a 48-bit width (OREDATA- OBODATA). In order to realize this data conversion, as shown in FIG. 5, memory read clocks having different duties are used.

FIG. 6 is a memory access image diagram when the low-resolution video data is divided and displayed on the high-resolution liquid crystal panel shown in FIG.

First, in the writing operation, the first divided video data 0201 is written. The number of memory writes for one horizontal line is such that the input video data is two parallel inputs and the input video data at the timing of FIG.
Since the timing ratio with the memory write access is 2: 3, it is necessary to perform 480 accesses (see the following formula).

1H memory write frequency = 640/2 (input 2 parallel) × 3/2 (conversion ratio in FIG. 4) = 480 Therefore, first, write access is performed to ROW0 1 to 480 of the first line. Next, following the 480th write access of ROW0, write access is made to 1 to 480 of ROW2 of the second line. Thereafter, by the same control, finally, from ROW958 1st to 480th line 958
By performing write access to 80, the video data of the first split screen 0201 of FIG. 2 is written.

Next, in order to write the video data of the second divided screen 0202, first, write access is made to 481 to 960 of the first line ROW1. Next, after the 960th write access of ROW1, the second line ROW
Write access is made to 481 to 960 of W3.
Thereafter, ROW9 of the 480th line is finally controlled by the same control.
By performing write access to 481 to 960 of 59, the video data of the second divided screen 0202 of FIG. 2 is written. Similarly, video data is written to the third divided screen 0203 and the fourth divided screen 0204.

After the video data is written in the memory area corresponding to the first divided scene 0201 to the fourth divided screen 0204, the first divided screen 0201 is changed to the third divided screen 0201.
When the fourth divided screen is set as a work area by referring to the still image up to the 2033 as a still image, all video data input thereafter are written in the memory area corresponding to the fourth divided screen.

FIG. 7 is a timing chart for the memory write operation. First, register setting is performed by an MRS command. Here, full mode burst setting and the like are performed. The row address is determined by the next ACTV command. Here, first, the ROW0 address is set. Next, a WRIT command is generated, and from this timing, continuous writing is performed by a burst operation. ROW0 1 to 4
The BST command is generated in the next cycle after the writing up to 80 is completed, and the writing operation for ROW0 is completed. Subsequently, the row address of the next line ROW2 is determined by the ACTV command, and the same write operation is performed.

Next, in the read operation, first, read access is made to ROW0 1 to 480 on the first line. Next, following the 480th read access of ROW0, read access is similarly performed to 481 to 960 of ROW1 of the first line. Thereafter, by the same control, finally, 481 to 960 of ROW 1919 on the 960th line
By performing read access to the
The video data from the split screen 0101 to the fourth split screen 0204 can be simultaneously displayed.

FIG. 8 is a timing chart for the memory read operation.

The difference from the memory write operation is that the second ACTV command specifies ROW2 in order to access the second line ROW0 in the first line ROW0 following the read operation of 480. Line RO
In order to read 481 of W1, ROW1 is designated by the next ACTV command.

As described above, by devising the write and read addresses for the memory, low-resolution video signals can be displayed simultaneously on the high-resolution liquid crystal panel by dividing the screen. A document creation operation by a word processor or the like can be realized while referring to the still image.

FIG. 9 shows an adjustment menu (on-screen display) for the first embodiment described so far.
It is an example showing the above operation method. In FIG. 9, first, a screen division menu (DI
Select (PLAY DIVIDE). Next, enable / disable of screen division is enabled in setting menu 0902 (YES
Select). Further divided area setting menu 0903
To select an area to be written. Here, it is assumed that the first split screen is selected (1ST-PLANE). In the next menu 0904, a selection is made at the timing when the video signal to be captured is displayed, while checking the video data displayed on the first split screen (YES selection).

When the capture of one video signal is completed,
It returns to the previous split screen selection menu and waits for the selection of the split screen again or the return selection to the main menu. That is, it is possible to capture the same or different video signal as a still image for all the divided screens as well as to repeatedly capture the same divided screen as a still image. It is also possible to always take in the video signal by using the remaining divided screen as the work display area (the method of use according to the first embodiment shown in FIG. 2).

According to the first embodiment described above, the display of video data by a plurality of applications at the same time can be displayed on a single display device without simultaneously activating the plurality of applications. Requires less space.

FIG. 10 is a block diagram showing a second embodiment of the present invention. As compared with the first embodiment shown in FIG. 1, arbitrary data can be written to or read from the frame memory 1 0101 and the frame memory 2 0102 by access from a microcomputer. FIG.
0, reference numeral 1001 denotes a microcomputer, and 1002 denotes a frame memory 1 0101 or a frame memory 2 0102 by the microcomputer.
1003 is a register for setting write enable / disable of writing arbitrary data to the PC, and 1003 is video data WDATA from the personal computer.
And selector circuits for performing switching to arbitrary data MDATA by the microcomputer in accordance with the register 1002.

The register 1002 is set to an arbitrary data write mode by the microcomputer by user adjustment. As a result, the frame memory / write control unit 0103 and the frame memory / write address generation unit 0104 output the write command WCMD and the write address WADR according to the control from the microcomputer. Further, under the control of the microcomputer, the write / read switching control unit 0108 causes the frame memory 1 1010 regardless of the input vertical synchronization signal IVSYNC.
Alternatively, any one of the frame memories 2 0102 is fixed in the write mode, and the selector circuit selects arbitrary data MDATA from the microcomputer. Thereby, any data can be written to any area of the frame memory.

FIG. 11 shows a display screen image diagram according to the second embodiment using the configuration of FIG.

First, as a first stage, the microcomputer writes arbitrary display data serving as a reference for image quality adjustment on the fourth divided screen. Arbitrary data written in the fourth divided screen is held under the same control as in the first embodiment.
Next, as a second step, the input video data is displayed on the first split screen, and the display data is adjusted while referring to the display data serving as the adjustment reference displayed on the fourth split screen. I do. When the desired adjustment state is reached, the screen is brought into the holding state.

Next, as a third step, the input video data is displayed on the second divided screen while the reference data and the first adjustment data are displayed on the fourth divided screen. Then, the adjustment is performed in the same manner as in the second stage, and when a desired adjustment state different from the display data of the first divided screen is reached, the screen is brought into a holding state. Finally, as a fourth step, the display image quality of the second divided screen is selected from among the first divided screen or the second divided screen adjusted by the third step, and this is set as the final High-resolution display with adjusted values can be performed.

In this embodiment, the number of screen divisions is four,
The reference data is displayed on the fourth divided screen and the data to be adjusted is displayed on the first and second divided screens, and either one is selected. However, the number of screen divisions, the display position of the reference data,
Obviously, the number of screens to be adjusted can be arbitrary.

FIG. 12 is a display image diagram showing a third embodiment of the present invention.

The present embodiment is based on the fact that the liquid crystal panel is thinner than a CRT and is presumed to be used on a flat surface. That is, in the present embodiment, the high-resolution liquid crystal panel is divided into four screens, and the display can be recognized from two facing directions (A) and (B). That is,
For the direction from (A), a third split screen 0203 and
Display is performed on the fourth divided screen 0204, and the direction from (B) is displayed on the first divided screen 0201 as the fourth divided screen 02.
The video data displayed on 04 is displayed in a vertically and horizontally inverted state, and the video data displayed on the third divided screen 0203 is displayed on the second divided screen 0202 in a vertically and horizontally inverted state. Thus, the same display data can be recognized from any of the directions (A) and (B).

FIG. 13 is a schematic configuration diagram for display data control for realizing the third embodiment according to the present invention shown in FIG. In FIG. 13, 1301 is a microcomputer, 1302 is a frame memory 1 for storing display data for one screen of high resolution, 1303 is a frame memory 2 for storing display data of another screen, and 1304 is a frame memory for storing display data for another screen. Frame memory 1 130 under the control of microcomputer 1301
2 or a selector circuit for selecting the liquid crystal panel display data from the frame memory 21303.

When the display control shown in FIG. 12 is performed on the frame memory 1 1302 by the microcomputer 1301, the selector circuit 1303 performs a stable display by the frame memory 2 1303 during this time in order to prevent the display screen from being disturbed.
4 selects the read data from the frame memory 21303.

During this time, the frame memory 1 1302 performs data transfer with the microcomputer 1301 and stores data so that symmetric display can be performed between the divided display screens. When the data storage is completed, the selection by the selector circuit 1304 is switched, and the display shown in FIG. 12 is performed. Next, when a display having the configuration shown in FIG. 12 is performed on another display data, the display control shown in FIG. 12 is performed on the frame memory 2 1303, while a stable display is performed by the frame memory 1 1302. As described above, the selector circuit 1304 selects the data read from the frame memory 1 1302.

FIG. 14 is a schematic diagram showing an operation of writing video data to the frame memory in FIG. 12 in the third embodiment. As the first stage, the third split screen 02
03 low-resolution video data (1) ... (n) ... (n +
1) Write in the order of (m). As a second step, while holding the video data written in the third divided screen 0203,
Another video data for the fourth split screen 0204 (1)
Write in the order of (n) .. (n + 1) .. (m). Next, as a third step, the microcomputer 1301 reads the video data held in the third divided screen 0203 written in the first step for one pixel, and writes the data to the second divided screen 0202. Repeat the operation. At this time, the writing position of the memory is controlled so that the display data is displayed in a state where the display data is inverted left and right and up and down on the second divided screen 0202.

That is, the data of (n) is read and
Write to the position of (n), then read the data of (1)
Write in the position of (1). Hereinafter, by repeating the read and write operations in the same manner, the third divided screen 0203
Can be set in the second divided screen 0202. Finally, as a fourth step, the display data held in the fourth divided screen 0204 is transferred to the first divided screen 02 by the control similar to the third step.
Write to 01 with left, right, upside down.

As described above, when the operations from the first stage to the fourth stage are performed on the frame memory 1 1302, the stable video data stored in the frame memory 2 1303 is displayed on the liquid crystal panel during this period. This can prevent the screen from being disturbed due to this operation. By switching the read data from the frame memory 2 1303 to the frame memory 1 1302 by the microcomputer 1301 at the end of the fourth stage, a display which can be simultaneously recognized from the two opposite sides as shown in FIG.

Further, as shown in FIG. 15, in the third embodiment, frame memories for two screens are mounted as a frame memory 1 1302 and a frame memory 2 1303, of which the microcomputer 1 1302 is connected to the microcomputer 1 1302.
The display screen can be stopped by continuing to read out stable display data from the frame memory 21303 in order to prevent display disturbance when writing and reading operations from the 301 are performed over several frame periods. .

FIG. 16 is a block diagram showing a fourth embodiment according to the present invention. The present embodiment aims at recognizing a normal display by the recognition medium when the display device and the medium for recognizing the display device screen face in the same direction. In FIG. 16, 1601 is a liquid crystal panel and its display data, 1602 is a reflector for displaying the display by the liquid crystal panel, 1603 is display data for the reflector.
Reference numerals 1604 denote recognition media for recognizing display data projected on the reflection plate 1602, respectively.

The video signal displayed on the liquid crystal panel 1601 is projected by the reflector 1602, and is recognized in the recognition medium 1604 in a state where the left and right are inverted as shown by the reflector display data 1603. Therefore, the display on the liquid crystal panel 1601 is left-right inverted so that the reflector display data 1603 projected on the reflector 1602 can be recognized by the recognition medium 1604 in a normal display state. Thus, it can be used in game machines, barbers, and the like.

FIG. 17 shows the liquid crystal panel 16 shown in FIG.
FIG. 1 shows a schematic diagram of frame memory control for performing display in a horizontally inverted state. First, when writing a video signal from a personal computer, etc., use (1)... (N).
Write in the order of 1) .. (m) from the upper left side to the lower right side. On the other hand, on the reading side, the data of (1), (n), (n + 1), (m), which is read from the upper right side to the lower left side, is normally sent to the liquid crystal panel 1601. Displaying the video data inverted left and right is made possible by displaying from the upper left side to the lower right side of the street.

FIG. 18 shows a display image diagram for the fifth embodiment according to the present invention. In this embodiment, the high-resolution display panel is divided into a plurality of screens, and one screen is
The two display data are displayed at different magnifications.

That is, in the writing operation to the frame memory, the high resolution display panel 0117 is divided into screens and the first
One video data is written to and held in the frame memory area corresponding to the divided screen 0201. Next, in the frame memory area corresponding to the second divided screen 0202, the same data as that of the first divided screen 0201 is written and held. Similarly, the same data is written to the frame memory area corresponding to the third divided area 0203 and held. Video data input from a personal computer or the like is sequentially written into the frame memory area corresponding to the fourth divided screen 0204.

As described above, the same video data is written and retained from the first divided screen 0201 to the third divided screen 0203, and the inputted video data is sequentially written to the fourth divided screen 0204. .

Next, in the read operation, the first divided screen 02
All the video data written in 01 is read out and displayed on a one-to-one basis. Regarding the display of the second and third divided screens 0202 and 0203, the display data specified in the display data of the first divided screen 0201 is partially enlarged and displayed on each divided screen. That is, for convenience, if the pixel size of each divided screen is n dots in both the horizontal and vertical directions, and the pixel size of the display data to be partially enlarged is m dots in both the horizontal and vertical directions, the enlargement ratio is set to n. / M. For the fourth divided screen 0204, all video data input from a personal computer or the like to which data is sequentially written is read out and displayed on a one-to-one basis.

FIG. 19 is a schematic configuration diagram for realizing the fifth embodiment shown in FIG. In FIG.
1901 is a selector circuit for input image data from a personal computer or the like, 1902 is a frame memory 1, 1903 is a frame memory 2, 1904 is a selector for selecting either the frame memory 1 1902 or display data read from the frame memory 2 1903. A circuit 1905 is an enlargement processing control unit for performing enlargement processing of display data, and 1906 is a selector circuit for selecting either non-enlargement processing data or enlargement processing data.

The operation will be described with reference to the display of FIG. 18 as an example. First, the frame memories 1 1902 and 2 1903 are stored in the memory areas corresponding to the first divided screen 0201 to the third divided screen 0203, respectively. The video data displayed on the first split screen is written. Next, the selector circuit 1901 is set to the selected state of the frame memory 11902, and one screen of the video data sequentially input is written into the memory area corresponding to the fourth divided screen. When this writing is completed, the selector circuit 1904 selects reading from the frame memory 11902. In reading from the frame memory 11902, the high-resolution liquid crystal panel 0117 is read as usual.

Since the enlargement process is not performed in reading the first and fourth divided screens 0201 and 0204, the selector circuit 1906 directly selects the output of the selector circuit 1904. Second
And in the reading of the third divided screens 0202 and 0203,
To enlarge and display a part of the display data of the first divided screen 0201, the selector circuit 1906 selects enlarged display data which is an output of the enlargement processing control unit 1905.

While the frame memory 1 1902 is being read, the frame memory 2 1903 is in a write state by the selector circuit 1901, and the first to third divided screens 0201-0 are displayed.
The video data sequentially input to the fourth divided screen 0204 is written while the memory data corresponding to 203 is held. As described above, in the present embodiment, one image data can be enlarged and displayed at the same time, and another screen division area can be used as a work area while referring to them.

FIG. 20 shows a display image diagram for the sixth embodiment according to the present invention. In the present embodiment, when two pieces of video data are simultaneously displayed on one display screen while being superimposed on each other, both pieces of display data can be displayed without any loss. That is, when the second video data such as an adjustment menu on the screen is displayed while being superimposed on the first video data 2001, it is possible to recognize simultaneously without depending on both video data. It was done.

FIG. 21 is a comparison of a data overlay method using a simple overlay method, which is a conventional method, with the present embodiment, and a shift overlay method in which the first video data 2001 according to the present invention is overlaid after shifting by one bit. Show.

First, in the conventional simple overlay system, the most significant bit (MS) of the first video data 2001
B) is unconditionally discarded, and the logical sum is calculated with the second video data 2002 assigned only to the most significant bit (MSB). Therefore, as shown in FIG. 21, the combined display has the same information as the first video data before the combination and does not reflect the information of the second video data. Also, the first
When the most significant bit (MSB) of the video data 2001 is invalid, the combined display can reflect both video data. As described above, depending on the state of the first video data 2001, the synthesized video data reflects or does not reflect both video data, so that the display is disturbed.

On the other hand, in the shift overlay method according to the present invention, the uppermost (MS)
Rather than discarding B), all data is shifted one bit downward, and this information and the most significant bit (MS
The logical sum is calculated with the second video data 2002 allocated only to B). Therefore, the most significant bit (MSB) of the first video data 2001 is always reflected in the second most significant bit, and the second video data has the most significant bit (MSB).
B), the combined display can output both video data information. However, since the first video data 2001 is shifted by one bit in the lower direction, the luminance is reduced to half in the combined area. However, display disturbance in the synthesis area can be completely prevented.

FIG. 22 shows a display image diagram for the seventh embodiment according to the present invention. In the present embodiment, a part of high-resolution video data is used as background (border) display data when displaying low-resolution video data in a display panel supporting high resolution. In FIG. 22, first, after switching to low-resolution video data after displaying high-resolution video data corresponding to the panel size, the display is performed before switching in the display panel display area other than the low-resolution video data display area. By continuously displaying the high-resolution video data, it is possible to use the high-resolution video data as background data (border).

FIG. 23 shows an outline of the frame memory operation for the display image of FIG. First, in writing high-resolution video data, input video data is sequentially written into the entire memory area for one frame. Next, when switching to the low-resolution video data, the low-resolution video data is overwritten only in the memory area corresponding to the portion displaying the low-resolution video data in the frame memory in which the high-resolution video data is written. . At this time, the data in the frame memory is low-resolution video data and high-resolution video data is stored in an area other than the low-resolution video data. By reading the data stored in this memory by the same operation as the memory read operation when displaying high-resolution display data, low-resolution video data is displayed on the display panel, and high-resolution video data is stored in other areas. It can be displayed as background data (border).

FIG. 24 is a schematic block diagram showing an eighth embodiment according to the present invention. In FIG. 24, reference numeral 2401 denotes a selector circuit for selecting either video data 1 or video data 2, and reference numeral 2402 denotes a selector circuit for selecting which frame of a frame memory provided with two frames of the selected video data. , 2403 is the frame memory 1,
2404 is the frame memory 2 and 2405 is the frame memory 1
A selector circuit for selecting display data of either 2403 or frame memory 2 2404 is shown.

First, the selector circuit 2402 is selected so that video data is written to the frame memory 12403. During this time, the selector circuit 2405 is selected so that the data read from the frame memory 22404 is displayed on the liquid crystal panel. In the first frame, the selector circuit 2401 selects the video data 1 and writes it to the frame memory 12403. In the second frame, the selector circuit 2401 selects the video data 2 and stores it in the frame memory 1 2403.
Write to.

In the third frame, in order to display the display data stored in the frame memory 1 2403 on the liquid crystal panel, the selector circuit 2405 is operated by the frame memory 2 2.
The state is switched from the 404 selection state to the frame memory 1 2403 selection state. At the same time, writing to the frame memory is also performed from the frame memory 1 2403 to the frame memory 22404.
The selector circuit 2402 is switched so that In the third frame, the selector circuit 2401 is selected so that the same video data 1 as the first frame is written in the frame memory 22404 again.

Next, in the fourth frame, as in the second frame, the selector circuit 2401 is selected so that the video data 2 is written into the frame memory 22404. Hereinafter, this control is repeated. That is, the selector circuit 2401 switches the selection between video data 1 and video data 2 for each frame,
02, the selector circuit 2405 switches the selection between the frame memory 1 2403 and the frame memory 2 2404 every two frames.
Therefore, the display on the liquid crystal panel is a video in which both the video data 1 and the video data 2 are thinned out every two frames.

FIG. 25 shows another configuration example different from the configuration of FIG. In the case of FIG. 24, it is assumed that the input video data 1 and video data 2 are digital data, whereas the configuration in FIG. 25 is based on analog data.

In FIG. 25, reference numeral 2501 denotes a PLL for reproducing a dot clock based on a horizontal synchronization signal from video data 1
Circuits 1 and 2502 are also PLL circuits 2 and 2503 for reproducing a dot clock based on a horizontal synchronization signal from video data 2, and a selector for selecting a dot clock reproduced from the PLL circuit 1 2501 or the PLL circuit 2 2502. A circuit 2504 converts an analog video data 1 or video data 2 into digital data using a dot clock selected by the selector circuit 2503.
Each of the D conversion circuits is shown.

The operation of this configuration example is the same as that of the configuration example shown in FIG. 24, except that analog data is converted into digital data. Regarding the analog-digital conversion control, when the selector circuit 2401 selects the video data 1, the selector circuit 2503 selects the PLL circuit 1 2501 and reproduces the dot clock based on the horizontal synchronization signal from the video data 1. . An A / D conversion circuit
Output to 2504, and at the timing synchronized with this clock,
The analog video data 1 is converted into digital video data. Similarly, when the selector circuit 2401 selects the video data 2, the selector circuit 2503 operates as the PLL circuit 22.
502 is selected, and the dot clock is reproduced based on the horizontal synchronization signal from the video data 2. This dot clock is A /
The signal is output to the D conversion circuit 2504, and the analog video data 2 is converted into digital video data at a timing synchronized with the clock.

FIG. 26 shows a memory write image for each frame and a display image diagram in the present embodiment having the configuration shown in FIGS. 24 and 26. In the writing operation, the video data 1 is stored in the frame memory 1 in the first frame.
In the second frame, the video data 2 is also written in the frame memory 12403 in the second frame. Next, in the third frame, the video data 1 is written into the frame memory 2 2404 again, and in the fourth frame, the video data 2 is written into the frame memory 2 2404. In the reading operation, the frame memory 2 240 is read in the first and second frames because the data is read from the frame memory in which the writing is not performed.
4 and read from the frame memory 12403 for the third and fourth frames. Therefore, the display data accompanying the read operation is updated every two frames, so that a frame thinning operation is performed.

As described above, according to the present invention, as described in the first to eighth embodiments, a display device with high usability can be realized by devising a control method for a frame memory using a high-resolution display panel. Can be.

[0093]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

That is, according to the liquid crystal display control device of the present invention, a display panel corresponding to high resolution is divided into a plurality of screens, and different video data is displayed on each divided screen by a small-capacity main memory. Thus, the user can work while checking a plurality of video data on the same screen at the same time, and the effect of improving the working efficiency can be obtained.

Also, a display panel also corresponding to high resolution is divided into a plurality of screens, ideal video data is set by a microcomputer for one of the divided screens, and input video is By setting data and displaying both of these video data on the same screen at the same time, it is possible to adjust input video data while referring to ideal display data.

Also, by dividing the display panel, which also supports high resolution, into a plurality of screens and displaying the input video data in a vertically or horizontally inverted state on a part of the divided screen, When a liquid crystal panel, which is characterized by its thinness, is placed on a plane, the same display data can be simultaneously recognized from both of the two opposing surfaces.

When two pieces of video data (for example, video data from a personal computer or the like and an adjustment menu on an on-screen display) are displayed on the display panel in a superimposed manner, the data depends on both data. An effect is obtained that the two images can be displayed so that they can always be recognized without any problem.

Further, the display panel, which also supports high resolution, is divided into two screens, and in addition, it is configured such that video data from a personal computer or the like can be input in two systems, and these two video data are updated every two frames. By realizing the frame thinning control to be displayed, an effect is obtained that two input video data can be simultaneously displayed on one display panel.

[Brief description of the drawings]

FIG. 1 is an overall configuration diagram showing a first embodiment of a display system using the present invention.

FIG. 2 is a display image diagram for the first embodiment according to the present invention.

FIG. 3 is a flowchart showing a write operation to a frame memory according to the first embodiment of the present invention.

FIG. 4 is a data conversion timing chart at the time of writing to a frame memory according to the first embodiment of the present invention.

FIG. 5 is a data conversion timing chart at the time of reading from a frame memory according to the first embodiment of the present invention.

FIG. 6 is a memory operation diagram for a display image according to the first embodiment of the present invention.

FIG. 7 shows a synchronous DR according to a first embodiment of the present invention.
6 is a memory write timing chart for AM.

FIG. 8 shows a synchronous DR according to the first embodiment of the present invention.
6 is a memory read timing chart for AM.

FIG. 9 is a flowchart showing an example of an adjustment menu display for the first embodiment according to the present invention.

FIG. 10 is an overall configuration diagram showing a second embodiment of the display system using the present invention.

FIG. 11 is a display image diagram for a second embodiment according to the present invention.

FIG. 12 is a display image diagram according to a third embodiment of the display system using the present invention.

FIG. 13 is a schematic configuration diagram of a third embodiment according to the present invention.

FIG. 14 is a memory operation diagram for a display image according to the third embodiment of the present invention.

FIG. 15 is a schematic configuration diagram for another effect of the third embodiment according to the present invention.

FIG. 16 is a diagram illustrating the effect of the display system using the present invention on the fourth embodiment.

FIG. 17 is a memory operation diagram for a display image according to the fourth embodiment of the present invention.

FIG. 18 is a display image diagram according to a fifth embodiment of the display system using the present invention.

FIG. 19 is a schematic configuration diagram of a fifth embodiment according to the present invention.

FIG. 20 is a display image diagram according to a sixth embodiment of the display system using the present invention.

FIG. 21 is an operation principle diagram for a fifth embodiment according to the present invention and an operation principle diagram according to a conventional method.

FIG. 22 is a display image diagram according to a seventh embodiment of the display system using the present invention.

FIG. 23 is a memory operation diagram for a display image according to the seventh embodiment of the present invention.

FIG. 24 is a diagram schematically illustrating the configuration of an eighth embodiment of the display system using the present invention.

FIG. 25 is another schematic configuration diagram of an eighth embodiment of the display system using the present invention.

FIG. 26 is a conceptual diagram illustrating writing and reading of a frame memory according to the eighth embodiment of the present invention;

FIG. 27 is a schematic configuration diagram of a conventional liquid crystal display control device.

[Explanation of symbols]

0101: Frame memory 1, 0102: Frame memory 2, 01
03: Frame memory write control unit, 0104: Frame memory write address generation unit, 0105: Frame memory
Read control unit, 0106: frame memory read address generation unit, 0107: screen division control unit, 0108: write / read switching control unit, 0109: oscillator, 0110: selector circuit 1,
0111 ... selector circuit 2, 0112 ... selector circuit 3, 0113 ...
Selector circuit 4, 0114: buffer circuit 1, 0115: buffer circuit 2, 0116: selector circuit 5, 0117: liquid crystal panel,
0118: Inverter circuit, 0119: Write data conversion control unit, 0120: Read data conversion control unit, 0201: First split screen, 0202: Second split screen, 0203: Third split screen,
0204: Fourth split screen, 0901: Main menu, 0902 ...
Screen division enable / disable setting menu, 0903: Screen division area setting menu, 0904: Video input selection menu, 1001 ...
Microcomputer, 1002: frame memory write enable / disable setting register, 1003: data selection selector circuit, 1601: liquid crystal panel display data, 1602: reflector, 1603: reflector display data, 1905: display data enlargement processing control unit, 2501 ... PL
L circuit 1, 2502 PLL circuit 2, 2504 A / D converter circuit, 2701 frame memory, 2702 synchronization circuit, 2703 write row address counter, 2704 write control circuit, 2705 synchronization signal generation circuit, 2706 Read row address counter, 2707 ... Read control circuit, 27
08: Address switching circuit, 2709: RAS / and CAS /
Generation circuit.

────────────────────────────────────────────────── ─── Continued on the front page (51) Int.Cl. ⁶ Identification code FI G09G 5/36 520 G09G 5/36 520E 520K (72) Inventor Shigehiko Kasai 1099 Ozenji Temple, Aso-ku, Kawasaki City, Kanagawa Prefecture Hitachi, Ltd. Inside the System Development Laboratory (72) Inventor Masashi Mori 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside Hitachi Image Information Systems (72) Inventor Yukio Hiruda 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Hitachi, Ltd. In the image information system (72) Inventor Hiroshi Kurihara 3300 Hayano Mobara-shi, Chiba Electronic Device Division, Hitachi, Ltd. (72) Inventor Tatsumi Mori 810 Shimoimaizumi, Ebina-shi, Kanagawa Prefecture Office System Division, Hitachi, Ltd.

Claims (9)

[Claims] 1. A liquid crystal display control device having a liquid crystal display device for displaying video display data from a personal computer or the like, wherein the liquid crystal display control device has a resolution of the liquid crystal display device that is higher than a resolution of the video display data. In the case of high resolution, a screen dividing means for dividing the display screen of the liquid crystal display device into a plurality of low resolution screens adapted to the video display data, and a still image or A liquid crystal display control device comprising a display control means for controlling display of display data inputted from a personal computer or the like as needed. 2. A liquid crystal display control device comprising a liquid crystal display device for displaying video display data from a personal computer or the like, wherein the liquid crystal display control device has a resolution of the liquid crystal display device which is higher than a resolution of the video display data. A screen dividing means for dividing a display screen of the liquid crystal display device into two or more areas when the resolution is high; and a video display data for one of the display areas divided by the screen dividing means. A liquid crystal display comprising display control means for displaying ideal digital display data as an adjustment reference for various adjustments to the display area and controlling display of video display data from a personal computer or the like in the other display area. Control device. 3. A liquid crystal display control device provided with a liquid crystal display device for displaying video display data from a personal computer or the like, wherein the liquid crystal display control device has a resolution of the liquid crystal display device which is higher than a resolution of the video display data. In the case of a high resolution, a screen dividing means for dividing the display screen of the liquid crystal display device into upper and lower two parts, a normal display of the low resolution video display data on one of the two divided screens, and a display on the other divided screen On the other hand, a liquid crystal display control device comprising a display control means for controlling display of the same low-resolution video display data in a vertically and horizontally inverted state. 4. A liquid crystal display control device including a liquid crystal display device for displaying video display data from a personal computer or the like, wherein the liquid crystal display control device includes a memory capable of storing display data for a plurality of screens. Memory control means for repeatedly reading display data stored in a memory area for one screen of the memory and arbitrarily setting display data serving as an adjustment reference for various adjustments to the video display data in another memory area A liquid crystal display control device comprising: 5. A liquid crystal display device for displaying video display data from a personal computer or the like, the liquid crystal display device comprising: a display control device for inverting and displaying video display data; A liquid crystal display control device comprising a plate. 6. A liquid crystal display control device provided with a liquid crystal display device for displaying video display data from a personal computer or the like, wherein the liquid crystal display control device has a resolution of the liquid crystal display device that is higher than the resolution of the video display data. In the case of high resolution, screen division means for dividing the display screen of the liquid crystal display device into a plurality of low resolution screens according to the video display data,
An enlarged display control means for controlling the whole display and partial enlarged display of the video display data from the personal computer by arbitrarily scaling and displaying each divided area divided by the screen dividing means. Liquid crystal display control device. 7. A liquid crystal display control device provided with a liquid crystal display device for displaying video display data from a personal computer or the like, the liquid crystal display control device superimposing other display data on a part of the display screen, and A liquid crystal display control device comprising superimposing means for making both of the displayed images simultaneously recognizable. 8. A liquid crystal display control device provided with a liquid crystal display device for displaying video display data from a personal computer or the like, wherein the liquid crystal display device has a higher resolution than the resolution of the video display data. After the high resolution video signal is displayed on the entire display screen, when the input video signal is switched to the low resolution video signal, the display area other than the display area of the low resolution video signal is switched to the high resolution video signal before switching. A liquid crystal display control device comprising a display control means for performing display. 9. A liquid crystal display control device provided with a liquid crystal display device for displaying video display data from a personal computer or the like, wherein there are a plurality of input systems for the video data, and the resolution of the video display data is different from the input system. When the resolution of the liquid crystal display device is high, the video signals of the plurality of systems are switched and input for each frame, and the input video signals are temporarily stored in memories in mutually different areas, and are displayed at the time of display. A liquid crystal display control device comprising: display control means for sequentially displaying video signals of a plurality of systems by sequentially reading them out according to a screen.