JP2002182639A - Image processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image processor which synthesizes source image data more than conventional in a processing time of one frame by reducing the frequency in access to source image data. SOLUTION: In Figure, the axis of abscissas shows the frequency in memory access permitted for one frame, and two kinds of source image data to be synthesized are described, and the frequency in memory access of one frame is limited, that is, the frequency in first access processing and that in second access processing are limited to two respectively and that in third access processing is limited to one. Source image data is plotted in a frame buffer for plotting by first and second access processing, and the other source image data is read out after conversion from the frame buffer for plotting and that for display and is superposed on one source image data and is outputted to a display device. As the result, synthesis of source image data is divided into processing at the time of picture composition and that at the time of output to a monitor, and the frequency in memory access for write of the other source image data to a plotting area is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device (monitor) which combines a plurality of image data stored in an image memory.
The present invention relates to an image processing apparatus for displaying an image on a display screen.

[0002]

2. Description of the Related Art In recent years, as microcomputers and memories have become more sophisticated and less expensive, image processing has become possible in home appliances and games, and various images have been displayed on a display screen. Has become. In the above-described image processing, there is a method of forming a moving image by displaying one screen (frame) created by combining a plurality of source image data on a display screen of a display device in chronological order.
Here, assuming that the image processing apparatus employs a frame buffer method, the image processing apparatus has two frame buffers, and when pixel data of an image synthesized from one frame buffer is output to a display circuit, the other frame buffer is used. In the buffer, the image synthesis of the next frame performs a drawing process of synthesizing images of a plurality of source images. The image processing apparatus uses the two frame buffers alternately for output and drawing.

[0003] The above-mentioned frame buffer image synthesizing process will be briefly described with reference to FIG. The drawing apparatus 100 includes a drawing circuit 101 and a RAM (Random Acces
s Memory) is composed of an arbitration circuit 102, a transfer circuit 103, and a display circuit 104. The source image data stored in the ROM 105 is read out, and the RAM 106 is rendered for image synthesis of a plurality of source image data. Perform processing. The RAM 106 has a display area 111 and a drawing area 112 as two frame buffers. Here, in the RAM 106, for the sake of explanation, the functions of the respective frame buffers are specified and indicated as the display area 111 and the drawing area 112.
As described above, these two frame buffers are alternately used for display and drawing. An area 110 shows the area of the buffer memory (display area 111 and drawing area 112) in the RAM 106 and the memory map of the source image data area 113.

When the image processing apparatus is started by a CPU (not shown) or the like, the transfer circuit 103 reads the ROM (Read On
ly Memory) · 105, a plurality of source image data to be used for image composition are read, and are developed and stored in the corresponding source image data area 113 via the RAM arbitration circuit 102. The drawing circuit 101 performs image synthesis of a plurality of source image data, and writes pixel data of a synthesized image obtained as a result of the image synthesis into the drawing area 112. At this time, the display circuit 104 reads out the already synthesized image data from the display area 111 and outputs the image data to the monitor 107 in units of pixel data. The RAM arbitration circuit 102
When the transfer circuit 103 reads the source image data from the ROM 105 and writes it to the RAM 106,
Each source image data read out from 105 is stored in RAM
At 106, the address of the source image data area 113 to be written is determined.

When performing image synthesis in the drawing area 112, the RAM arbitration circuit 102 stores the source image data read from each source image data area 113 in the address of the source image data area 113 and in the drawing area 112. The address to be written to the drawing area 112 is calculated based on the address. With the above-described configuration, the drawing apparatus 100 performs image combining processing of a plurality of source image data for each frame based on the source image data developed in the RAM, and sequentially outputs the combined image. , A predetermined moving image is displayed on the monitor 107.

[0006]

The above-described conventional frame buffer type image display apparatus may not be able to synthesize an image within the processing time of a synthesized image of one frame. That is, in the image display device, the monitor 107
When the images to be displayed are combined, all the source image data necessary for the combination is read from the source image data area 113, and each time one source image data is read, the sequentially read source image data is written into the drawing area 112. Going is necessary.

When the image processing apparatus is started,
Necessary source image data is read from the ROM 105 and expanded in the source image data area 113 of the RAM 106. Depending on the frame, the transfer circuit 103 reads new source image data and uses the unused source image data. Is stored in the source image data area 11
3 needs to be overwritten. As described above, in order to generate a composite image of one frame, the RAM
It is necessary to access the reading and writing of the source image data at 106, the reading of the source image data from the ROM 105 and the writing of the source image data to the RAM 106. All of these access processes need to be performed within the processing time of a composite image of one frame.

In particular, access to read and write of the source image data in the RAM 106 is required by the number of source image data to be synthesized, so that the occupation ratio of the bus width is increased and the time margin for image processing is increased. Causes pressure. For this reason, in the conventional image processing apparatus, when the number of source image data to be combined increases, the number of accesses to the RAM 106 increases, and the necessary number of source image data is combined in one frame. There is a disadvantage that it cannot be done in time. As a solution, it is conceivable to increase the transfer amount of image data from the memory. However, in order to increase the bandwidth indicating the amount of data transferred per unit time (for example, 100 Mbytes / sec when the transfer clock frequency is 100 MHz and an 8-bit bus), the transfer bus is increased and the data bus width is increased. However, this is costly in terms of hardware, and there is a limit to increasing the transfer amount.

Therefore, in the conventional image processing apparatus, as another solution, it is necessary to draw a necessary image on the source image data to be combined in advance. However, many images (eg,
If the character) is drawn, the use of these source image data is limited only to a specific frame, and there is a problem that the degree of freedom in using each source image data is reduced. As a result, the conventional image processing apparatus has a ROM 1 for synthesizing the image of each frame.
05, it is necessary to store more source image data, and for each frame, it takes time to read out the source image data necessary for the composition from the ROM 105 and develop it in the RAM 106, which also has a margin of time. Causes the problem of reducing Further, as another solution, 1
Reducing the number of frames displayed per second (frame rate) can increase the number of memory accesses that can be used per frame, but this solution involves reducing the frame rate and causing the display to flicker on the display screen. There is a problem that the quality of the displayed image deteriorates.

The present invention has been made under such a background and reduces the number of times of memory access of source image data to be synthesized. An object of the present invention is to provide an image processing device capable of performing composition.

[0011]

An image processing apparatus according to the present invention synthesizes a plurality of predetermined source image data, outputs a synthesized image, sequentially displays the synthesized image on a display device, and displays a moving image. A first memory storing a plurality of source image data used for generating the composite image and a plurality of source image data read from the first memory and composited, and And a display circuit that outputs the synthesized image to an image display device. When the synthesized image is synthesized by the drawing circuit in one storage area, the synthesized image is synthesized from the other storage area. A second memory, which has two storage areas alternately used for drawing or display, from which a composite image is read by the display circuit, The pixel data of the composite image read from the display storage area and the other pixel data of the other source image data not included in the composite image read from the first memory are displayed on the display screen of the image display device. It is characterized in that arithmetic processing is performed for each dot of the corresponding address and output to this image display device.

Further, in the image processing circuit of the present invention, the display device has a line buffer, and stores pixel data for one scanning line of the synthesized image in the line buffer. And the other pixel data at the position corresponding to the scanning line in the source image data of
It is characterized by performing arithmetic processing.

The image processing circuit according to the present invention is arranged such that, when the other pixel data is transparent as a result of the arithmetic processing, the display device outputs the pixel data to the display device, and outputs the other pixel data. Is translucent, after performing translucent processing based on the pixel data and the pixel data, outputting newly obtained pixel data to the display device, and translucent even if the other image data is transparent. If not, the pixel data is output to the display device.

[0014] The image processing circuit according to the present invention is characterized in that the display device indicates relative positions of the composite image and the other source image data on the relative position information of the composite image and the other source image data. And generating an address of the pixel data to be subjected to the arithmetic processing and the other pixel data based on the relative position information.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Before describing the configuration, an outline of the present invention will be briefly described. As described in the conventional example, the frame buffer method has two frame buffers (second
When the stored composite image is read from one frame buffer (for display), the source image data is written to the other frame buffer (for drawing). Here, in order to synthesize the source image data in the drawing frame buffer and to output the synthesized image data to the display device, even if only one type of source image data is used, at least three times of memory Access processing is required. That is, the following access is required. (1) First access processing in reading out the source image data (2) Second access processing in writing the source image data read out in (1) to the drawing frame buffer (3) Image synthesis is completed, Third access processing for reading out composite image data from a frame buffer whose function has been changed from drawing to display, in the above-described first to third access processing, a plurality of pieces of source image data or composite image data Pixel data of 1
Since each pixel data (1 dot) is handled, a plurality of memory accesses corresponding to the number of pixel data displayed on the display device are performed.

In (1) to (3), the number of memory accesses in the third access processing of (3) is
The display size of the display device (for example, VGA (Video Gra
phics Array), SVGA (Super Video Graphics Array)
Or XGA (eXtended Graphics Array)), it cannot be reduced because it is fixed. For this reason, in the image processing apparatus of the frame buffer system, reducing the number of times of memory access in the first access processing and the second access processing increases the bandwidth of the memory and improves the drawing performance of the synthesized image. A solution to improve. In FIG. 1, the horizontal axis indicates the number of possible memory accesses in one frame. For example, two types of source image data to be combined are described. For the sake of explanation, the number of memory accesses in one frame is the first
And the second access processing is limited to two times, and the third access processing is limited to one time. Here, according to the present invention, one source image data is subjected to the first and second access processes, and is drawn in a frame buffer for drawing. A method is used in which source image data is read out and output to a display device while being superimposed on one source image data. That is, in the present invention, the synthesis of the source image data is performed by dividing the image data in the drawing area and the time when the pixel data is output to the display device (the monitor 18 in FIG. 2). The number of memory accesses for writing to the drawing area (second access processing) is reduced.

Therefore, in addition to the function of reading out the composite image from the display frame buffer, pixel data of an arbitrary area of the above-mentioned other source image data is read out (fourth pixel data).
Access processing), and by providing the rendering device with a composite output function of superimposing the pixel data on the composite image and outputting the pixel data to the display device, the access of (2) of the other source image data can be omitted. The number of memory accesses can be reduced, and the drawing performance of the image processing apparatus can be improved. The fourth access processing according to the present invention substantially corresponds to the first access processing. As a result, the frame buffer system of the present invention can reduce the second access processing compared to the conventional frame buffer system,
It is possible to give a margin to the memory bandwidth.
Further, in the case of performing the translucent processing, a fifth access for reading an area for performing the translucent processing in the drawing frame buffer is also required between the first access processing and the second access processing. By adding a function of performing a translucent operation to the output function, the fifth access processing can be omitted.

An embodiment of the present invention will be described below with reference to the drawings based on the outline of the present invention described above. FIG. 2 is a block diagram illustrating a configuration example of an image processing apparatus according to an embodiment of the present invention. In this figure, a drawing apparatus 1
It is composed of a drawing circuit 5, a RAM arbitration circuit 6, a transfer circuit 4, and a display circuit 7. The source image data stored in the ROM 2 is read out, and the RAM 3 (first and second
In the memory) is subjected to a rendering process for synthesizing a plurality of source image data. As shown in FIG. 3, the RAM 3 has a display area (or drawing area) 30 and a drawing area (or display area) 31 as two frame buffers.
Are provided. Here, in RAM-3,
For the sake of explanation, the functions of each frame buffer are specified and shown as the display area 30 and the drawing area 31 (second memory). However, as described above, these two frame buffers (the display area 30 and the drawing area 31) are used. 31) is alternately used as a display area and a drawing area for display and drawing.

Returning to FIG. 2, the transfer circuit 4 includes a C (not shown)
When the image processing apparatus is started by a PU or the like, the ROM
A plurality of source image data A, B, and C used for image synthesis of a frame to be output next (one screen displayed on the display image on the monitor 18) in the drawing area 31 are read from 105, and the RAM arbitration circuit 102 is read out. Then, these source image data A, B, and C are respectively developed and stored in the corresponding source image data areas 32, 33, and 34 (see FIG. 3). The RAM arbitration circuit 6 is configured such that the transfer circuit 5
When the source image data is read from the ROM 2 and written to the RAM 3, each source image data read from the ROM 2 is associated with each of the source image data A, B, and C, and RA
Source image data areas 32, 3 to be written in M · 3
The addresses of 4, 35 (first memory) are determined. The drawing circuit 5 reads the source image data A and B from each of the source image data areas 32 and 34 (first access processing), performs image synthesis of the plurality of source image data, and obtains a result of the image synthesis. The pixel data of the composite image is written into the drawing area 31 (see FIG. 3) (second access processing). At this time, the display circuit 17 reads out the already synthesized image data from the display area 30 (see FIG. 3) (third access processing) and outputs it to the monitor 18 in units of pixel data.

The display circuit 7 includes a register 8, a register 9,
Register 10, register 12, address generator, transparent
It comprises a translucent processing circuit 14, a pointer generation circuit 15, a line buffer 16, and a selector 17. The names of the data stored in the registers 8 to 12 are shown in parentheses in FIG. The register 8 has an address indicating the range of the display area 30 and a numerical value of the address width “X1, Y1, H1, W1”.
Is stored. “X1” and “Y1” are the display area 30
And the address indicating the starting point of "W1" and "H".
“1” is a numerical value indicating the width of the address in the x direction and the y direction from the start point of the display area 30. In the register 9, the source image data to be superimposed on the composite image in the display area 30 in the display circuit 7, for example, the source address area in which the source image data C is stored, for example, the address indicating the range of the source address area 34 and the address width Numerical values "X2, Y2, H2, W2" are stored. At this time, it is assumed that the combined image stored in the display area 30 is a combination of the source image data A and the source image data B stored in the source image data areas 32 and 33. "X2 and" Y2 "are addresses indicating the starting point of the source image area 34, and" W2 "and" H2 "
Is a numerical value indicating the width of the address in the x and y directions from the start point of the source image area 34, respectively.

The register 10 stores a numerical value "X3, Y3" of an address indicating a position where the source image data C is superimposed on the composite image in the display area 30 in the display circuit 7. Here, the numerical values “X3, Y3” are relative addresses indicating the position of the start point of the source image data C to be superimposed on the display area 30 with the start point of the display area 30 as the origin, as shown in FIG. In the register 11, a MODE flag indicating whether or not the source image data C to be superimposed on the composite image in the display area 30 includes transparent pixel data is set.
Here, when the MODE flag is “1”, the source image data C includes transparent pixel data, and when the MODE flag is “0”, the source image data C does not include transparent pixel data. The register 12 stores a numerical value of the transparency α (data of a ratio in the range of 0 ≦ α ≦ 1) of the translucent pixel data of the source image data C used for the translucency calculation. Here, the translucent operation is performed in the display area 30.
Is "D" and the gradation data of the translucent pixel data of the source image data C is "E", the newly superimposed pixel data "R" and "G" ,
For each luminance of “B” (Red, Green, Blue signal system), for example, R is calculated as “DR × (1−α) + ER × α”. Here, DR and ER indicate the numerical values of "R" of the gradation data D and E, respectively. The registers 8 to 12 described above are set in advance by the CPU for each frame image combining process.

The line buffer 16 stores pixel data of a horizontal data row stored in the display area 30 in the horizontal direction.
Alternatively, the pixel data of the horizontal data row in the horizontal direction of the source image data C is stored corresponding to the scanning line on the monitor 18. That is, when the MODE flag is “1”, since the source image data C includes transparent pixel data, the display circuit 7 writes the pixel data of the corresponding horizontal data row in the display area 30 to the line buffer. On the other hand, M
When the ODE flag is “0”, since the source image data C does not include transparent pixel data, the display circuit 7 outputs the pixel data of the corresponding horizontal data row of the source image data C,
The source image data C and the pixel data of the corresponding horizontal data row in the non-overlapping display area 30 are written to the line buffer. The address generator 13 responds to the output of the horizontal synchronization signal from the display circuit 7 to the monitor 18 by causing the horizontal data sequence to correspond to the position of the scanning line displayed on the monitor 18, 3
4 for sequentially transferring the horizontal data string at the corresponding vertical position to the line buffer 16 for each pixel data.
Generate an address in M · 3. Further, based on the numerical values stored in the registers 8 to 10, the address generator 13 corresponds to the overlapping pixel data (pixel data of the display area 30) in the horizontal data row stored in the address buffer 16, The display circuit 7 generates an address from which the pixel data of the source image data C is read (fourth access process). Pointer generation circuit 15
Generates a pointer P indicating the position in the line buffer of the pixel data to be transferred to the monitor 18 in synchronization with the timing of displaying the pixel data on the scanning line of the monitor 18.

The selector 17 synchronizes the pixel data read from the position indicated by the pointer P in the line buffer 16 with the pixel data output from the transparent / semi-transparent processing circuit 14 in synchronization with the generation timing of the pointer P. Switching (selection) of which is output to the monitor 18 is performed. The transparent / semi-transparent processing circuit 14 stores the pixel data of the source image data C from the source image data area 34 with the pointer P
Is input in correspondence with the address generated by the address generation circuit 6 in synchronization with the generation timing of the address. At this time, the image finally displayed on the monitor 18 is an image obtained by combining the source image data A, B, and C.

Here, when the MODE flag stored in the register 11 is “0”, the transparent / semi-transparent processing circuit 14 reads out pixel data to the monitor 18
The selector 17 is controlled so as to output the pixel data from the line buffer 16. On the other hand, when the MODE flag stored in the register 11 is “1”, the transparent / semi-transparent processing circuit 14 determines that the source image data C includes transparent pixel data. Is determined for each pixel data (arithmetic processing), and control is performed to select the pixel data of the source image data C or the pixel data output from the line buffer 16. The selection signal is output to the selector 17. That is, the transparent / translucent processing circuit 14 outputs the pixel data from the line buffer 16 to the monitor 18 when the pixel data of the source image data C is transparent, and outputs the source data when the pixel data of the source image data C is not transparent. The pixel data of the image data C is output to the monitor 18. The above-described arithmetic processing is performed by converting one of the pixel data of one scanning line stored in the line buffer 16 and the pixel data of the source image data C corresponding to the display position of the pixel data on the display screen of the monitor 18. Or the calculation of whether to use the pixel data obtained as a result of the translucent processing is performed for each dot (each pixel data) on the display screen of the monitor 18.

When the pixel data of the input source image data C is transparent, the transparent / semi-transparent processing circuit 14 selects the pixel data read from the line buffer 16 to the Output to On the other hand, when the pixel data of the input source image data C is not transparent,
The input source image data C is input to the selector 17.
And outputs it to the monitor 18. Here, each pixel data has, for example, a data configuration shown in FIG. In FIG. 5, a flag T is a transparent flag. When "1", the pixel data is transparent, and when "0", the pixel data is non-transparent. Each of the registers R, G, and B is composed of a plurality of bits, for example, five bits, and indicates a numerical value of luminance (gradation) of red, green, and blue, respectively. Further, when the translucency α of the register 12 is not “0”, the transparent / semi-transparent processing circuit 14 assigns this pixel to the line buffer 16 for all non-transparent pixel data of the source image data C. The above-described translucent operation is performed on the pixel data (this makes it possible to omit the fifth access process as described in the summary of the invention), and new pixel data obtained by the translucent operation is obtained. And outputs a selection signal to be output to the monitor 18 to the selector 16.

When the drawing circuit 5 synthesizes an image in the drawing area 31 (see FIG. 3), the RAM arbitration circuit 102
By controlling the drawing circuit 5, the source image data area 32,
The source image data A and B read from each of the source image data areas 32 and 33 are written in the drawing area 31 based on the address where 33 is arranged and the address where the source image data A and B are arranged in the drawing area 31. Calculate the address. The RAM arbitration circuit 102 transfers the pixel data of the composite image in the display area 30 to the line buffer 16 based on the address generated by the address generator 13 under the control of the display circuit 7, and The pixel data of the image data C is transferred to the transparent / translucent processing circuit 14. With the above-described configuration, the drawing apparatus 1 performs image combining processing of a plurality of source image data for each frame based on the source image data developed in the RAM, and sequentially outputs the combined image. , A predetermined moving image is displayed on the monitor 107.

Next, an operation example of the embodiment will be described with reference to FIGS. For example, a CP not shown
It is assumed that U has started the image processing apparatus. At this time, area 3
It is assumed that 0 is set as the drawing area and the area 31 is set as the display area. Then, in the drawing area 30, the source image data A and B to be synthesized are respectively stored in the source image data area 3
2,33. The source image data C to be superimposed on the composite image at the time when the image is output to the monitor 18 is developed in the source image data area 34. Further, it is assumed that the image finally displayed on the monitor 18 is an image obtained by combining the source image data A, B, and C. On the other hand, at this time, in parallel with the allowable range of the bandwidth,
The pixel data of the composite image is output from the display area 31 to the line buffer 16, and the pixel data read from another source image data area (not shown) and the pixel data of the line buffer 16 are read, respectively. ~ Output processing of pixel data to be displayed on the monitor 18 based on the numerical values stored in the register 12.

Then, the transfer circuit 4 reads the source image data, which is necessary for starting the synthesis and is not developed in the RAM 3, from the ROM 2, and makes the source image data unnecessary in the RAM 3. It is expanded by overwriting the source image data area where is expanded.
Next, the drawing circuit 5 reads the source image data A and B from the source image data 32 and 33, respectively, and performs a synthesis process of the source image data A and B in the drawing area 30. When the synthesizing process of the source image data A and B in the drawing circuit 5 and the transfer of the pixel data to be displayed from the display circuit 31 to the monitor 18 are completed, the display area 3
1 is converted into a drawing area 31, that is, the function as a frame buffer is converted from display to drawing.
0 is converted to the display area 30, that is, the function as the frame buffer is converted from drawing to display. Accordingly, the drawing circuit 5 starts generating a composite image in the drawing area 31, and the display circuit 7 starts processing to transfer pixel data of the composite image in the display area 30 to the monitor 18.

Next, the address generator 13 synchronizes with the horizontal synchronizing signal, and monitors the monitor 18 corresponding to the horizontal synchronizing signal.
Display area 30 output at the scanning line position on the screen of FIG.
Generates the address of the horizontal data string in. And
When the MODE flag of the register 11 is “0” via the RAM arbitration circuit 6 based on the address generated by the address generator 13, the display circuit 7 performs one scanning line on the display screen of the monitor 18 based on the address. The pixel data of the horizontal data row is read out from the display area 30 and the source image data area 34, and the pixel data of the horizontal data row is stored in the line buffer 16 at the corresponding position. On the other hand, based on the address generated by the address generator 13, the display circuit 7 passes through the RAM arbitration circuit 6,
When the MODE flag of the register 11 is “1”, the pixel data of the horizontal data column for one scanning line on the display screen of the monitor 18 is read from the display area 30 based on the address, and the line buffer 16 The pixel data is stored in corresponding positions.

At this time, the address generator 13 expands the numerical value indicating the position and range of the display area 30 in the RAM 3 stored in the register 8 and the source image data C stored in the register 9. The numerical value indicating the position and range of the area (source image data area 34) in the RAM 3 and the numerical value of the relative address where the source image data C is located in the address range of the display area 30 stored in the register 10 Based on this, the address of the pixel data of the source image data C at the overlapping position with the pixel data of the composite image in the display area 30 is calculated in the RAM 3. For example, if the source image data C is superimposed on the composite image as shown in FIG.
The position of the pixel data at the position of the point D on the composite image in the source image data area 34 is “x2, y2”. For this reason, the address generator 13 determines that the start point “x1 + x” where the source image data C is arranged in the display area 30.
3, y1 + y3 ”, the start point“ x ”in the source image data area 34 in correspondence with the address of the start point.
An address of pixel data to be read from the source image data C of “2, y2” is generated.

Then, the pixel data to be displayed is displayed on the monitor 18.
In order to output the pixel data, the pixel data of the composite image and the pixel data of the source image data C are subjected to arithmetic processing to generate pixel data to be displayed on the display screen of the monitor 18, but are stored in the register 11 as described above. The calculation processing of this output is different between the case where the MODE flag is “1” and the case where the MODE flag is “0”. Therefore, the related processing for outputting the pixel data to the monitor 18 will be described below with reference to the monitor of FIG. A description will be given with reference to a conceptual diagram showing the relationship between pixel data of a composite image and pixel data of source image data C at each dot of a predetermined scanning line displayed on the display screen 18. When the MODE flag stored in the register 11 is “0”, it indicates that the source image data C does not include transparent pixel data. Therefore, the position overlapping the pixel data of the source image data C, that is, The pixel data of the composite image below the source image data is not displayed. Therefore, the line buffer 16 stores the source image data C
Only the pixel data at positions that do not overlap with the horizontal line are read from the horizontal data string corresponding to the scanning lines on the display screen of the monitor 18 in the display area 30. At this time, the address generator 1
3 generates the address for reading out the pixel data of the composite image from the horizontal data row of the display area 30 by skipping the address of the area overlapping with the source image data C and generating the source image data C in the source image data area 34. , The address of each pixel data of the horizontal data row of the source image data C in the skipped portion is generated.

That is, the address generator 13 calculates, for example, the address of the vertical position "y1 + y3" in the scanning line direction.
From "x1, y1 + y3" to "x1 + x3, y1 + y3" and from "x1 + x3 + w2, y1 + y3" to "x1 + w1, y1"
+ Y3 ”is generated. Then, the display circuit 7 responds to the horizontal synchronizing signal of the monitor 18 by “x1, y1 + y3”.
To “x1 + x3, y1 + y3” and “x1 + x3 + w
In the address range from “2, y1 + y3” to “x1 + w1, y1 + y3”, pixel data is read from the display area 30 and written to the line buffer 16, and “x1 + x3 +
1, y1 + y3 "to" x1 + x3 + w2-1, y1 + y3 "
In the address range up to, the pixel data of the source image data C is written to the line buffer 16. Next, when the storage of the pixel data of the horizontal data string for one scanning line from the display area 30 to the line buffer 16 is completed, the pointer generation circuit 15 sequentially stores each pixel data of the line buffer 16. It outputs a pointer P indicating the address position of the address. The display circuit 7 outputs the pixel data of the composite image or the pixel data of the source image data C stored in the line buffer 16 to the monitor 18 via the selector 17 in accordance with the output timing of the pointer P.
Are sequentially output for each dot. That is, the line buffer 1 when the MODE flag described below is “1”
The number of times of memory access when pixel data is stored in No. 6 is “the number of times of access to pixel data of all the horizontal data lines in the display area 30” and “the number of times of access to all pixel data of the horizontal data lines of the source image data C”. In addition. However, the number of memory accesses when storing the pixel data in the line buffer 16 when the MODE flag is “0” is “the number of access times of the pixel data of the portion that does not overlap with the source image data C in the horizontal data row of the display area 30”. "And" the number of accesses to the pixel data of all the horizontal data rows of the source image data C ". As described above, when the MODE flag is “0”, the image processing apparatus of the present invention
Pixel data that does not need to be displayed is removed from the display area 30 by the line buffer 26 as compared with the case where the DE flag is “1”.
It is possible to reduce the number of times of memory access for reading data, so that the overall number of times of memory access can be further reduced, leaving a margin in bandwidth and providing bandwidth for other processing. Become.

On the other hand, the MO stored in the register 11
When the DE flag is “1”, it indicates that the source image data C includes transparent pixel data or translucent pixel data. All pixel data for each scanning line unit (horizontal data row) of the composite image, including the position overlapping the C pixel data, is read out to the line buffer 16.
Next, when the storage of the pixel data of the horizontal data string for one scanning line from the display area 30 to the line buffer 16 is completed, the pointer generation circuit 15 sequentially turns on the line buffer 16.
Output a pointer P indicating the address position where each pixel data is stored. Then, the display circuit 7 reads the pixel data of the composite image at the address position indicated by the pointer P, and, in accordance with the timing of the pointer P, based on the address generated by the address generator 13, the source image data area 34 , The pixel data of the source image data C is read out. The transparent / translucent processing circuit 14 determines whether or not the pixel data of the source image data C is transparent for each read pixel data (arithmetic processing), and selects the pixel data of the source image data C,
A control signal for controlling whether to select pixel data output from the line buffer 16 is output to the selector 17.
At this time, as shown in FIG. 7, the transparent / semi-transparent processing circuit 14 performs the above-described comparison from the address “x1 + x3, y1 + y3” where the composite image and the source image data overlap with “x1 + x3 +
w2, y1 + y3 ". The transparent / translucent processing circuit 14 converts “x1, y1 + y3” to “x1 + x3-1,
y1 + y3 ”and“ x1 + x3 + w2 + 1, y1 +
Pixel data is read from the position indicated by the pointer P in the line buffer 16 and output to the monitor 18 via the selector 17 without performing comparison in the range from "y3" to "x1 + w1, y1 + y3".

When the translucency α of the register 12 is not “0” and the pixel data of the source image data C is transparent, the transparent / translucent processing circuit 14
If the pixel data of the source image data C is not transparent, a control signal for outputting the pixel data of the source image data C to the monitor 18 is sent to the selector 17. That is,
The transparent / translucent processing circuit 14 converts the pixel data for one scanning line stored in the line buffer 16 and the pixel data of the source image data C corresponding to the display position of the pixel data on the display screen of the monitor 18. Output either
That is, it is confirmed whether or not the pixel data of the read source image data C is transparent by dot unit (each pixel data) by the transparency flag T in FIG. 5, and when “T = 1 (transparent)”, the composite image The pixel data is output to the monitor 18 and "T = 0
In the case of (non-transparent), a control signal for outputting the pixel data of the source image data C to the monitor 18 is sent to the selector 17, and the process of selecting the pixel data to be displayed on the display screen of the monitor 18 is performed.

Further, when the translucency α of the register 12 is not “0”, the transparent / semi-transparent processing circuit 14 applies the line buffer 16 to the line buffer 16 for all non-transparent pixel data of the source image data C. The above-described translucent operation is performed with the corresponding pixel data, and new pixel data obtained by the translucent operation is selected, and a control signal to be output to the monitor 18 is output to the selector 16. Accordingly, the selector 17 sequentially outputs pixel data of the composite image or pixel data of the source image data C to the monitor 18 for each dot based on the control signal. As described above, according to the present invention, when the pixel data is output from the display area 30 to the monitor 18 without performing the final synthesizing process of the image displayed on the display screen of the monitor 18 all together in the drawing area. In order to generate a final composite image by superimposing another source image data C not included in the composite image on the composite image in the display area 30 and generate a final composite image, the source image Since the memory access in writing the pixel data of the data C can be reduced, it is possible to prevent a problem that a synthesized image cannot be generated due to lack of time, and it is possible to synthesize more source image data, and , Allowing a margin in the bandwidth, reading the new source image data from the ROM 2 in the open bandwidth, and developing the data in the RAM 3. Seth processing can be performed.

[0036]

According to the present invention, the display device (monitor 1)
8) Final synthesis processing of the image displayed on the display screen
When the pixel data is output from the display storage area (display area) to the display device without being collectively performed in the storage area for drawing (drawing area), the pixel data is included in the composite image of the display area. Overlay other source image data
In order to generate a final composite image, when creating a composite image in the drawing area, it is possible to reduce memory access in writing pixel data of other source image data. It is possible to prevent the generation of a composite image from being disabled, and it is possible to combine more source image data. Further, a margin is given to the bandwidth, and new source image data is read in the open bandwidth, and the first Memory access for expanding to the memory of

[Brief description of the drawings]

FIG. 1 is a conceptual diagram illustrating an outline of a function capable of reducing the number of accesses in the present invention.

FIG. 2 is a block diagram illustrating a configuration of an image processing apparatus according to an embodiment of the present invention.

FIG. 3 is a conceptual diagram showing a memory map of a buffer memory area (a display area 111 and a drawing area 112) and a source image data area 113 in a RAM 3 in FIG.

FIG. 4 is a conceptual diagram showing a relative positional relationship between a display area 30 and a source image data area 34.

FIG. 5 is a conceptual diagram illustrating a configuration example of pixel data.

FIG. 6 is a conceptual diagram illustrating an arithmetic process for pixel data to be transferred to a monitor, that is, each pixel data of a composite image and source image data C;

FIG. 7 is a conceptual diagram for explaining an arithmetic process on pixel data to be transferred to a monitor, that is, each pixel data of a composite image and source image data C;

FIG. 8 is a block diagram illustrating a configuration of a conventional frame buffer image processing apparatus.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Drawing apparatus 2 ROM 3 RAM 4 Transfer circuit 5 Drawing circuit 6 RAM arbitration circuit 7 Display circuit 8, 9, 10, 11, 12 Register 13 Address generator 14 Transparent / semi-transparent processing circuit 15 Pointer generation circuit 16 Line buffer 17 Selector 18 Monitor 30, 31 Display area (or drawing area) 32, 33, 34 Source image data area

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5B057 CA01 CA08 CA12 CA16 CB01 CB08 CB12 CB16 CC01 CE08 CH08 CH11 5C023 AA11 BA11 CA03 DA02 DA04 5C082 AA01 BA12 BA27 BA41 BB15 BB26 CA55 DA54 DA55 DA57 DA64 DA65 DA10

Claims (4)

[Claims] 1. An image processing apparatus that performs a synthesis process on a plurality of predetermined source image data, outputs a synthesized image, sequentially displays the synthesized image on a display device, and generates a moving image. A first memory storing a plurality of source image data used for generation, a plurality of source image data read from the first memory and synthesized, and a drawing circuit for generating the synthesized image; A display circuit for outputting to a display device, and when the synthesized image is being synthesized by the drawing circuit in one storage area, a synthesized image synthesized from the other storage area is read out by the display circuit. A second memory having two storage areas used for drawing or display, wherein the display circuit reads out from the storage area for display. The pixel data of the image and the other pixel data of the other source image data not included in the composite image read from the first memory are arithmetically processed for each dot of the corresponding address on the display screen of the image display device. And outputting the image data to the image display device. 2. The display circuit has a line buffer, and stores pixel data for one scanning line of a composite image in the line buffer, and stores the scanning data in the pixel data and the other source image data. 2. The image processing apparatus according to claim 1, wherein arithmetic processing is sequentially performed on other pixel data at a position corresponding to. 3. The display circuit outputs the pixel data to the display device when the other pixel data is transparent as a result of the arithmetic processing, and when the other pixel data is translucent. After performing a translucent process based on the pixel data and the pixel data, output the newly obtained pixel data to the display device, if the other image data is neither transparent nor translucent, the pixel The image display device according to claim 1, wherein data is output to the display device. 4. The display circuit indicates in which position of the composite image the other source image data is superimposed.
A storage unit for storing relative position information of the synthesized image and other source image data, and generating an address of the pixel data to be subjected to the arithmetic processing and the other pixel data based on the relative position information The image processing apparatus according to any one of claims 1 to 3, wherein the processing is performed.