JPH05249953A - Image display device - Google Patents

Abstract

PURPOSE:To provide a compact high-speed three-dimensional image display device with small-scale structure at low cost by adding a depth value (z) buffer of background image display information to the frame buffer of a three- dimensional animation as a three-dimensional image high speed display means, and using this to represent the background of the animation and the longitudinal display target of a sprite. CONSTITUTION:The color value and z-value of a background image are held in a frame buffer 501 and a z-value buffer 502, respectively, and the color value and z-value of a sprite in a memory 503 and a memory 504, respectively. The value of a sprite starting position displayed on a CRT 508 is set in a resistor 505. The z-value 510 of the background image and the z-value 511 of the sprite are compared to each other by a comparator 512, the AND operation of a comparison result 503 and an area judging result 508 is performed in an AND circuit 521. By using the result as a selection signal 514, either the color information 515 on the background image or the color information 516 on the sprite is selected by a selector 520 and transmitted to the CRT 518 through a digital analog converter 517.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device used in the field of three-dimensional image computer graphics, and more particularly to an image display device for displaying animation by three-dimensional images at high speed.

[0002]

2. Description of the Related Art The prior art will be described below. First, the first conventional technique will be described.

Prior art 1: z-buffer algorithm When creating a three-dimensional image, it is necessary to perform processing (hidden surface removal) to display only the most front object when objects overlap each other in the front and rear. As this method, there is a z-buffer algorithm. In this method, apart from the frame buffer holding the image data, the z
It has a z-buffer, which is a buffer that holds coordinate values of directions. Both frame buffer and z buffer are x and y
Addressing can be performed at coordinates (x, y).

Pixel information written in the frame buffer and the z buffer includes x, y coordinates (x, y), and
It has color information c and coordinates z in the depth direction.

The value of the z buffer at coordinates (x, y) is z
(X, y), where z is the z buffer value of the point to be newly written, if z ≦ z (x, y), the point to be newly written is before the point already written. Of the object (the smaller z is defined as the side closer to the viewpoint), and in that case, the frame buffer c (x,
The contents of the y) and z buffers (x, y) are updated as follows.

C (x, y) c z (x, y) z Here, c and z are the frame buffer value and z buffer value of the point to be newly written to the coordinate (x, y).

If z> z (x, y), the data c of the point to be newly written,
z is on the rear side (farther from the viewpoint) than the data of the points already written, and indicates that writing is not necessary. Therefore, in this case, the values of the frame buffer c (x, y) and the z buffer z (x, y) are not updated.

A feature of this z-buffer algorithm is that the processing order of the points corresponding to each object is arbitrary. Regardless of the order in which they occur, the color information of the object at the foremost point remains in each buffer for the point of each coordinate (x, y).

Shading is often used to create three-dimensional images using the z-buffer algorithm. In shading, the surface of an object is approximated as being composed of small polygons. For each polygon, it is necessary to calculate all the z-coordinates and color values of the points inside the polygon. Normally, the number of polygons that make up an object in one image is several thousand to tens of thousands. Therefore, it takes a long processing time to generate an image.

In particular, even in the case of an animation in which only some of the objects move in the three-dimensional image (in the x, y and z directions), the data of all the objects are recalculated each time, The problem is that it is necessary to generate an image with the above procedure.

The second conventional technique will be described below with reference to FIGS.

Prior Art 2: Sprite Method A sprite method is available as a method for enabling animation in which only a part of an image moves at high speed.

In this sprite method, in addition to the frame buffer 2-2, a plurality of moving picture memories (sprite memories) 2-5 each having a smaller size than that are held.
In each sprite memory 2-5, the display context (display priority) is determined in order. Further, the sprite memory 2-5 is defined to be in front of the frame buffer 2-2 (on the side closer to the viewpoint). Further, information 2-1 indicating where each sprite memory 2-5 is located in the frame buffer is also added.

When the contents of the frame buffer 2-2 are displayed on the CRT as in the case of the display 201, the contents of the sprite memory 2-5 are also read out at the same time, and the regions 104 and 105 where the sprites are displayed are the frames. Instead of the contents of the buffer 2-2, the sprite memory 2-5
Send the contents of CRT to CRT. When a plurality of sprites overlap each other, the data 104 of the foremost sprite is sent to the CRT in accordance with the above-mentioned display priority. As a result, CRT
An image 203 as shown in FIG. 2 is displayed above.

This method enables high-speed moving image processing for so-called two-dimensional images. However, in this method, since the priorities of the display context of the image are determined for each sprite, a three-dimensional image in which a part of the image is projected according to the uneven shape is formed. Can not do it.

[0016]

In the drawing method using the z-buffer described in the prior art 1, a new background image has to be generated every time, so that the background image display transition speed is slow and the required time is taken. There are drawbacks. The method using the sprite in the two-dimensional image display described in the prior art 2 can draw at high speed, but since the context (priority order) of the background image and the display information by the sprite is determined for each sprite, the unevenness / shape of the image Therefore, there is a problem that a three-dimensional image display in which a part of the shape is exposed to the front cannot be performed. Therefore, it is an object of the present invention to provide a three-dimensional image display device that operates at high speed. In other words, it is an object of the present invention to provide a high-speed three-dimensional image display device which is compact in terms of hardware, has a relatively small device configuration, and can be realized at low cost.
Further, it is another object of the present invention to provide a three-dimensional image display device which has a greatly improved animation display operation applicable to a game machine or the like.

[0017]

In order to achieve the above object, the image display device of the present invention has the following features.

An image display device according to a first aspect of the present invention includes a frame buffer for storing image information, a z-buffer for storing a depth value of the image information, a plurality of moving image buffers for storing a plurality of moving image information, A moving image depth buffer that stores a depth value of moving image information, a display unit that displays the image information and the moving image information, and a corresponding address when the image information and the moving image information are displayed at a predetermined address on the display unit. Comparing means for comparing the depth value of the image information in the z buffer with the depth value of the moving image information for each of the plurality of moving image depth buffers, and the image information in the frame buffer based on the comparison result in the comparing means. And a control means having a function of transferring any one of a plurality of pieces of moving picture information in the moving picture buffer to the display means. It is a symptom.

The image display device according to a second aspect is the image display device according to the first aspect, further comprising an address for displaying the moving image information in each of the moving image buffers on a predetermined address in the display means. A position register for storing is provided, and by rewriting the contents of the register, it has a function of displaying the moving image information on a different address in the display means without changing the moving image information in the moving image buffer. I am trying.

An image display device according to a third aspect is the image display device according to the first aspect, wherein the comparing means uses either the image information or the moving image information when comparing the depth values. The feature is that the comparison operation is performed after adding a predetermined offset value.

An image display device according to a fourth aspect is the image display device according to the first aspect, wherein the control means displays the image information and the moving image information displayed on the display means and their depth values. It is characterized by having a function of feeding back and storing it in the frame buffer and the z buffer.

An image display device according to a fifth aspect is the image display device according to the first aspect, further comprising an image line buffer for storing image information in the frame buffer corresponding to one line of the display means and the image line buffer. A z-value line buffer of depth values in the z-buffer relating to image information, reading information for one line in the moving-picture buffer, and a z-value in the moving-picture depth buffer corresponding to the moving-picture information and the z-value. The z value in the z value line buffer is compared, the information on the viewpoint side is stored in the image line buffer, and this operation is repeated for the number of the moving image buffers. It is characterized by having a function of transmitting to a display means.

An image display device according to a sixth aspect is the image display device according to the fifth aspect, wherein at least two image line buffers are provided, and information in one image line buffer is transferred to the display means. When this is done, the other image line buffer has a function of producing display data for the next one line.

An image display apparatus according to a seventh aspect of the present invention is a plurality of frame buffers for storing image information or moving image information, a plurality of z buffers for storing depth values of the image information or moving image information, the frame buffer, It comprises a plurality of processors provided corresponding to a z-buffer and a display means for displaying the image information and the moving picture information. The plurality of processors are connected in a plurality of stages, and each processor has the image information and the moving picture information. When displaying at a predetermined address on the display means, a comparison means for comparing a depth value in the z buffer corresponding to the address with a depth value of the image information and moving image information input from the processor in the preceding stage, Image information in the frame buffer, moving images in the plurality of moving image buffers based on the comparison result in the comparing unit. It is characterized by comprising a control means for transferring one of the broadcast to the next processor.

[0025]

The sprite method in the conventional two-dimensional image display device can draw at high speed, but the context (priority order) of the background image and the sprite display information is determined for each sprite. For this reason, 1
There is a drawback that it is not possible to display a three-dimensional image such that the part is in front. On the other hand, in the three-dimensional image display device of the present invention,
As a three-dimensional image high-speed display means, a background image display information depth value z buffer is added to the frame buffer of the three-dimensional animation, and by using this, the background of the animation and the display object before and after the sprite can be represented. The three-dimensional sprite is a rectangular image data smaller than the frame buffer and can have az value for each pixel area range.
When the RT display is performed, the sprite data which is scan-lined and displayed is fetched, and the z values are compared in size, and only the one in front (viewpoint side) is regarded as the display data. Thus, the 3 of the present invention
In the three-dimensional image display device, it becomes possible to perform three-dimensional high-speed moving image processing in which sprite information before and after the background image is inserted.

It is also conceivable to extend the sprite pattern to have an α value. As a result, it is possible to realize an inexpensive and high-speed three-dimensional image display device that is compact in terms of hardware and can be configured in a relatively small device.
If the present invention is applied to an animation display device such as a game machine, the efficiency of drawing operation can be greatly improved.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the outline of the present invention will be described with reference to FIGS. FIG. 1 is a basic conceptual diagram of the present invention.

In the three-dimensional image device of the present invention, the prior art 1
As in the case of the z-buffer algorithm described above, the z-buffer and the sprite memory 5 are added to the frame buffer.
03,504 is attached. This sprite memory 50
3, 504, the color information has the same number of bits (per pixel) as the frame buffer, and the z information has the same number of bits (per pixel) as the z buffer. The size of the area of the sprite memory is usually smaller than that of the frame buffer, but it may have the same size as the frame buffer.

The image data held in the frame buffer and the z buffer will be referred to as a background image 301. C
Contents of sprite memory 3 when displayed on RT518
02 is read out together with the image data in the frame buffer and z buffer, and both are combined. At this time, in the sprite data, z value smaller than the background image,
That is, for 304, the color value of the sprite is sent to the CRT 518 instead of the color value of the background image. This makes CR
The image synthesized and displayed on T518 is like 303.

The above processing is realized by the image processing apparatus having the configuration of FIG. The color value of the background image is held in the frame buffer 501 and the z value is held in the z buffer 502. Sprite color values are stored in memory 503 and z values are stored in memory 5.
It is held at 04. Also, the start position of the sprite displayed on the CRT 518 (the position of the upper left corner of the sprite)
Is set in the register 505. Address generator 5
06 sends the display address 507 to the frame buffer 501 and the z buffer 502 sequentially in synchronization with the refresh of the CRT 518. On the other hand, the address generator 506 determines that the position where the sprite is displayed is reached based on the values of the sprite start position and the display position, and the area determination result 50
8 is output to the AND circuit 521, and the address 509 related to the sprite memory is output.

Background image z value 510 and sprite z value 5
11 are compared by the comparator 512. The comparison result 513 (assumed to be 1 when the sprite z value is small),
The AND operation of the area determination result 508 (assumed to be 1 in the sprite display area) is performed in the AND circuit 521, and the result is used as the selection signal 514, and the selector 520 determines whether the background image color information 515 (the selection signal is 0). Alternatively, one of the sprite color information 516 (selection signal is 1) is selected and sent to the CRT 518 via the digital-analog converter (DAC) 517.

Using the image display device having the above-described configuration, when the position of the object in the sprite memories 503 and 504 is changed, the same three-dimensional image whose position has been moved can be displayed by simply rewriting the contents of the sprite start position register 505. Since it can be displayed on the CRT 518, 3
Dimensional animation becomes possible by simple operation.

Next, an image display apparatus as a first embodiment of the present invention will be described with reference to FIGS. 6, 7 and 8.

The overall structure of the image display device of this embodiment is shown in FIG. In contrast to FIG. 1 of the outline of the invention, a bus 601 for writing data to a frame buffer, a z buffer, and a sprite memory from the outside, a z offset register 60
2. Registers 603 and 604 for temporarily holding the color information of the frame buffer and sprite, and a delay register 60 for delaying the result of the comparator by one clock.
5 is newly added.

In the following description, the size of the frame buffer is 512 × 512 pixels, and x and y are both 9 bi.
It shall be addressed by a counter of t. The size of the sprite is 32 × 32 pixels. Further, the z buffer is assumed to be composed of 1 pixel 8 bits. However, even if another number of bits is used, the z buffer can be realized in exactly the same manner.

FIG. 7 is a block diagram of the address generator 506. A display address generator 701 generates an address for normal CRT display. The address is updated once per clock with respect to the reference clock and output. From the outputs x702 and y703, addresses x'704 and y'705 for the sprite memory are generated. The address is calculated by the subtracters 706 and 707 as in the following equation. Here, xs and ys are sprite start positions, and the sprite start position register 505 is x,
Each of y has start positions xs708 and ys709. The sprite start position register 505 has a function of externally fetching a new value via the signal lines 711 and 712 and changing its content.

X '= x-xs y' = y-ys Whether or not it is the sprite display position is determined by the determination circuit 710 using the following equation.

0 <= x '<32 0 <= y'<32 Therefore, the judgment circuit 710 outputs the value 1 to the judgment result output 508 when both x and y satisfy this condition.
The subtraction result x'704 and y'705 together form the address 509 to the sprite memory.

The z comparator will be described with reference to FIG. In the z comparator, a predetermined offset value (z offset) is added to the z value (sprite) of the sprite, and then the z value of the background image is compared. That is, when the following conditions are satisfied, the comparison result 5
"1" is output as 13.

Z sprite + z offset ≦ z background where z sprite is the z value of the sprite, z offset is the z offset value of the sprite, and z background is the z of the background image.
It is a value. Sprite z-value 511 and background z-value 510
Is an 8-bit unsigned numerical value. On the other hand, z offset 8
01 is a signed number in 2's complement notation and takes a value of 9 bits. The z sprite 511 has a code bit of 0 at the top.
Is added and added by the adder 802, and the addition result 803 becomes a signed bit number of 9 bits. z background z value 51
For 0, 0 is added to the highest order as a code bit, and the comparison result 513 is output by the magnitude comparator 804 with a sign.

The comparison result once enters the delay register 605 and, at the next clock cycle, acts as a selection signal for the selector 520, and the background image color information stored in the temporary register 603 and the sprite color stored in the temporary register 604. Any of the information is selected.

That is, the z value comparison and the color value selection are pipeline operations in two stages. The reason why the pipeline structure is adopted is that it is difficult to perform both z value comparison and color value selection within one clock cycle in which the dot rate of display on the CRT 518 is short.

In this embodiment, as shown in FIG. 6, an offset register 602 for z is provided, and this register 602 also has a writing means like the sprite start position register 505. Therefore, even if the object represented by the sprite moves not only in the x and y directions but also in the depth direction, a new three-dimensional image can be displayed only by rewriting the register.

In this embodiment, a random access memory is used for the frame buffer and the z buffer, but a dual port RAM is used as is often used in an ordinary image display system, and a serial read is used for display. It is also easy to use a port.

The embodiment described above is for the case where there is one sprite memory, but the structure of the modules constituting a plurality of sprite memories will be described below with reference to FIGS. 9 and 10. As shown in FIG. 9, the functions of comparing the sprite memory with the z value and selecting the color information are modularized, and each module 901 as a unit of the sprite memory.
Can be connected in series as many times as necessary.
As a result, it becomes possible to simultaneously display different sprites on the screen by the number of connected modules 901. As shown in FIG. 9, color information 902 and z value 903 are sequentially input to this module 901 in synchronization with a reference clock 910 for each clock. Further, a vertical synchronizing signal 904 and a horizontal synchronizing signal 905 are given as synchronizing signals for CRT control. These signals have two purposes:
Due to (1) and (2), each module 901- of this module
1, 901-2, ..., 901-N and sent to the CRT.

(1) Since the final color signal sent to the CRT is delayed by the number of modules, it is necessary to delay the synchronization signals 904 and 905 by the same time accordingly.

(2) Used to initialize the counter in the module.

Furthermore, a plurality of bits for setting various parameters and internal memory for this module 901.
The command signal 906 consisting of

The following modules 901-2 and the following modules are shown below.
The flow of various signals input to 901-N will be described.
First, as the output of the first-stage module 901-1, color information 902-2, z value 903-2, and vertical synchronization signal 904-
2, horizontal sync signal 905-2, command signal 906-2
Is output. Each of these signals is input to the subsequent modules. These pieces of information are input information 902-1, 903-1, 904 of the first-stage module 901-1.
Since it is the same as -1, 905-1 and 906-1, description thereof will be omitted.

The data read from the frame buffer 502 is input to the color information 902 of the input of the module 901-1 in the first stage. As the z value information input 903, the data read from the z value buffer 501 is input. As the output of the module 901-N at the final stage, the color information 902-N is sent to the CRT 518 via the DAC 517.
Sent to the vertical 904-N and horizontal sync signal 905-N.
Is sent as a sync signal to the CRT 518. On the other hand, the z value information and the command signal are not transmitted to the CRT.

A signal 920 as an identification number for each module is also input to each module 901.

FIG. 10 is a block diagram showing the internal structure of the module 901-1. First, processing of addresses of memories such as the c memory 503 and the z memory 504 will be described. When the vertical synchronizing signal 904-1 becomes active, the value of the y start register 1002 is transferred to the y counter 1001.
Further, the y width counter 1003 is set to the y width register 1004.
The value is transferred.

Thereafter, each time the horizontal synchronizing signal 905-1 becomes active, the value of the y counter 1001 is decremented by one.

When the y counter 1001 becomes 0, the value in the y counter 1001 is not decremented. If the content of the y start register 1002 is 0, it is not decremented at all.

When the y counter 1001 is 0, the y width counter 1 is activated each time the horizontal synchronizing signal 905-1 becomes active.
The value of 003 is decremented by 1.

When the y width counter 1003 changes from 0 to -1, the value in the y width counter 1003 is not decremented thereafter.

When the horizontal synchronizing signal 905-1 becomes active, the x start register 100 is set in the x counter 1005.
The value of 6 is stored in the x-width counter 1007 by the x-width register 100.
A value of 8 is transferred.

Thereafter, x is synchronized with the reference clock 910.
The value of the counter 1005 is decremented by one.

After the x counter 1005 reaches 0, the x counter x1001 is not decremented. If the content of the x start register 1006 is 0, it is not decremented at all.

When the x counter 1005 is 0, the value of the x width counter 1007 is 1 in synchronization with the reference clock 910.
Decremented one by one.

After the x-width counter 1007 has changed from 0 to -1, the x-width counter 1007 is not decremented.

X counter 1005, y counter 1001
Is 0, x width counter 1007, y width counter 1
If 003 is not 0, the sprite is displayed on the CRT. The area determination unit 1010 outputs to the AND circuit 1052 a signal 1011 indicating that it is in the sprite display period under the above conditions.

X width counter 1007, y width counter 10
A signal 1009, which is a signal obtained by inverting the signal except for the sign bit of 03, is generated in the c memory 503 and the z memory 50.
4 is input as an address.

For example, sprite memory or c memory 5
03, when the size of the z memory 504 is 256 * 256 pixels, the X (Y) width counters 1007 and 1003 are each configured by 9 bits including a code. If the size of the sprite is 32 * 32 pixels, the value 31 (11111 in hexadecimal) is preset in the X (Y) width register 1008.

When the vertical synchronizing signal 904-1 is input to the X (Y) width counter 1007, the value 31 (000011111) of the X (Y) width register 1008 is loaded, and thereafter the x width counter 1007 is -1. (1111111
It is decremented sequentially until 11). When the horizontal synchronizing signal 905-1 is input, the y width counter 1003
Is decremented and the x-width register 1008 again has 3
1 is loaded.

The y-width counter is decremented to the value obtained by subtracting -1 from the y-width register 1004.

In the above case, the c memory 503,
The change of the address input to the z memory 504 is shown below. Here, the first 8 bits of the address are the x coordinate and the second 8
The bit indicates the y coordinate.

[0068]

[Table 1] This is the end of the description of the address processing for the c memory 503 and the z memory 504 as sprite memories.

Next, the data processing of the module 901-1 will be described.

The c value of the first stage frame buffer 502 and the z value of the z value buffer 501 enter the c input register 1020 and the z input register 1021 in synchronization with the reference clock 910. At the same time, the contents of the c memory 503 and z memory 504, which are sprite memories, are read out according to the address 1009 and entered into the sprite memory data registers 1022, 1023.

Second Stage In the next clock cycle, the z comparator 512 compares the z value in the z input register 1021 and the c value in the c input register 1023 with the value in the z offset register 602. Further, a signal 1011 indicating the sprite display period,
The result of performing the AND operation with the "non-command signal" from the control unit 1050 is the z-comparison result register 10 of 1-bit configuration.
Write in 30.

Meanwhile, at the same time, the c input registers 1020, z
The contents of the input register 1021, the c value register 1022 for the sprite memory, and the z value register 1023 are pipeline-processed.
026 and 1027 respectively.

Third stage In the next clock cycle, the output of the comparison result register 1030 is used as a selection signal according to the value of this signal and the selector 1
031, 1032, the c value of the sprite in the register 1024 and the c value of the frame in the register 1026 are compared by the selector 1031 and one of them is output to the c output register 1033. Also, the z value of the sprite in the register 1025 and the z value of the frame in the register 1027 are compared by the selector 1032, and one of them is written in the z output register 1034.

The contents of the c output register 1033 and the z output register 1034 are output to the CRT 518.

As described above, the first to third stages are executed by pipeline processing of three stages. That is, 1 at each stage
It receives an input every clock and outputs from the module 901-1 every clock with a delay of three clocks.

Handling of sync signal The vertical sync signal 904-1 and the horizontal sync signal 905-1 are
In order to synchronize the length of the delay of the color signal and the z value in the module 901-1, the registers 1040, 1041, 1
042 is sequentially transferred. The value of the register 1040 at the first stage is sent to the control unit 1050 and used for the address control.

● Handling of commands As initial setting of each module, it is necessary to set various registers and write to c memory and z memory, and these processes are executed based on command signals. A schematic structure of the command signal is shown in FIG.

The command signal 906-1 enters the command register 1043, is decoded by the control unit, and various control signals 1051 are produced. The command includes a code section 1101 for instructing the type of command and an ID section 1102 for instructing the module number. The number of modules that can be connected in series is determined by the number of bits in this ID section. The control unit 1050 compares the value of the ID section 1101 of the command with the ID input signal 920 for the module, performs the corresponding operation in the module only when they match, and when they do not match, the command and data Pass through.

The command signal 906-1 is also transferred to the registers 1043, 1044 and 1045 similarly to the synchronizing signal.

When setting the parameters in the register, the parameters are c input 902-1 and z as color information.
It is provided to the register using the z input 903-1 as the value. C input register 102 depending on the type of command
0 and the contents of the z input register 1021 are the z offset register 602, the z start register 1006, the y start register 1002, the x width register 1008, and the y width register 10.
04.

C memory 503 as sprite information,
The write data to the z memory 504 is also the c input register 1
020, c memory 5 via z input register 1021
03, z memory 504. When the memory write command is issued, both memories are in the write mode and are written in the corresponding areas in the memories according to the preset values of the x width register 1008 and the y width register 1004.

Next, the structure of the control unit will be described with reference to FIG.

The control unit has a structure as shown in FIG. 17, and comprises a decoder unit and a comparator.

ID section 110 in command signal 906-1
In the control unit 1050, 2 is compared with the module ID signal 920 by the comparator 1706 as an ID unit 1705 (comparison of whether they match). The comparison result and the code portion 1101 in the signal 906-1 of the command, that is, the control portion 1
The code portion 1702 in 050 and the synchronization signal 1700 are input to the decoder 1703. With the decoder 1703,
The control signal 1051 is generated.

The decoder 1703 generates various control signals 1051 shown below. A brief description of these control signals will be given below.

Non-command signal Indicates that the current operation is not a command-based operation but a normal display. This signal is 0 during command execution.
And the AND gate 105 shown in FIG.
2, the input data of the module 901-1 is directly output to the outside of the module 901-1 as output data regardless of the output result of the z comparator 512.

Various write signals x start register write y start register write x width register write y width register write z offset write These signals become 1 according to the command code, and the module ID signal 920 and the ID portion of the command signal. 110
When the values of 2 do not match, the value becomes 0.

X counter load signal This signal becomes 1 only when the horizontal synchronizing signal is output.

Y counter load signal This signal becomes 1 when the vertical synchronizing signal is output.

X-width counter load signal This signal becomes 1 in the following two cases.

(1) When the horizontal synchronizing signal is output (2) When the command is the x width counter load command: y width counter load signal This signal becomes 1 in the following two cases.

(1) When the vertical synchronizing signal is output (2) When the command is the y width counter load command ● Memory write signal When the command is the memory write command, this signal becomes 1.

Next, some modifications of the image display device of the second embodiment will be described.

The first modification is that each module 901 has x
The configuration has a plurality of sets of registers for start, x width, y start, y width, and z offset. This makes it possible to display the same sprite information with different depth values at a plurality of positions on the screen, although the data is for the same sprite.

The second modification is that the final image data is DA
Not only the data is sent to C517, but also the data is written in the frame buffer and the z buffer or in a separately provided memory. As a result, it is possible to newly use a combination of some sprite data as background data.

In the third modification, the frame buffer and the z buffer are combined into the same memory, and one word of the memory has both color data and z data. In this case, the sprite memory also has the same number of bits per word. Furthermore, the distribution of the number of bits of color data and z data in one word is made variable. This requires modification of the z comparator. It has a structure with a mask register that represents the z part in one word,
The value of this mask register is ANDed to the input of the z comparator.
Contains the result of the operation. The configuration of this modification is shown in FIGS.
Described in. The input data 1201 consists of 32 bits, and the z portion is continuously taken on the upper bit side of this, and up to 24 bits can be z data. In this case, the minimum color data is 8 bits. Figure 1
2 shows the data processing part in the module.

The read data 1202 in the internal memory is
Input data is taken into the register 1204 and taken into the register 1203. Higher 24 bit data 1 of both registers
205 and 1206 and the z offset register 602 are inputs to the z comparator 512. z offset register 602
Is composed of 25 bits obtained by adding a code bit to 24 bits. The AND of the output of the comparator and the area signal is stored in the register 1030 and becomes the selection signal of the selector 1210. The input data stored in the register 1203 and the read data 1202 of the internal memory stored in the register 1204 are pipeline registers 1207, 1
208 is entered, selected by the selector 1210 at the next clock, entered into the output register 1211, and output data 1212 is entered.
Becomes The z comparator 512 has a 25-bit z mask register 1301. In this register 1301, values are set such that 1 is n (bit) (0 ≦ n ≦ 25) from the higher order and 0 is 25−n (bit) from the lower order.
For example, it is set as "111 .... 000".

Input 1206 is 2 with "0" added at the top.
5 bits and AND with the value of z mask register 1301
The AND circuit 1310 performs the operation, and the operation result is input to the adder 802. This addition result and input 120
Comparator 8 in which the data with "0" added to the top of 5 has a sign
The input of 04 is the same as in the case of FIG.

Next, an image display device according to the third embodiment of the present invention will be described with reference to FIG.

In this embodiment, the sprite buffer and the frame buffer have the same size, and the drawing processors P ₀ , P _{1 to} P _m-1 are provided for each pair of the frame buffer and the sprite buffer. .. There is no difference between the frame buffer and the sprite buffer, and, for example, only the first buffer pair connected in series is used as the frame buffer and the second buffer pair is used as the z buffer. Hereinafter, the entire buffer pair will be referred to as a frame buffer and a z buffer. Since all buffers have the same size, the superimposition using z comparison at the time of display is performed for the entire screen. The m frame buffers are cj (j = 0, 1, ...
There are m drawing processors 1403pj for 401 and z buffer zj1402, and pj is responsible for drawing for cj. When displaying, c0, z0 and c1, z
1 reads data at the same timing, but c2, z
The second and subsequent buffers are read with a constant delay (three reference clocks in the example below) compared to the previous buffer. Module dj (j = 1, 2, ... M-1) 1404 for selecting data while performing z comparison
Each module receives c data 1405, z data 1406 from the corresponding buffer, c input 1407, z input 1408 from the previous module, and c output 1409, z output 1410 to the next module. Give out. FIG. 15 shows a block diagram of the module dj.

Since the module dj performs z comparison and selection, the image display device of the third embodiment having the configuration of FIG. 15 differs from the image display devices of the first and second embodiments in that
Since the frame image and the sprite image are overlapped in the entire display area, it is not necessary to judge the area. Also, z offset is not necessary (it may be). This corresponds to the case where the memory inside the module goes out of the image display device of the second embodiment, and the operation corresponds to this case.

Inputs 1407, 1408, 1405, 14
06 is a register 1501, 1502, 1503, 150
Taken in 4. The contents of the z register are compared by a simple signed comparator 1505, and the comparison result is registered in the register 1506.
Be stored in.

At the same time, the registers 1501, 1502, 15
03,1504 contents of the registers 1511,1512,
1513 and 1514.

The values selected by the selectors 1031 and 1032 are output to the output registers 1033 and 1034.

This structure has an effect different from those of the above-described embodiments. In a graphics system that uses multiple normal drawing processors in parallel, memory access becomes a bottleneck because there is only one frame buffer.
Sufficient drawing performance cannot be obtained, so high-speed 3D animation is difficult. However, by using the configuration of the image display device of the present embodiment, each frame buffer shares a part of the data of all the objects, and finally, these images are superimposed while performing z comparison at the time of display. By doing so, the processing bottleneck disappears. The processing performance is proportional to the number m of drawing processors. There is no theoretical upper limit to the number of drawing processors.

It is needless to say that, in the shared drawing, the processor does not need to redraw the shared portion if the image is not changed.

Finally, an image display apparatus according to the fourth embodiment of the present invention will be described below with reference to FIG.

In the image display device of this embodiment, a line buffer is used for displaying. There are two line buffers (1602, 1603) for color data and one line buffer for z values (1
604) is provided. The frame buffer, z buffer, and sprite data are all in the common memory 1605.

The display processor 1601 takes charge of display control, and the procedure for displaying one line of the CRT 518 is as follows.

One line of the frame buffer is read into the line buffer (c and z).

The data for one line of the sprite that comes on this line is read, and the corresponding portion in the line buffer is updated by performing z comparison.

This procedure is repeated for the number of sprites.

The contents of the line buffer of c are converted to DAC517.
Transfer to CRT 518 via. At this time, one of the data in the two line buffers is selected using the selector 1606.

At this time, the above procedure is repeated again using the other line buffer c and line buffer z.

In this embodiment, unlike the previous embodiments, it is desirable that the sprite memory and the frame buffer or z buffer be in the same memory, but of course they can be placed in different memories. Further, the number and size of sprites can be freely changed without any limitation. However, since the time for displaying one line of the CRT is limited, the upper limit of the number of processing is determined in terms of processing time. The number of line buffers may be larger than two.

[0116]

As described above, in general, it takes time to create one screen for a three-dimensional computer graphic image, and it has been difficult to draw an animation in real time using an ordinary processor. In particular, even when only a part of the image moves, it is necessary to create the image from the beginning, and the image creation speed is still slow. On the other hand, the image display device of the present invention can display an image when only a part of the image moves at an extremely high speed, and enables animation by a three-dimensional image in real time. In the present invention, since the image of the part that does not change can be created in advance over time, or can be created by another means, it has a simple structure, and thus can be manufactured at low cost and with a three-dimensional image animation device or electronic device. A game console can be configured.

Another effect of the present invention is as follows. In the conventional image display device, even if the drawing process is performed in parallel using a plurality of drawing processors, the memory access becomes a bottleneck, the image creation speed does not increase, and high-speed display cannot be performed. Each processor only needs to create the corresponding image, and there is no influence of the overhead in superimposing the whole on the throughput. As a result, the image creation speed increases in proportion to the number of processors, and it becomes possible to construct a high-speed three-dimensional graphics system.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an image display device showing the basic concept of the present invention.

FIG. 2 is a diagram illustrating a sprite method that is a conventional technique.

FIG. 3 is a diagram illustrating a sprite method that is a conventional technique.

FIG. 4 is a diagram illustrating an image display method of the present invention.

FIG. 5 is a diagram illustrating an image display method of the present invention.

FIG. 6 is a block diagram of an image display device that is a first embodiment of the present invention.

7 is a block diagram of an address generator that is a component in the image display device shown in FIG.

FIG. 8 is a diagram showing the components z in the image display device shown in FIG.
The block diagram of a comparator.

9 is a block diagram of a module in which modules, which are constituent elements in the image display device shown in FIG. 6, are connected in series.

FIG. 10 is a detailed internal configuration diagram of the module.

FIG. 11 is a diagram showing a command format.

FIG. 12 is another configuration diagram of the z comparator.

FIG. 13 is another configuration diagram of the z comparator.

FIG. 14 is a block diagram of an image display device according to a third embodiment of the present invention.

FIG. 15 is a block diagram of a module used in the image display device of the third embodiment shown in FIG.

FIG. 16 is a block diagram of an image display device according to a fourth embodiment of the present invention.

17 is a detailed configuration diagram of a control unit used in the image display device shown in FIG.

[Explanation of symbols]

103 Composite display image 2-1 Display address control 2-2 Frame buffer 2-3 P / S 2-4 selector 2-5 Sprite pattern buffer 2-6 z buffer 2-7 Large / small comparator 2-8 z buffer 201 Background image 202 Content of Sprite Memory 203 Display Image 210 Background Image 301 Background Image 302 Content of Sprite Memory 303 Image to be Synthesized and Displayed 304 Video 501 z Buffer 502 Frame Buffer 503 Color Value Memory 504 z Memory 505 Register (Value of Sprite Start Signal) 506 Display address generator 507 Display address 508 Judgment result output 509 Address to sprite memory 510 Background z value 511 Sprite z value 512 z Comparator 513 Comparison result (it should be 1 when the sprite z value is small ) 514 selection signal 515 color information of background image (selection signal is 0) 516 sprite color information (selection signal is 1) 517 DA converter 518 CRT 520 selector 521 AND circuit 601 bus 602 z offset register 603 register 604 register 605 register 701 Display address generator 702 address x 703 address y 704 address x '705 address y' 706 subtractor 707 subtractor 708 start position xs 709 start position ys 710 judgment circuit 801 z offset 802 adder 803 addition result 804 comparison of signed sign 901 Module 902-1 Color information input 903-1 z-value input 904-1 Vertical sync signal input 905-1 Horizontal sync signal input 910 Reference clock 906-1 Command input 911 color Report output 912 z-value output 913 vertical sync signal output 914 horizontal sync signal output 915 command output 920 signal having different value for each module 921 C input 923 z input 1001 y counter 1002 y start register 1003 y width counter 1004 y axis register 1005 x counter 1006 x start counter 1007 x width counter 1008 x width register 1010 area determination unit 1011 area determination result 1020 c input register 1021 z input register 1022 c register read from memory 1023 z register 1024 c value pipe read from memory Line register 1026 c-value pipeline register 1025 z-value pipeline register 1027 z-value pipeline register 1030 z comparison result 1031 selector 1 32 selector 1033 c output register 1034 z output register 1040 register 1041 register 1042 register 1043 command register 1044 register 1045 register 1050 control unit 1051 control signal 1101 code unit for instructing command type 1102 ID unit for instructing module number 1201 input data 1202 read data from internal memory 1203 register 1204 register 1205 register 1023 upper 24 bit data 1206 register 1024 upper 24 bit data 1207 pipeline register 1208 pipeline register 1301 z master register 1310, 1312 AND circuit 1401 m frame buffers cj 1402 z buffer zj 1403 m drawing Processor pj 1404j module dj 1405 c data input 1406 z data input 1407 c data from previous module 1408 z data from previous module 1501 c register 1502 z register 1503 c register 1504 z register 1506 z comparison result 1511 c pipeline register 1512 z pipeline register 1513 c pipeline register 1514 z pipeline register 1601 display processor 1602 color data line buffer 1603 color data line buffer 1604 z line buffer 1605 memory 1700 sync signal 1701 command 1702 code section 1703 decoder 1705 ID section 1706 comparator

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] December 2, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 1

[Correction method] Change

[Correction content]

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0018

[Correction method] Change

[Correction content]

An image display device according to a first aspect of the present invention includes a frame buffer for storing image information, a z-buffer for storing a depth value of the image information, a plurality of moving image buffers for storing a plurality of moving image information, A plurality of moving picture depth buffers for storing the depth value of moving picture information, a display means for displaying the image information and the moving picture information, and displaying the image information and the moving picture information at a predetermined address on the display means,
Comparing means for comparing the depth value of the image information in the z buffer corresponding to the address and the depth value of the moving picture information for each of the plurality of moving picture depth buffers, and the frame buffer based on the comparison result in the comparing means. And a control means having a function of transferring any one of the image information in the inside and the moving picture information in the plurality of moving picture buffers to the display means.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0071

[Correction method] Change

[Correction content]

Second stage At the next clock cycle, z value in z input register 1021, z value in sprite z register 1023, z off
The z comparator 512 compares the value of the set register 602 . Further, the signal 1 indicating that it is the sprite display period
011 and the “non-command signal” from the control unit 1050 and A
The result of the ND operation is written in the z-comparison result register 1030 having a 1-bit configuration.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0100

[Correction method] Change

[Correction content]

In this embodiment, the sprite buffer and the frame buffer have the same size, and the drawing processors P ₀ , P _{1 to} P _m-1 are provided for each pair of the frame buffer and the sprite buffer. .. No differences between the frame buffer and the sprite buffer, for example, only one pair of eyes of the buffer pairs connected in series is used as the frame buffer and the z-buffer. Hereinafter, the entire buffer pair will be referred to as a frame buffer and a z buffer. Since all buffers have the same size, the superimposition using z comparison at the time of display is performed for the entire screen. m frames buffer c j (j = 0,1, ......... m-1) 140
For one and a bar Ffa Zj1402, there are m portrayal processor 1403pj, pj is responsible for drawing against cj. At the time of display, c0, z0 and c1, z1 read data at the same timing, but after c2, z2, each is constant compared to the previous buffer (in the example below, 3 clocks of the reference clock). It is read with a delay of. There is a module dj (j = 1, 2, ... M-1) 1404 for selecting data while performing z comparison, each module having c data 1 from the corresponding buffer.
405, z data 1406, c input 1407 and z input 1408 from the previous module, and c output 1409 and z output 1410 are output to the next module. FIG. 15 shows a block diagram of the module dj.

[Procedure Amendment 5]

[Document name to be corrected] Drawing

[Name of item to be corrected] Fig. 10

[Correction method] Change

[Correction content]

[Figure 10]

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H04N 5/265 7337-5C

Claims (7)

[Claims] 1. A frame buffer for storing image information, az buffer for storing depth values of the image information, a plurality of moving image buffers for storing a plurality of moving image information, and a moving image for storing depth values of the moving image information. A depth buffer, a display unit for displaying the image information and the moving image information, and a display unit for displaying the image information and the moving image information at a predetermined address on the display unit. Comparing means for comparing the depth value and the depth value of the moving picture information for each of the plurality of moving picture depth buffers; An image display device comprising: a control unit having a function of transferring any of the information to the display unit. 2. The image display device according to claim 1, further comprising a position register for storing an address for displaying the moving picture information in each moving picture buffer on a predetermined address in the display means, and the register. An image display device having a function of displaying the moving picture information on a different address in the display means by rewriting the contents of the moving picture buffer without changing the moving picture information in the moving picture buffer. 3. The comparing means, when comparing the depth values, performs a comparison operation after adding a predetermined offset value to either the image information or the moving image information. The image display device described in 1. 4. The control means has a function of feeding back the image information and moving image information displayed on the display means and their depth values to store them in the frame buffer and the z buffer. The image display device according to claim 1. 5. The image display device according to claim 1, further comprising an image line buffer for storing image information in the frame buffer corresponding to one line of the display means, and a depth in the z buffer for the image information. A z-value line buffer of values, and reads out information for one line in the motion picture buffer, and z value in the motion picture depth buffer and z value in the z value line buffer corresponding to the motion picture information. And the information on the viewpoint side is stored in the image line buffer, the operation is repeated for the number of the moving image buffers, and then the information in the image line buffer is transmitted to the display means. An image display device characterized by. 6. The image line buffer is at least 2
One of the image line buffers is transferred to the display means, and the other image line buffer has a function of generating display data for the next one line. The image display device according to claim 5. 7. A plurality of frame buffers for storing image information or moving image information, a plurality of z buffers for storing depth values of the image information or moving image information, and a plurality of z buffers provided corresponding to the frame buffers and z buffers. And a display means for displaying the image information and the moving picture information, the plurality of processors are connected in a plurality of stages, and each processor sets the image information and the moving picture information at a predetermined address on the display means. When displaying, based on the comparison result in the comparison means for comparing the depth value in the z-buffer corresponding to the address and the depth value of the image information and the moving image information input from the processor in the previous stage, , One of the image information in the frame buffer and the moving image information in the plurality of moving image buffers, An image display device, comprising: