JP3481913B2 - Image processing device - Google Patents

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a display device (monitor) by synthesizing a plurality of image data stored in an image memory.
The present invention relates to an image processing device for displaying on the display screen.

[0002]

2. Description of the Related Art In recent years, as microcomputers and memories have become more sophisticated and have become less expensive, image processing becomes possible in home appliances, games, etc., and various images are displayed on the display screen. Has become. In the image processing described above, there is a method of forming a moving image by displaying one screen (frame) created by combining a plurality of source image data in time series on the display screen of the display device.
Here, assuming that the image processing apparatus is a frame buffer system, it has two frame buffers, and when one frame buffer outputs pixel data of an image combined image to a display circuit, the other frame buffer outputs the pixel data of the other frame. In the buffer, the image composition of the next frame is performing a drawing process for compositing a plurality of source images. Then, the image processing apparatus alternately uses the two frame buffers for output and for drawing processing.

The above-mentioned image synthesizing process of the frame buffer method will be briefly described with reference to FIG. The drawing apparatus 100 includes a drawing circuit 101 and a RAM (Random Acces
s Memory) An arbitration circuit 102, a transfer circuit 103, and a display circuit 104, which reads out the source image data stored in the ROM 105 and draws it in the RAM 106 for image composition of a plurality of source image data. Perform processing. The RAM 106 is provided with a display area 111 and a drawing area 112 as two frame buffers. Here, in the RAM 106, each frame buffer is shown as a display area 111 and a drawing area 112 for the purpose of explanation, but
As described above, these two frame buffers are alternately used for display and drawing. In the area 110, the memory map of the area of the buffer memory (display area 111 and drawing area 112) in the RAM 106 and the source image data area 113 is shown.

When the image processing apparatus is started by a CPU (not shown), the transfer circuit 103 causes the ROM (Read On) to operate.
ly Memory) 105, a plurality of source image data to be used for image composition are read out, and are expanded and stored in the corresponding source image data area 113 via the RAM arbitration circuit 102. The drawing circuit 101 performs image composition of a plurality of source image data, and writes pixel data of a composite image obtained as a result of image composition in the drawing area 112. At this time, the display circuit 104 reads the already combined image data from the display area 111 and outputs it to the monitor 107 in pixel data units. The RAM arbitration circuit 102
When the transfer circuit 103 reads the source image data from the ROM 105 and writes it in the RAM 106, the ROM
Each source image data read from the 105
At 106, the address of the source image data area 113 to be written is determined.

Further, the RAM arbitration circuit 102 arranges the source image data read from each source image data area 113 at the address of the source image data area 113 and in the drawing area 112 when the images are combined in the drawing area 112. The address to be written in the drawing area 112 is calculated based on the address to be written. With the above-described configuration, the rendering device 100 performs image combining processing of a plurality of source image data for each frame based on the source image data loaded in the RAM, and sequentially outputs the combined images. A predetermined moving image is displayed on the monitor 107.

[0006]

The conventional frame buffer type image display device described above may not be able to combine images within the processing time of one frame of combined image. That is, in the above image display device, the monitor 107
When synthesizing the images to be displayed on the screen, all the source image data necessary for synthesizing are read from the source image data area 113, and each time one source image data is read, the read source image data is written in the drawing area 112. Going processing is necessary.

Further, when the image processing apparatus is activated,
Necessary source image data is read from the ROM 105 and expanded in the source image data area 113 of the RAM 106, but the transfer circuit 103 reads new source image data depending on the frame and does not use the source image data. Source image data area 11 in which is stored
It is necessary to overwrite by overwriting to 3. As described above, in order to generate a 1-frame composite image, RAM.
It is necessary to access to read and write the source image data in 106, read the source image data from the ROM 105 and write the source image data to the RAM 106. All of these access processes need to be performed within the processing time of the composite image of one frame.

In particular, access to read and write source image data in the RAM 106 is required as many as the number of source image data to be combined, and a large bus width occupancy rate is taken, so that there is a time margin for image processing. It causes pressure. Therefore, in the conventional image processing apparatus, when the number of source image data to be combined is increased, the number of accesses in the RAM 106 is increased, and the necessary number of source image data can be combined within one frame. It has the drawback that it can't be done in time. One possible solution is to increase the amount of image data transferred from the memory. However, in order to increase the bandwidth indicating the amount of data transferred per unit time (for example, 100 Mbytes / sec in the case of an 8-bit bus with a transfer clock frequency of 100 MHz), the transfer clock must be increased to increase the data bus width. However, this increases the hardware cost, so there is a limit to increasing the transfer amount.

Therefore, in the conventional image processing apparatus, as another solution, it is necessary to draw an image required for the source image data to be combined in advance. However, in this way many images (eg,
When a character is drawn, the use of these source image data is limited only in a specific frame, and the degree of freedom in using each source image data decreases. As a result, in the conventional image processing apparatus, in order to synthesize the images of the respective frames, the ROM 1
05, it is necessary to store more source image data in 05, and it is necessary to read the source image data required for composition from the ROM 105 and develop it in the RAM 106 for each frame. Cause the problem of decreasing. Furthermore, as another solution, 1
By reducing the number of frames displayed per second (frame rate), it is possible to increase the number of memory accesses that can be used per frame, but this solution is to reduce the frame rate and display flicker on the display screen. There is a problem that the quality of the displayed image deteriorates.

The present invention has been made under such a background, and the number of memory accesses of the source image data to be combined is reduced, so that more source image data than the conventional example can be processed in the processing time of the image combining of one frame. An object is to provide an image processing device that enables composition.

[0011]

An image processing apparatus according to the present invention synthesizes a plurality of predetermined source image data, outputs a synthesized image, and sequentially displays the synthesized image on a display device to display a moving image. In the image processing device for generating the composite image, a first memory in which a plurality of source image data used for generating the composite image is stored, and a plurality of source image data are read from the first memory and composited, and the composite image And a display circuit that outputs the composite image to the image display device, and when the composite image is being composited by the drawing circuit in one storage area, the composite image is composited from the other storage area. A second memory having two storage areas alternately used for drawing or displaying, in which a composite image is read by the display circuit, On the display screen of the image display device, the pixel data of the composite image read from the storage area for display and the other pixel data of the other source image data not included in the composite image read from the first memory are displayed. It is characterized in that arithmetic processing is performed for each dot at a corresponding address and the dot is output to the image display device.

In the image processing circuit of the present invention, the display device has a line buffer, and pixel data for one scanning line of the composite image is stored in the line buffer, and the pixel data and the other data are stored. In the source image data of the other pixel data at the position corresponding to the scanning line,
It is characterized by performing arithmetic processing.

In the image processing apparatus of the present invention, the display circuit outputs the pixel data of the composite image to the display device when the other pixel data is transparent in the result of the arithmetic processing, If the pixel data of is semi-transparent, the semi-transparent process is performed based on the other pixel data and the pixel data of the composite image, and then the newly obtained pixel data is output to the display device, and When the image data of 1 is neither transparent nor semi-transparent, the other pixel data is output to the display device.

In the image processing apparatus of the present invention, the display circuit indicates at which position of the composite image the other source image data is superimposed, and relative position information of the composite image and the other source image data. Is stored, and addresses of the pixel data of the composite image to be subjected to the arithmetic processing and the other pixel data are generated based on the relative position information.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The outline of the present invention will be briefly described before the description of the configuration. As described in the conventional example, the frame buffer method has two frame buffers (second
When the stored composite image is read from one frame buffer (for display), the source image data is written to the other frame buffer (for drawing). Here, in the frame buffer for drawing, in order to synthesize the source image data and output the synthesized image data to the display device, even if only one type of the source image data is used, at least three times of memory is required. Access processing is required. That is, the following access is required. (1) First access process for reading source image data (2) Second access process for writing source image data read in (1) to a frame buffer for drawing (3) Image composition is completed, Third access processing for reading the data of the composite image from the frame buffer whose function has been changed from the drawing to the display In the above-described first to third access processing, a plurality of source image data and data of the composite image are included. Pixel data of 1
Since each pixel data (1 dot) is handled, a plurality of memory accesses corresponding to the number of pixel data displayed on the display device are performed.

In these (1) to (3), the number of memory accesses in the third access processing of (3) is
The display size of the above display device (for example, VGA (Video Gra
phics Array), SVGA (Super Video Graphics Array)
Or fixed by XGA (eXtended Graphics Array) etc., it cannot be decreased. Therefore, in the frame buffer type image processing device, reducing the number of memory accesses in the first access process and the second access process allows a margin of the memory bandwidth to improve the rendering performance of the composite image. It will be a solution to improve. FIG. 1 shows the number of possible memory accesses in one frame on the horizontal axis. For example, two types of source image data to be combined are described. For the sake of explanation, the number of memory accesses in one frame is the first
It is assumed that the second access processing is limited to twice and the third access processing is limited to once. Here, in the present invention, one source image data is subjected to the first and second access processes, drawn in a frame buffer for drawing, and after this frame buffer is converted from drawing to display, another A method is used in which the source image data is read and is superimposed on one source image data and is output to the display device. That is, in the present invention, the source image data is synthesized by dividing the image synthesis in the drawing area and the time when the pixel data is output to the display device (monitor 18 in FIG. 2), and other source image data is synthesized. The number of memory accesses for writing (second access processing) to the drawing area is reduced.

Therefore, in addition to the function of reading the composite image from the display frame buffer, the pixel data of an arbitrary area of the other source image data described above is read (fourth
Access processing), and by adding a composite output function for superimposing this pixel data on the composite image and outputting the composite image to the display device, the access (2) of the other source image data can be omitted. The number of memory accesses can be reduced, and the drawing performance of the image processing apparatus can be improved. The fourth access processing of the present invention substantially corresponds to the first access processing. As a result, the frame buffer method of the present invention can reduce the second access processing as compared with the conventional frame buffer method,
It is possible to give a margin to the memory bandwidth.
Further, in the case of performing the semi-transparent process, a fifth access for reading out an area to be subjected to the semi-transparent process in the drawing frame buffer is also required between the first access process and the second access process. By adding the function of performing the translucent calculation to the output function, the fifth access process can be omitted.

An embodiment of the present invention will be described below with reference to the drawings based on the above-described outline of the present invention. FIG. 2 is a block diagram showing a configuration example of an image processing apparatus according to an embodiment of the present invention. In this figure, the drawing device 1
It is composed of a drawing circuit 5, a RAM arbitration circuit 6, a transfer circuit 4, and a display circuit 7. The source image data stored in the ROM 2 is read out to the RAM 3 (first and second
Drawing process for image composition of a plurality of source image data. As shown in FIG. 3, the RAM 3 has a display area (or drawing area) 30 and a drawing area (or display area) 31 as two frame buffers.
And are provided. Here, in RAM3,
For the sake of explanation, the function of each frame buffer is specified as the display area 30 and the drawing area 31 (second memory), but as described above, these two frame buffers (the display area 30 and the drawing area) are shown. 31) are alternately used by being selectively used as a display area and a drawing area for display and drawing.

Returning to FIG. 2, the transfer circuit 4 has a C (not shown).
When the image processing device is started by the PU or the like, the ROM
A plurality of source image data A, B, C used for image composition of a frame to be output next (one screen displayed on the display image of the monitor 18) in the drawing area 31 is read from 105, and the RAM arbitration circuit 102 is read. These source image data A, B, C are expanded and stored in the corresponding source image data areas 32, 33, 34 (see FIG. 3). In the RAM arbitration circuit 6, the transfer circuit 5 is a ROM
When the source image data is read from the RAM 2 and written in the RAM 3, the source image data read from the ROM 2 is made to correspond to the source image data A, B, C, and RA
Source image data areas 32 and 3 written in M3
Addresses 4, 35 (first memory) are determined. The drawing circuit 5 reads the source image data A and B from each of the source image data areas 32 and 34 (first access processing), performs image synthesis of the plurality of source image data, and obtains the result of image synthesis. The pixel data of the composite image is written in the drawing area 31 (see FIG. 3) (second access processing). At this time, the display circuit 17 reads the already combined image data from the display area 30 (see FIG. 3) (third access processing), and outputs it to the monitor 18 in pixel data units.

The display circuit 7 includes registers 8, 9 and
Register 10, register 12, address generator, transparent
It is composed of a semi-transparent processing circuit 14, a pointer generation circuit 15, a line buffer 16, and a selector 17. The names of the data stored in these registers are shown in the parentheses in FIG. 2 of the registers 8 to 12. In the register 8, an address indicating the range of the display area 30 and numerical values of the address width "X1, Y1, H1, W1"
Is remembered. "X1" and "Y1" are display areas 30
Is an address indicating the start point of, and also "W1" and "H
“1” is a numerical value indicating the width of the address in each of the x direction and the y direction from the starting point of the display area 30. In the register 9, the source image data to be superimposed on the composite image in the display area 30 in the display circuit 7, for example, the source address area in which the source image data C is stored, for example, the address and the address width indicating the range of the source address area 34 are stored. Numerical values "X2, Y2, H2, W2" are stored. At this time, the combined image stored in the display area 30 is a combination of the source image data A and the source image data B stored in the source image data areas 32 and 33. "X2 and" Y2 "are addresses indicating the starting point of the source image area 34, and" W2 "and" H2 ".
Is a numerical value indicating the width of the address in the x direction and the y direction from the starting point of the source image area 34.

The register 10 stores the numerical values "X3, Y3" of the address indicating the position where the source image data C is superimposed on the composite image in the display area 30 in the display circuit 7. Here, as shown in FIG. 4, the numerical value “X3, Y3” is a relative address indicating the position of the starting point of the source image data C superimposed on the display area 30 with the starting point of the display area 30 as the origin. In the register 11, a MODE flag indicating whether or not the source image data C to be superimposed on the composite image in the display area 30 includes transparent pixel data is set.
Here, when the MODE flag is “1”, the source image data C includes transparent pixel data, while when the MODE flag is “0”, the source image data C does not include transparent pixel data. The register 12 stores a numerical value of the transparency α (data of a ratio within the range of 0 ≦ α ≦ 1) of the semitransparent pixel data of the source image data C, which is used for the semitransparent calculation. Here, the translucent calculation is performed in the display area 30.
If the gradation data of the composite image is “D” and the gradation data of the translucent pixel data of the source image data C is “E”, the newly overlapped pixel data “R” and “G”. ，
For each luminance of “B” (Red, Green, Blue signal system), for example, R is calculated as “DR × (1−α) + ER × α”. Here, DR and ER represent the numerical values of "R" of the gradation data D and E, respectively. The above-described registers 8 to 12 are preset by the CPU for each frame image synthesizing process.

The line buffer 16 stores pixel data of a horizontal horizontal data string stored in the display area 30,
Alternatively, the pixel data of the horizontal data string of the source image data C in the horizontal direction is stored in correspondence with the scanning line on the monitor 18. That is, when the MODE flag is “1”, since the source image data C includes transparent pixel data, the display circuit 7 writes the pixel data of the corresponding horizontal data string in the display area 30 into the line buffer. On the other hand, M
When the ODE flag is “0”, since the source image data C does not include transparent pixel data, the display circuit 7 displays the pixel data of the corresponding horizontal data string of the source image data C,
The source image data C and the pixel data of the corresponding horizontal data row in the display area 30 that does not overlap are written in the line buffer. The address generator 13 causes the horizontal data string to correspond to the position of the scanning line displayed on the monitor 18 according to the output of the horizontal synchronizing signal from the display circuit 7 to the monitor 18, and displays the display area 30 and the source image data area. Three
RA for transferring this horizontal data string of corresponding vertical positions of 4 to the line buffer 16 sequentially for each pixel data.
Generate an address in M3. Further, the address generator 13 makes the pixel data corresponding to the overlapping pixel data (pixel data of the display area 30) in the horizontal data string stored in the address buffer 16 based on the numerical values stored in the registers 8 to 10, The display circuit 7 generates an address for reading the pixel data of the source image data C (fourth access processing). Pointer generation circuit 15
Generates a pointer P indicating the position in the line buffer of this pixel data transferred to the monitor 18 in synchronization with the timing of displaying the pixel data on the scanning line of the monitor 18.

The selector 17 synchronizes the pixel data read from the position indicated by the pointer P of the line buffer 16 with the pixel data output from the transparent / translucent processing circuit 14 in synchronization with the generation timing of the pointer P. It is switched (selected) which one is output to the monitor 18. In the transparent / translucent processing circuit 14, the pixel data of the source image data C is transferred from the source image data area 34 to the pointer P.
Is input in correspondence with the address generated in the address generation circuit 6 in synchronism with the generation timing of. At this time, the image finally displayed on the monitor 18 is an image in which the source image data A, B, and C are combined.

Here, when the MODE flag stored in the register 11 is "0", the transparent / semi-transparent processing circuit 14 reads the pixel data to the monitor 18,
The selector 17 is controlled to output the pixel data from the line buffer 16. On the other hand, when the MODE flag stored in the register 11 is “1”, the transparent / translucent processing circuit 14 includes the source image data C as shown below because the source image data C includes transparent pixel data. Is determined for each pixel data (arithmetic processing), and control is performed to select the pixel data of the source image data C or the pixel data output from the line buffer 16. The selection signal is output to the selector 17. That is, the transparent / semi-transparent processing circuit 14 outputs the pixel data from the line buffer 16 to the monitor 18 when the pixel data of the source image data C is transparent, and outputs the pixel data of the source image data C when the pixel data is not transparent. The pixel data of the image data C is output to the monitor 18. In the above-described arithmetic processing, one of the pixel data for one scanning line stored in the line buffer 16 and the pixel data of the source image data C corresponding to the display position of this pixel data on the display screen of the monitor 18 is used. , Or whether or not to use the pixel data resulting from the semitransparent processing is processed in dot units (each pixel data) on the display screen of the monitor 18.

The transparent / semi-transparent processing circuit 14 selects the pixel data read from the line buffer 16 to the selector 17 when the pixel data of the input source image data C is transparent, and selects the pixel data from the monitor 18. Output to. On the other hand, if the pixel data of the input source image data C is not transparent, the transparent / translucent processing circuit 14
Source image data C input to the selector 17
Pixel data is selected and output to the monitor 18. Here, each pixel data has a data structure shown in FIG. 5, for example. In FIG. 5, the flag T is a transparent flag. When it is “1”, it indicates that the pixel data is transparent, and when it is “0”, it indicates that the pixel data is non-transparent. The registers R, G, and B are composed of a plurality of bits, for example, 5 bits, and indicate the numerical values of the brightness (gradation degree) of red, green, and blue, respectively. Further, when the translucency α of the register 12 is not “0”, the transparent / translucent processing circuit 14 corresponds each pixel to the line buffer 16 with respect to all the non-transparent pixel data of the source image data C. The above-described translucent operation is performed with the pixel data (this makes it possible to omit the fifth access processing as described in the summary of the invention), and new pixel data obtained by this translucent operation Is selected, and a selection signal to be output to the monitor 18 is output to the selector 16.

The RAM arbitration circuit 102, when the drawing circuit 5 synthesizes an image in the drawing area 31 (see FIG. 3),
Under control of the drawing circuit 5, the source image data area 32,
The source image data A and B read from the source image data areas 32 and 33 are written in the drawing area 31 based on the address where the source image data A and B are arranged in the drawing area 31. Calculate the address. Further, the RAM arbitration circuit 102 transfers the pixel data of the composite image of the display area 30 to the line buffer 16 based on the address generated by the address generator 13 under the control of the display circuit 7, and the source of the source image data area 34. The pixel data of the image data C is transferred to the transparent / translucent processing circuit 14. With the above-described configuration, the drawing apparatus 1 performs image combining processing of a plurality of source image data for each frame based on the source image data loaded in the RAM, and sequentially outputs the combined images. A predetermined moving image is displayed on the monitor 107.

Next, an operation example of one embodiment will be described with reference to FIGS. 1, 2 and 3. For example, CP not shown
Suppose U starts the image processing apparatus. At this time, area 3
It is assumed that 0 is set in the drawing area and area 31 is set in the display area. Then, in the drawing area 30, the source image data A and B to be combined are respectively the source image data area 3
It has been expanded to 2,33. Further, the source image data C, which is superimposed on the composite image at the time of being output to the monitor 18, is expanded in the source image data area 34. Further, it is assumed that the image finally displayed on the monitor 18 is an image in which the source image data A, B, and C are combined. On the other hand, at this time, in parallel, within the allowable range of the bandwidth,
The pixel data of the composite image is output from the display area 31 to the line buffer 16, or the pixel data read from another source image data area (not shown) and the pixel data of the line buffer 16 are read respectively, and the register 8 The pixel data to be displayed on the monitor 18 is output based on the numerical values stored in the register 12.

Then, the transfer circuit 4 reads out the source image data, which is necessary for starting the synthesis and is not expanded in the RAM.3, from the ROM.2, and the unnecessary source image data in the RAM.3 is read. Expand by overwriting the source image data area that has been expanded.
Next, the drawing circuit 5 reads the source image data A and B from the source image data 32 and 33, respectively, and performs a combining process of the source image data A and B in the drawing area 30. When the combining processing of the source image data A and B in the drawing circuit 5 and the transfer of the displayed pixel data from the display circuit 31 to the monitor 18 are completed, the display area 3 is displayed.
1 is converted into the drawing area 31, that is, the function as the frame buffer is converted from the display area to the drawing area, and the drawing area 3
0 is converted into the display area 30, that is, the function as the frame buffer is converted from drawing to display. As a result, the drawing circuit 5 starts the generation of the composite image in the drawing area 31, and the display circuit 7 starts the process of transferring the pixel data of the composite image in the display area 30 to the monitor 18.

Next, the address generator 13 synchronizes with the horizontal synchronizing signal, and the monitor 18 corresponding to this horizontal synchronizing signal.
Area 30 output to the scanning line position on the screen of
Generate the address of the horizontal data string at. And
When the MODE flag of the register 11 is “0” via the RAM arbitration circuit 6 on the basis of the address generated by the address generator 13, the display circuit 7 determines one scanning line on the display screen of the monitor 18 based on the above address. Pixel data of the horizontal data row is read from the display area 30 and the source image data area 34, and the pixel data of the horizontal data row is stored in the corresponding positions in the line buffer 16. On the other hand, the display circuit 7, based on the address generated by the address generator 13, via the RAM arbitration circuit 6,
When the MODE flag of the register 11 is “1”, the pixel data of the horizontal data string for one scanning line on the display screen of the monitor 18 is read from the display area 30 based on the above address, and the line buffer 16 stores the horizontal data string of the horizontal data string. Pixel data is stored in corresponding positions.

At this time, the address generator 13 expands the numerical values indicating the position and range in the RAM 3 of the display area 30 stored in the register 8 and the source image data C stored in the register 9. The numerical value indicating the position and range of the existing area (source image data area 34) in the RAM 3 and the numerical value of the relative address where the source image data C is arranged in the address range of the display area 30 stored in the register 10. Based on this, the address in the RAM3 of the pixel data of the composite image of the display area 30 and the pixel data of the source image data C at the overlapping position is calculated. For example, if the source image data C is overlaid on the composite image as shown in FIG.
The position of the pixel data of the position of the point D on the composite image in the source image data area 34 is "x2, y2". Therefore, the address generator 13 determines that the start point “x1 + x” where the source image data C is arranged in the display area 30.
3, y1 + y3 "in order to correspond to the address of this start point, and the start point" x
The address of the pixel data read from the source image data C of "2, y2" is generated.

Then, the pixel data to be displayed is monitored 18
In order to output to, the pixel data of the composite image and the pixel data of the source image data C are arithmetically processed to generate the pixel data to be displayed on the display screen of the monitor 18, which is stored in the register 11 as described above. Since the calculation processing of this output differs depending on whether the MODE flag is "1" or "0", the related processing for outputting pixel data to the monitor 18 will be described below with reference to the monitor of FIG. Explanation will be given using a conceptual diagram showing the relationship between the pixel data of the composite image and the pixel data of the source image data C in each dot of a predetermined scanning line displayed on the display screen of 18. When the MODE flag stored in the register 11 is “0”, it indicates that the source image data C does not include transparent pixel data. Therefore, at a position overlapping the pixel data of the source image data C, that is, The pixel data of the composite image below the source image data is not displayed. Therefore, in the line buffer 16, the source image data C
Only the pixel data at the position not overlapping with is read from the horizontal data string corresponding to the scanning line of the display screen of the monitor 18 in the display area 30. At this time, the address generator 1
3 generates the address for reading the pixel data of the composite image from the horizontal data string of the display area 30, skips the address of the area overlapping the source image data C, and generates the source image data C as the source image data area 34. When read from, the address of each pixel data of the horizontal data row of the source image data C of the skipped portion is generated.

That is, the address generator 13 determines, for example, the address in the scanning line direction at the vertical position "y1 + y3" as
From "x1, y1 + y3" to "x1 + x3, y1 + y3" and "x1 + x3 + w2, y1 + y3" to "x1 + w1, y1
Generate up to + y3 ". Then, the display circuit 7 responds to the horizontal synchronizing signal of the monitor 18 by "x1, y1 + y3".
To "x1 + x3, y1 + y3" and "x1 + x3 + w
In the address range from "2, y1 + y3" to "x1 + w1, y1 + y3", pixel data is read from the display area 30 and written to the line buffer 16, and "x1 + x3 +"
1, y1 + y3 "to" x1 + x3 + w2-1, y1 + y3 "
In the address range up to, the pixel data of the source image data C is written in the line buffer 16. Next, when the pointer generation circuit 15 finishes storing the pixel data of the horizontal data row for one scanning line from the display area 30 to the line buffer 16, the pointer generation circuit 15 sequentially stores each pixel data of the line buffer 16. A pointer P indicating the existing address position is output. Then, the display circuit 7 responds to the output timing of the pointer P with the pixel data of the composite image stored in the line buffer 16 or the pixel data of the source image data C via the selector 17 and the monitor 18.
To each dot sequentially. That is, the line buffer 1 when the MODE flag described below is "1"
The memory access count when storing pixel data in 6 is the “access count of pixel data of all horizontal data columns of the display area 30” and the “access count of pixel data of all horizontal data columns of the source image data C”. It was added. However, the memory access count when storing pixel data in the line buffer 16 when the MODE flag is “0” is “access count of pixel data in a portion of the horizontal data string of the display area 30 that does not overlap with the source image data C”. And “the number of times of access to the pixel data of all the horizontal data strings of the source image data C”. As described above, when the MODE flag is “0”, the image processing apparatus of the present invention uses the MO described later.
Compared to the case where the DE flag is “1”, pixel data that does not need to be displayed is transferred from the display area 30 to the line buffer 26.
Since it is possible to reduce the number of memory accesses for reading, it is possible to further reduce the total number of memory accesses, provide a margin in bandwidth, and provide the bandwidth for other processing. Become.

On the other hand, the MO stored in the register 11
When the DE flag is "1", it indicates that the source image data C includes transparent pixel data or semi-transparent pixel data. Therefore, the source image data corresponding to the horizontal synchronizing signal of the monitor 18 is displayed. All the pixel data in each scanning line unit (horizontal data row) of the composite image including the position overlapping with the pixel data of C is read to the line buffer 16.
Next, when the pointer generation circuit 15 finishes storing the pixel data of the horizontal data row for one scanning line from the display area 30 to the line buffer 16, the pointer generation circuit 15 sequentially operates the line buffer 16.
A pointer P indicating the stored address position of each pixel data is output. Then, the display circuit 7 reads out the pixel data of the composite image at the address position pointed to by the pointer P, and at the timing of the pointer P, based on the address generated by the address generator 13, the source image data area 34. The pixel data of the source image data C is read from. The transparent / translucent processing circuit 14 determines whether or not the pixel data of the source image data C is transparent for each read pixel data (arithmetic processing) and selects the pixel data of the source image data C, or
A control signal for controlling whether to select the pixel data output from the line buffer 16 is output to the selector 17.
At this time, as shown in FIG. 7, the transparent / semi-transparent processing circuit 14 performs the above-mentioned comparison from the address “x1 + x3, y1 + y3” at which the composite image and the source image data overlap to “x1 + x3 +”.
w2, y1 + y3 ". The transparent / semi-transparent processing circuit 14 changes from “x1, y1 + y3” to “x1 + x3-1,
up to "y1 + y3" and "x1 + x3 + w2 + 1, y1 +
The comparison is not performed in the range from "y3" to "x1 + w1, y1 + y3", and the pixel data is read from the position indicated by the pointer P in the line buffer 16 and output to the monitor 18 via the selector 17.

When the translucency α of the register 12 is not "0" and the pixel data of the source image data C is transparent, the transparent / translucent processing circuit 14 causes the line buffer 16 to operate.
When the pixel data of the source image data C is not transparent, the pixel data read from is output to the monitor 18, and the control signal for outputting the pixel data of the source image data C to the monitor 18 is sent to the selector 17. That is,
The transparent / semi-transparent processing circuit 14 stores the pixel data of one scanning line stored in the line buffer 16 and the pixel data of the source image data C corresponding to the display position of this pixel data on the display screen of the monitor 18. Output either
That is, whether or not the pixel data of the read source image data C is transparent is confirmed in dot units (for each pixel data) by the transparency flag T of FIG. 5, and if “T = 1 (transparent)”, the composite image The pixel data is output to the monitor 18 and “T = 0
In the case of (non-transparent), a control signal for outputting the pixel data of the source image data C to the monitor 18 is sent to the selector 17, and the pixel data to be displayed on the display screen of the monitor 18 is selected.

Further, when the translucency α of the register 12 is not “0”, the transparent / translucent processing circuit 14 performs this pixel by pixel and the line buffer 16 for all the non-transparent pixel data of the source image data C. The above-mentioned semi-transparency calculation is performed with the corresponding pixel data of 1), new pixel data obtained by this semi-transparency calculation is selected, and a control signal to be output to the monitor 18 is output to the selector 16. As a result, the selector 17 sequentially outputs the pixel data of the composite image or the pixel data of the source image data C to the monitor 18 for each dot based on the control signal. As described above, according to the present invention, the final combining process of the images displayed on the display screen of the monitor 18 is not collectively performed in the drawing area, but when the pixel data is output from the display area 30 to the monitor 18. , The source image data C not included in the composite image is superimposed on the composite image in the display area 30 to generate a final composite image. Since it is possible to reduce the memory access in writing the pixel data of the data C, it is possible to prevent the problem that the composite image cannot be generated due to lack of time, and it is possible to combine more source image data. , With a margin in the bandwidth, to read new source image data from ROM · 2 in the opened bandwidth and expand it to RAM · 3. Seth processing can be performed.

[0036]

According to the present invention, the display device (monitor 1
The final composition processing of the image displayed on the display screen of 8)
When the pixel data is output from the display storage area (display area) to the display device without being collectively performed in the drawing storage (drawing area) area, it is included in the composite image in the display area. Overlay other source image data,
Since a final composite image is generated, when a composite image is created in the drawing area, it is possible to reduce memory access in writing pixel data of other source image data, so that there is no time margin. It is possible to prevent the generation of a composite image from becoming impossible, it becomes possible to combine a larger amount of source image data, and to allow a margin for the bandwidth so that new source image data is read in the opened bandwidth, You can access the memory to expand the memory.

[Brief description of drawings]

FIG. 1 is a conceptual diagram illustrating an outline of a function capable of reducing the number of accesses in the present invention.

FIG. 2 is a block diagram showing a configuration of an image processing apparatus according to an embodiment of the present invention.

FIG. 3 is a conceptual diagram showing a memory map of a buffer memory area (display area 111 and drawing area 112) and a source image data area 113 in the RAM 3 in FIG.

4 is a conceptual diagram showing a relative positional relationship between a display area 30 and a source image data area 34. FIG.

FIG. 5 is a conceptual diagram illustrating a configuration example of pixel data.

FIG. 6 is a conceptual diagram for explaining a pixel data transferred to the monitor 18, that is, a calculation process for each pixel data of the combined image and the source image data C.

FIG. 7 is a conceptual diagram for explaining a pixel data transferred to the monitor 18, that is, a calculation process for each pixel data of the composite image and the source image data C.

FIG. 8 is a block diagram showing a configuration of a conventional frame buffer type image processing apparatus.

[Explanation of Codes] 1 drawing device 2 ROM 3 RAM 4 transfer circuit 5 drawing circuit 6 RAM arbitration circuit 7 display circuit 8, 9, 10, 11, 12 register 13 address generator 14 transparent / semi-transparent processing circuit 15 pointer generation circuit 16 line buffer 17 selector 18 monitor 30, 31 display area (or drawing area) 32, 33, 34 source image data area

─────────────────────────────────────────────────── --- Continuation of the front page (56) Reference JP-A-61-99189 (JP, A) JP-A-62-182794 (JP, A) JP-A-62-239672 (JP, A) JP-A-2000-89749 (JP, A) JP 2000-284776 (JP, A) JP 2001-242848 (JP, A) JP 2002-123250 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) ) G09G 5/00-5/40

Claims (4)

(57) [Claims] 1. An image processing apparatus which synthesizes a plurality of predetermined source image data, outputs a synthesized synthesized image, sequentially displays the synthesized images on a display device, and generates a moving image. A first memory that stores a plurality of source image data used for generation; a drawing circuit that reads the plurality of source image data from the first memory and synthesizes the synthesized image to generate the synthesized image; A display circuit for outputting to a display device, and when the composite image is being composited by the drawing circuit in one storage area, the composite image composited from the other storage area is read by the display circuit, alternately. A second memory having two storage areas used for drawing or displaying, and the display circuit reads out from the storage area for display. The pixel data of the image and the other pixel data of the other source image data not included in the composite image read from the first memory are arithmetically processed for each dot of the corresponding address on the display screen of the image display device. Then, the image processing apparatus is characterized by outputting to this image display apparatus. 2. The display circuit includes a line buffer, and pixel data for one scanning line of a composite image is stored in the line buffer, and the scanning line is stored in the pixel data and the other source image data. 2. The image processing apparatus according to claim 1, wherein the other pixel data at the position corresponding to is sequentially processed. Wherein the display circuit, the result of the arithmetic processing, when the other pixel data is transparent, the alloy
When the pixel data of the composed image is output to the display device and the other pixel data is semi-transparent, a semi-transparent process is performed based on the other pixel data and the pixel data of the composite image , The pixel data obtained is output to the display device, and when the other image data is neither transparent nor semi-transparent, the other pixel data is output to the display device. 2. The image display device according to 2. 4. The display circuit indicates at which position of the composite image the other source image data is superimposed.
A storage unit that stores relative position information of this composite image and other source image data is provided. Based on this relative position information, the pixel data of the composite image and the other pixel data of the composite image on which the arithmetic processing is performed are performed. The image processing device according to claim 1, wherein the image processing device generates an address.