JPH06295171A - Image processor - Google Patents

Abstract

PURPOSE:To provide a computer device capable of executing the image processing with high functionality by providing a means deciding the priority of pictures sent from different kinds and plural image data generation units. CONSTITUTION:The picture data to be dealed respective data formats are divided to the image data and area information to be operated. Then, the decision of the priority is performed by using a priority register, a priority circuit and a selector incidental to the output control of the image data and a related image processing function. The area information containing the contents of the priority register is operated by the priority circuit, and the operated result is sent to the selector. The image data are sent to the selector, and the image data are processed according to the operated result of the area information to be output ted to a D/A converter. Then, when the number of display pixels of the image data to be dealed are different from each other, the superposition of the pictures whose number of pixels are different from each other is dealed by revising the control clock of the image processing after priority while considering the priority of the pixel at a fixed pitch.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer device having an image processing function.

[0002]

2. Description of the Related Art An image processing function performed by a conventional computer will be described below. When image processing and output are performed by a computer device, the background screen is configured in units of a pattern called a character whose unit is the raster of the CRT screen and character pitch. An example is given of a computer game device that employs an expression system in which the screen is superimposed on the background and sprites.

The image processing function of the computer game device mainly includes an external storage device, a CPU, a VRAM, a video display controller (VDC), a video encoder (VDE), and a CRT. Image data is transferred from the external storage device to the VRAM under the control of the CPU,
Image data is obtained from the VRAM, processed, and output.

The background is defined for each character by information such as display position, color and pattern, and a background attribute table (BAT) in VRAM.
And a character generator (CG).

A sprite is defined by display position, color, and pattern information for each sprite, and is managed in a data format of a sprite attribute table buffer (SATB) and a sprite generator (SG).

BAT consists of CG color and character code, and CG defines a character pattern on four sides (16-color mode). The character code is a code for generating a CG address. This code shows which CG the BAT refers to. SATB is mainly composed of a sprite color and a pattern code, and SG defines a pattern of each sprite. With this code SATB
Can see which SG refers to.

The output of the background image data is
An address is generated from the raster position, BAT is read, and a character code and a CG color code are obtained. An CG address is generated from the obtained character code, pattern data is obtained, and the pattern data is output together with the CG color code.

When outputting sprite image data, SA
Reading is sequentially performed from the beginning of the TB address. After obtaining the sprite pattern code and the SG color code, the SG address is generated from the sprite pattern code, the pattern data is obtained, and the SG color code is output together with the SG color code. Sequentially, the coordinate data designating the CRT display position of SATB and all the data in the SAT area are rewritten to change the screen display.

The superposition of the background and the sprite is performed using a priority circuit. When the sprite data and the background data are sent to the priority circuit, only the data to be displayed is output at the overlapping coordinate positions according to the instruction written in the priority register.

In order to display a plurality of sprites at the same time and to determine the priority order when the sprites overlap each other, the SAT area defining each sprite in the VRAM is arranged at an address in the order of the priority order. . In this method, the order of reading and transferring sprite data is used as a priority.

The background and sprite expression system can display moving images and still images. In addition, there is a function to display the screen data read by the scanner as a still image.

[0012]

As described above, the prior art is as follows.
The priority circuit controls the output of multiple screens created by the video display controller according to the priority order. The priority circuit processes background and sprite image data in the video display controller.

Conventionally, the background and the sprite, which have been superposed, have the same display dot cycle and are image data of exactly the same data format generated in the same image data generation unit. The background screen has one or two sides, and the combination of sprites is
Easy to determine priority. Since the image processing function is also simple, the data transfer to the priority circuit is performed by the CRT.
The speed is the same as the dot clock for screen display, and there is no need to change the speed.

However, there is a trend toward increasing the number of types of image data to be handled and expanding the image processing function in order to advance the multimedia of computer devices. For that purpose, it is necessary to control the output of screen data sent from a plurality of different types of image data generation units.
Considering the time required for image processing applied to each image data,
It is necessary to transfer the screen data from each image data generation unit to the priority circuit and determine the priority order.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a computer device capable of executing high-performance image processing by obtaining means for determining the priority order of screens sent from a plurality of image data generation units of different types.

[0016]

In order to solve the above problems, according to the present invention, screen data of each data format to be handled is divided into image data and surface information for calculation. The priority order is determined by using a priority register and a priority circuit, and a selector having an output control of image data and a related image processing function.

The surface information including the contents of the priority register is calculated by the priority circuit, and the calculation result is sent to the selector. The image data is sent to the selector, the image data is processed according to the calculation result of the surface information, and the image data is output to the D / A converter.

When the number of display pixels of the image data to be handled is different, the priority of the pixels is taken into consideration at a constant pitch, and the superposition of screens having different numbers of pixels is dealt with. The processing time in the selector and the priority circuit is changed corresponding to the change in the frequency of the dot clock due to the change in the number of pixels.

[0019]

Embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram of an apparatus according to an embodiment of the present invention.

A soft recording medium such as a CD-ROM, a 32-bit CPU, a control unit mainly for image / audio data transfer control and an interface of each device, an image data expansion / conversion unit, an image data output unit, an audio data output unit, Video encoder unit, VD
It is composed of a P unit and the like. K for each unit
-Has memory such as RAM, M-RAM, R-RAM, V-RAM.

The CPU directly drives the DR through the memory support.
It has a memory control function that can control AM and an I / O control function that can communicate with various peripheral devices through an I / O port. It also has a timer, parallel input / output port, and interrupt control mechanism.

The display data written in the VRAM by the CPU is read out by the VDP unit and sent to the video encoder unit to be displayed on the screen.

The controller unit has a built-in SCSI controller, and an external storage device such as a CD-ROM drives the S unit.
Capture data such as images and sounds via the CSI interface. The captured data is once K-RA
Buffered in M.

The controller unit has a built-in DRAM controller, and the function allows the data stored in the K-RAM to be read at a predetermined timing.

The background image data of the natural image is sent to the video encoder unit after being subjected to priority determination in the unit of dot data in the controller unit.

The data-compressed moving image (full color, palette) data is sent to the image data expansion unit. The image data decompression unit decompresses the data and sends it to the video encoder unit.

In the video encoder unit, the VDP image sent from the VDP unit, the controller unit, and the image data expansion unit, the background image of the natural image, the superimposing process of the moving image (full color, palette) data, the color palette reproduction, and the special effect are performed. The image signal, which has been subjected to processing, D / A conversion, and the like, is output, and finally an image signal encoded into an NTSC signal is output by an external circuit.

ADP read from a CD-ROM or the like
The CM audio data is buffered in the KRAM like the image data, and then sent to the audio data output unit by the controller unit and reproduced.

A block diagram of the video encoder unit is shown in FIG. The video encoder unit has a sync signal generation circuit, a color palette RAM, a priority calculation circuit, a cellophane calculation circuit, and a video signal D / C on the IC chip.
It is made by integrating an A converter, an 8 / 16-bit data bus (M-bus) interface, a VDP interface, a controller unit interface, and an image data expansion unit interface.

An 8 / 16-bit data bus (M-bus) interface is an I / F for determining whether the operation on the video encoder unit side is 8 bits or 16 bits according to the data width of the data bus of the processing system including the CPU.
It is a switching circuit.

The VDP interface is an interface for data sent from two VDPs, and normally receives data from the upper VDP, and receives data from the lower VDP only when the upper VDP outputs chroma key data.

The color palette RAM converts a video data input signal into a YUV digital signal.

The video encoder unit has registers (16 bits × 24 lines) inside. By accessing these from the CPU, functions such as operation mode setting and color palette read / write are fulfilled.

The color palette RAM will be described.
The color palette data is converted into YUV data by the color palette RAM and becomes data that can be actually displayed. The color palette RAM is a color information table composed of 512 addresses in the address direction and 16 bits in the data direction.

As shown in FIG. 3, a color palette RAM
Is composed of a RAM having 512 addresses in the address direction and 16 bits in the data direction. One address has data of one color and can have data of 512 colors in total.

Data of one color (one address) is composed of Y8 bits, U4 bits and V4 bits as shown below, and can represent 65536 colors. The Y data indicates brightness, has a value of 00 (black) to FFh (white), and the U data is blue-yellow color difference information, has a value of 0 to 15, and is 8 in the case of colorless. V data is red-green color difference information, 0 to
It has a value of 15 and is 8 when it is colorless.

After resetting, YY = 00h, U = 0h, and V = 0h are set in the color palette address 0. Therefore, it is necessary to set the color data to the color palette address 0 again after the reset.

A method of setting YUV data in the color palette RAM will be described. The contents of the color palette RAM are written by the CPU, read by the color palette information from the VDP, the controller unit, and the image data expansion unit, and converted into Y, U, and V data. The CPU can also read the contents of the color palette RAM if necessary.

Writing to the color palette RAM (when writing data continuously) is performed as follows.

1step: The register number 01h of the color palette address register (CPA) is set in the address register (AR) 2step: Color palette address register (CP)
Write the start address in A) 3step: Register number 02 of color palette data write register (CPW) in address register (AR)
Set h. 4step: Write data to the color palette data write register. (CPA is incremented.) 5step: Write data to the color palette data write register. (CPA is incremented.)

When the 8-bit bus is selected, writing to the data write register is performed in the order of the lower byte and the upper byte. When the upper byte is written, the actual writing to the internal register is performed and CPA is incremented. .

When the 8-bit bus is selected, the reading from the data read register is performed in the order of the lower byte and the upper byte, and when the upper byte is read, the actual writing to the internal register is performed and the CPA is incremented. To do.

The display of color palette data will be described. The color palette data surface of the VDP, the controller unit, and the image data decompressing unit stores the color palette data in Y, U, and
Convert to V data and display the actual image.

Since there is only one set of color palette RAM, all surfaces using color palette data use the same color palette RAM. However, by utilizing the color palette address offset register, the color palette address to be used can be set for each surface.

In the display processing, the priority processing block first determines the surface to be displayed in dot units. If the surface is the color palette data surface, the color palette address offset value of the surface is read from the register, and twice the value and the color palette data are added to calculate the color palette address.

The data designated by the calculated color palette address becomes the color of the dot, and the Y, U and V data are sent to the next functional block.

The color palette address is determined by calculating the color palette data and the color palette offset value set for each surface. Therefore, even if the color palette data is the same, different colors can be output if the surfaces are different.

The color palette offset register for VDP is one set, and the upper VDP and the lower VDP use the same register. If the color palette address exceeds 511, the 10th bit is simply truncated and follows the 0 address. This is shown in FIG. The color palette address offset is not relevant when the CPU accesses the color palette RAM.

From each LSI, the detailed color palette data as shown in FIG. 5 is sent. When calculating the color palette address, the palette bank number is simply treated as the upper bits of the palette number, and the palette bank number and palette number are not distinguished. Therefore, all the 8-bit data in each of the modes named above are treated as color palette data.

In the embodiment of the present invention, the video encoder is provided with the priority function, and the image dot information at that time sent from each of the VDP, the controller unit and the image data expansion unit is designated in the priority register. The image dots to be displayed are determined by processing according to the priority order of the screens.

The screen configuration of the image processing apparatus according to the embodiment of the present invention has a VDP having two surfaces, a sprite (SP) surface and a background (BG) surface, and a controller unit having a BM.
G0 surface, BMG1 surface, BMG2 surface, BMG3 surface, 4 surfaces,
The image data expansion unit has one of the IDCT / RL surfaces.

The video encoder in the apparatus of the embodiment can connect two VDPs. Two VDPs are selected in the input interface portion. Normally, the upper VDP is selected, and the lower VDP is selected only when the upper VDP outputs chroma key data.

Since the priority register of the VDP SP / BG and the controller units BMG0 to BMG3 cannot be changed only by the priority register of the video encoder in this example, they are changed together with the setting of each unit.

In the priority process in the video encoder, the priority of each LSI is determined dot by dot depending on the surface information and priority register value sent from each device of the VDP, the controller unit, and the image data expansion unit, and whether the data is chroma key. Decide

FIG. 6 is an explanatory diagram of the priority processing in the 256 dot mode. Dot clock 4 here
Processing is performed with double the clock, and priority processing is performed along with special processing such as chroma key processing and cellophane processing.

In the 320-dot mode, the controller unit and the image data expansion unit are 256 dots, VD
Since P is 320 dots, the surface to be displayed is determined in a cycle of 21 Mhz, the surface (device) is selected, and it is immediately displayed.

The chroma key function (transparency processing) will be described. The chroma key function (transparency processing) is a function of treating a part of a certain surface as transparent and displaying a low priority surface on the transparent portion.

Specifically, the color (key color) determined to be transparent is determined, and the portion using that color becomes transparent. The key color is color palette data for the surface or IDCT
-The handling differs depending on whether it is YUV data or YUV data of the controller unit.

When the chroma key is not used, the key color is not used when creating a picture. FIG. 7 shows an explanatory diagram of the chroma key.

On the color pallet data side, the color pallet data 0 is transparent on any run mode of the VDP, the controller unit, and the image data decompression unit in any color mode. In VDP, palette number 0 becomes transparent in all color palette banks.

On the color palette data side of the controller unit, the controller unit may perform chroma key determination and may send an invalid signal.

On the controller unit-YUV data surface (16M color, 64K color mode), if Y data of YUV data is 00h, regardless of the UV value,
The dot becomes transparent. Y at the part you don't want to be transparent
It is necessary to add 01h to the data so that the data will not be 00h.

On the IDCT-YUV data surface, the color in the range set in the chroma key register becomes transparent.

The chroma key portion of the surface having the lowest priority is processed as follows. In the chroma key part of the surface with the lowest priority, the next surface with the priority is displayed.

Therefore, in a portion where all surfaces including the surface of YUV data are transparent, the surface which comes next with priority is displayed. Similarly, in the case of cellophane processing, the chroma key portion of the surface having the lowest priority is processed. FIG. 8 summarizes the above processing.

The cellophane function is a function of displaying the upper image and the lower image in a mixed manner when the images are combined according to the priority in the video encoder of the present invention.

For example, when the cellophane on the 0th surface of the controller unit is turned on, the surface with a lower priority is mixed with the image on the 0th surface of the controller unit, so that the 0th surface of the controller unit is displayed as translucent. To be done.

Since it is possible to change the mixing ratio of images, fading in / out of images and smooth switching of images can be realized.

The cellophane coefficient is 9 from 0/8 to 8/8.
There are stages, and the degree of cellophane is changed by setting the numerator value. The coefficient setting must be done by software.

In the cellophane coefficient register, the six parameters are in one set, and there are three sets. When setting cellophane on a certain surface, set cellophane coefficient register numbers (1 to 3) to
Write to the specified location. If 0 is set here, the cellophane on that side is turned off. The cellophane coefficient register values 9 to F are not supported and are not set.

In the chroma key part of the surface to be overlapped,
The cellophane calculation is not executed and the normal chroma key processing is performed. Also, the cellophane function can use the following functions.

As a multiple cellophane function, cellophane can be further applied to the surface on which cellophane is applied. As a front cellophane function, you can change the color tone and brightness of the entire screen by applying cellophane with a preset color.

The surface with the lowest priority as the back cellophane function has no opponent to apply cellophane, so cellophane is normally disabled. However, when the back cellophane function is used, cellophane is displayed with a preset color for that surface. You can call.

As sprite special processing, on the sprite surface, cellophane OF / OFF can be set according to the palette bank number used by the sprite to be displayed. Set ON / OFF of cellophane calculation for each pallet bank number.

FIG. 9 is a conceptual diagram of cellophane processing. The process is performed for each dot, and the VDP, the controller unit, and the image data expansion unit correspond to any one of 1, 2, and 3, respectively. This correspondence is based on each LS
Depending on the priority of the surface output by the I unit,
It is determined for each dot.

For example, in a certain dot, if the priority is VDP> controller unit> image data expansion unit, VDP if it is, and the controller unit is the image data expansion unit.

If the surface (for example, the BMG1 surface of the controller unit) is on cellophane, cellophane processing is performed between the surfaces. The coefficient of cellophane processing is the value of the coefficient register set for the plane.

Also, if cellophane is turned on on the surface (eg, BG surface), cellophane processing is performed between the cellophane processing result and the result of cellophane processing. If the cellophane processing on the surface of is off, the surface of is hidden by the surface of, so the cellophane processing is performed only between the surface of and.

However, in the chroma key part of the surface of, the surface of can be seen without being hidden. Even if cellophane processing is set on the side of, it becomes invalid. The OF / OFF of cellophane is also determined for each dot depending on the surface.

The same device (VD
P, controller unit, image data expansion unit)
It is not possible to calculate cellophane between the surfaces that are cellophane. For example, the BMG of the controller unit
Cellophane calculation cannot be performed between the first surface and the BMG2 surface. Also, cellophane calculation between the sprite surface of VDP and the BG surface of VDP cannot be performed.

This is V when considering one dot unit.
Since the DP and controller units only output 1-dot data of one screen selected by their internal priority, they cannot perform cellophane calculation with other surfaces of the same device.

Each of the front cellophane and the back cellophane has one surface having a single-color surface (fixed color surface), and has a function of performing cellophane calculation with the surface. The color of the fixed color surface is set in the fixed color register.

The front cellophane function is a function for performing a fixed color surface and cellophane calculation after the cellophane processing of the surface from the VDP, the controller unit and the image data expansion unit is completed. The value of the coefficient register 1 is used as the coefficient of the cellophane calculation. FIG. 10 is an explanatory diagram of the front cellophane.

The back cellophane function is a function of performing cellophane processing on the surface having the lowest priority among the VDP, the controller unit, and the image data expansion unit and the fixed color surface, and processing the surface having the next priority. As the coefficient, the value of the coefficient register set on the surface is used. FIG. 11 is an explanatory diagram of a back cellophane.

Basically, all sprites are subjected to cellophane treatment, but it is possible to prevent cellophane treatment of only specific sprites by the following method.

The color palette bank number used by the sprite which is not desired to be subjected to cellophane processing is set to cellophane processing OFF in the SP sprite individual setting register. Then, the dot of the sprite using that color palette bank number operates as if the cellophane on the sprite surface is turned off.

However, since this function only functions at the time of cellophane calculation on the sprite surface, if cellophane processing is set on a surface having a higher priority than the sprite surface, any sprite will be the target of cellophane during the cellophane processing. .

The synchronizing signal generating function of the video encoder of the present invention will be described. The video encoder of the present invention has a built-in synchronizing signal generation circuit, and by inputting a color subcarrier frequency of 12 times, dot clocks to peripheral ICs, -HSYNCA, HSYNC of horizontal synchronizing signals.
B, HSYNC, and vertical sync signal -VSYNC
Is output.

The function of the internal register of the video encoder of the present invention will be described. Registers are addressed indirectly using address registers. Functions of Internal Register (1) Address Register (AR) As shown in FIG. 12, the address register (AR) specifies the registers R00 to R15 inside the video encoder. When A1 is at "L" level, AR is selected by writing to the video encoder. When writing or reading to R00 to R15, first, the number of the register designated in AR is written.

(2) Status register (SR) When A1 is at the "L" level, the status register is selected when the video encoder is read. In addition to the value of the address register, the raster number being displayed and information on the display surface of the interlace can be obtained. The status register is shown in FIG.

A. AR (bits 0 to 4) Current address register value.

B. RASTERCOUNT (bit5
~ 13) Indicates the raster number currently displayed on the CRT. Display period is 2
It is from 2 to 261. It should be noted that the scanning line number defined by the NTSC signal does not match. Further, during external synchronization, when the external synchronization signal is disturbed, it becomes 1FFh.

C. O / E (bit 14) Indicates whether the screen currently displayed on the CRT in the interlaced mode is an odd field or an even field. 0: Even,
1: Odd.

D. DISP (bit 15) Indicates whether the video encoder is currently in the display period or in the non-display period (H blank, V blank). 0:
Not displayed, 1: Displayed.

(3) Control register (CR: R0
0) Bits 8 to 14 are valid from the next horizontal period, and the others are valid from the next vertical period. The control register is a register that sets the display mode of the video encoder. FIG. 14 shows the control register.

A. DCC (bit 0, 1) FIG. 15 shows interlaced / non-interlaced mode switching.

B. EX Set to 1 to perform external synchronization. Free-runs until the external sync signal is detected, and locks when the sync signal with the correct cycle is detected. When 0 is set, external synchronization is released, but if the external synchronization signal is severely disturbed, it may not be released during that time. 0 after reset
Is set.

C. It is a bit for displaying DC7 VDP in horizontal 320 dots. 1
When set to, horizontal 320 dots display is obtained. In this mode, the dot clock for VDP only becomes 7 MHz, and the cellophane function is disabled.

D. Blanking (bits 8 to 14) This is a bit for setting whether or not to display each screen on the screen. It will be effective from the next horizontal period.

R00 bit8 0: turn off BG
1: Display BG R00 bit9 0: Turn off SP 1: S
Display P R00 bit10 0: BMG0 is erased 1: B
Display MG0 R00 bit11 0: BMG1 is erased 1: B
Display MG1 R00 bit12 0: BMG2 is erased 1: B
Display MG2 R00 bit13 0: BMG3 is erased 1: B
Display MG3 R00 bit14 0: IDCT / RL Erase image 1: IDC
Display T / RL image

In the case of all blanking (setting all bits 8 to 14 to 0 = reset state), black (Y = 00h, U = 80h, V = 80h) is output to the YUV output.

(4) Color palette address register (CPA: R01) The color palette address register is a register for setting the color palette address when the CPU accesses the color palette RAM. FIG. 16 shows the structure of the register.

The color palette data write register and the color palette data read register address the color palette with this color palette address register and read / write data.

Once data is set, the color palette address register is automatically incremented each time the color palette data write and color palette data read registers are accessed.

(5) Color palette data write register (CPW: R02) The color palette data write register shown in FIG.
It is a data write register when the CPU writes data in the color palette RAM.

The data is written to the color palette address indicated by CPA. The data is set in a positive integer format with YUV. Regarding UV, since the D / A converter has 8 bits, it is internally handled with 8 bits with the lower 4 bits set to 0000.

Since the color palette address register has the automatic increment function, data can be continuously written.

When the data bus is 8 bits, since the actual writing to the register is performed at the time when the upper byte is written, the writing must be performed in the order of the lower byte and the upper byte. The CPA is also incremented after writing the upper byte.

(6) Color palette data read register (CPR: R03) The CPU reads the color palette data read register from the color palette address register indicated by the color palette address register. Since the color palette address register has an automatic increment function, data can be read continuously.

When the data bus is 8 bits, the upper byte is read and then incremented. Therefore, it is necessary to read the lower byte and the upper byte in this order.

(7) Color palette address offset register Color palette address offset register 1
Each side of P is a register that indicates from which color palette address to use the color palette. FIG. 18 shows a register.

In practice, the set value is doubled to obtain the color palette address offset value. Each set address offset value becomes valid from the next horizontal display period.

SP color palette address = SP color palette data + (SP color palette offset ×
2)

BG color palette address = BG color palette data + (BG color palette offset ×)
2)

The color palette address offset register 2 shown in FIG. 19 is a register for instructing which color palette to use from the side of the color palette data from the controller unit. Here, BMG
0, BMG1 is set.

In practice, the set value is doubled to obtain the offset value of the color palette address. Each set address offset value becomes valid from the next horizontal display period.

BMG0 color palette address = BMG
0 color palette data + (BMG0 color palette address offset x 2)

BMG1 color palette address = BMG
1 color palette data + (BMG1 color palette address offset x 2)

The color palette address offset register 3 of FIG. 20 is a register for instructing which color palette to use from the side of the color palette data from the controller unit.

Here, BMG2 and BMG3 are set. Actually, the set value is doubled to obtain the offset value of the color palette address. Each set address offset value becomes valid from the next horizontal display period.

BMG2 color palette address = BMG
2 color palette data + (BMG2 color palette address offset x 2)

BMG3 color palette address = BMG
3 color palette data + (BMG3 color palette address offset x 2)

The color palette address offset register 4 shown in FIG. 21 is a register for instructing from which number the color palette used by the run-lens plane from the image data expansion unit. Actually, the set value is doubled to obtain the offset value of the color palette address.

Each address offset value that has been set becomes effective from the next horizontal display period. Color palette address of image data expansion unit = image data expansion unit color palette data + (image data expansion unit color palette address offset × 2).

(8) Priority register Priority registers 1 and 2 shown in FIGS.
Is a register that specifies the priority of the screen and is 3 bits (0
(Numbers from 1 to 7), the higher the numerical value, the higher the priority. However, do not set the same value in multiple registers.

(9) Chroma key register (used on IDCT surface) The chroma key Y (luminance) register shown in FIG.
It is a register showing the upper limit and the lower limit of the Y component in the chroma key processing of the T surface.

The data format is a positive integer and black = 00.
H, white = FFH. The set data becomes valid from the next horizontal display period.

The chroma key U (color difference) register shown in FIG. 25 is an upper limit of the U component in chroma key processing on the IDCT surface.
This is a register indicating the lower limit. The data format is a positive integer (black = 00H, white = FFH). The set data becomes valid from the next horizontal display period.

The chroma key V (color difference) register shown in FIG. 26 has an upper limit of the V component in the chroma key processing on the IDCT surface.
This is a register indicating the lower limit. The set data becomes valid from the next horizontal display period.

(10) Fixed color register (CCR: R
0D) The fixed color register is a register used for front cellophane and back cellophane in cellophane processing, and as shown in FIG. 27, Y8 bit, U4 bit, V4
A color is designated by each bit data. Set the data format as a positive integer. The set data becomes valid from the next horizontal display period.

(11) Cellophane surface setting register (BL
E: R0E) The cellophane surface setting register is a register for performing each setting in the cellophane process as shown in FIG.
The set data becomes valid from the next horizontal display period.
29 to 35 show details of each data in the register.

(12) SP Cellophane Individual Setting Register (SPBL: R0F) The SP cellophane individual setting register of FIG. 36 is a register used in sprite special processing in the cellophane function.

Cellophane processing is not applied to sprites using color palette banks (blocks) in which cellophane is set to OFF by this register. In the cellophane surface setting register, this register is valid only when the cellophane on the sprite surface is ON.

(13) Cellophane Coefficient Register FIG. 37 shows the cellophane coefficient register 1A. The cellophane coefficient registers are (1A, 1B), (2A, 2B),
Used in a pair of (3A, 3B), each coefficient of YUV has 9 levels from 0/8 to 8/8. The value of the numerator is set in the register.

[0135]

As described above, according to the present invention, it is possible to determine and output the priority order of images from a plurality of different image data generating units. Even when the number of display pixels of image data is different, it is possible to superimpose screens having different numbers of pixels by determining the priority order of the pixels at a constant pitch. In addition to the priority function, image processing such as cellophane processing and chroma key processing can be executed. Therefore, there is an effect that it is possible to cope with a change in the number of pixels accompanying the improvement of the resolution for the purpose of improving the image quality, and to perform complicated and advanced screen composition.

[Brief description of drawings]

FIG. 1 is a block diagram of an apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram of a video encoder unit used in the image processing apparatus of the present invention.

FIG. 3 is a configuration diagram of a color palette RAM.

FIG. 4 is an explanatory diagram of a color palette address.

FIG. 5 is a table of color palette data of each unit.

FIG. 6 is an explanatory diagram of priority processing in a 256 dot mode.

FIG. 7 is an explanatory diagram of chroma key processing.

FIG. 8 is a data flow diagram in cellophane calculation.

FIG. 9 is a conceptual diagram of cellophane processing.

FIG. 10 is an explanatory diagram of a front cellophane.

FIG. 11 is an explanatory diagram of a back cellophane.

FIG. 12 is an explanatory diagram of an address register.

FIG. 13 is an explanatory diagram of a status register.

FIG. 14 is an explanatory diagram of a control register.

FIG. 15 is an explanatory diagram of an interlaced / non-interlaced mode.

FIG. 16 is an explanatory diagram of a color palette address register.

FIG. 17 is an explanatory diagram of a color palette data write register.

FIG. 18 is an explanatory diagram of a color palette address offset register.

FIG. 19 is an explanatory diagram of a color palette address offset register.

FIG. 20 is an explanatory diagram of a color palette address offset register.

FIG. 21 is an explanatory diagram of a color palette address offset register.

FIG. 22 is an explanatory diagram of a priority register.

FIG. 23 is an explanatory diagram of a priority register.

FIG. 24 is an explanatory diagram of a chroma key Y (luminance) register.

FIG. 25 is an explanatory diagram of a chroma key U (color difference) register.

FIG. 26 is an explanatory diagram of a chroma key V (color difference) register.

FIG. 27 is an explanatory diagram of a fixed color register.

FIG. 28 is an explanatory diagram of a cellophane surface setting register.

FIG. 29 is an explanatory diagram of a cellophane surface setting register.

FIG. 30 is an explanatory diagram of a cellophane surface setting register.

FIG. 31 is an explanatory diagram of a cellophane surface setting register.

FIG. 32 is an explanatory diagram of a cellophane surface setting register.

FIG. 33 is an explanatory diagram of a cellophane surface setting register.

FIG. 34 is an explanatory diagram of a cellophane surface setting register.

FIG. 35 is an explanatory diagram of a cellophane surface setting register.

FIG. 36 is an explanatory diagram of an SP cellophane individual setting register.

FIG. 37 is an explanatory diagram of a cellophane coefficient register.

Claims (1)

[Claims] 1. A computer image processing apparatus comprising means for determining a display priority of a plurality of types of image data from a plurality of image data generation units, wherein the display priority is set according to the number of display pixels of the image data to be processed. An image processing apparatus comprising a clock switching means for controlling determination and subsequent image processing.